xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.898811                       # Number of seconds simulated
sim_ticks                                1898811181000                       # Number of ticks simulated
final_tick                               1898811181000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 163774                       # Simulator instruction rate (inst/s)
host_op_rate                                   163774                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5540525376                       # Simulator tick rate (ticks/s)
host_mem_usage                                 339592                       # Number of bytes of host memory used
host_seconds                                   342.71                       # Real time elapsed on the host
sim_insts                                    56127436                       # Number of instructions simulated
sim_ops                                      56127436                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           739584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24165760                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           241984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1058688                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28856384                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       739584                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       241984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          981568                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7824192                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7824192                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             11556                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            377590                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41412                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3781                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             16542                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                450881                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          122253                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122253                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              389498                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12726784                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1395804                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              127440                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              557553                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15197079                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         389498                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         127440                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             516938                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4120574                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4120574                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4120574                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             389498                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12726784                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1395804                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             127440                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             557553                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19317653                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        450881                       # Total number of read requests seen
system.physmem.writeReqs                       122253                       # Total number of write requests seen
system.physmem.cpureqs                         582476                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28856384                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7824192                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28856384                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7824192                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       66                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               3389                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28644                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 28625                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 28393                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 28250                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 28253                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 28243                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 28343                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 28155                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28192                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 27999                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                28056                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27883                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27988                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                28022                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27871                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27898                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  8087                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7991                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7846                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7763                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7721                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7658                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7765                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7698                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7705                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7559                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7625                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7394                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7457                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7400                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7239                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7345                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                        1873                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1898811160000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  450881                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                 124126                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 3389                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    320280                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     33102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      7745                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2959                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2701                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2699                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2644                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2576                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1519                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1446                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1411                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1353                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1373                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1404                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1608                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1496                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      924                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      760                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     8261632913                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               16092226663                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2254075000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5576518750                       # Total cycles spent in bank access
system.physmem.avgQLat                       18325.99                       # Average queueing delay per request
system.physmem.avgBankLat                    12369.86                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  35695.85                       # Average memory access latency
system.physmem.avgRdBW                          15.20                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.12                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.20                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.12                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                         8.51                       # Average write queue length over time
system.physmem.readRowHits                     422765                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93696                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.78                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.64                       # Row buffer hit rate for writes
system.physmem.avgGap                      3313031.79                       # Average gap between requests
system.l2c.replacements                        343964                       # number of replacements
system.l2c.tagsinuse                     65331.328526                       # Cycle average of tags in use
system.l2c.total_refs                         2620978                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        408975                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.408651                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    5576145752                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53755.791166                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4185.940391                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          5467.030556                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          1355.812299                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data           566.754114                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.820248                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.063872                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.083420                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.020688                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.008648                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996877                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             717909                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             533580                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             356656                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             291510                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1899655                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          844133                       # number of Writeback hits
system.l2c.Writeback_hits::total               844133                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             124                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              89                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 213                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            33                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            33                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                66                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           138119                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            53788                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               191907                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              717909                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              671699                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              356656                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              345298                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2091562                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             717909                       # number of overall hits
system.l2c.overall_hits::cpu0.data             671699                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             356656                       # number of overall hits
system.l2c.overall_hits::cpu1.data             345298                       # number of overall hits
system.l2c.overall_hits::total                2091562                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            11558                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           272086                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3797                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1924                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289365                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2537                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           537                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3074                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           59                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           99                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             158                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         105872                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          14967                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             120839                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             11558                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            377958                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3797                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             16891                       # number of demand (read+write) misses
system.l2c.demand_misses::total                410204                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            11558                       # number of overall misses
system.l2c.overall_misses::cpu0.data           377958                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3797                       # number of overall misses
system.l2c.overall_misses::cpu1.data            16891                       # number of overall misses
system.l2c.overall_misses::total               410204                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    785741000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  12284482500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    291007000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    130325998                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    13491556498                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       572500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1115999                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1688499                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       252000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        68000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       320000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6919340499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1319798500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   8239138999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    785741000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  19203822999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    291007000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1450124498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21730695497                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    785741000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  19203822999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    291007000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1450124498                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21730695497                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         729467                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         805666                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         360453                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         293434                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2189020                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       844133                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           844133                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2661                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          626                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3287                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           92                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          132                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           224                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       243991                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        68755                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           312746                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          729467                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1049657                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          360453                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          362189                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2501766                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         729467                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1049657                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         360453                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         362189                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2501766                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015844                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.337716                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010534                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.006557                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.132189                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.953401                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.857827                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.935199                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.641304                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.750000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.705357                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.433918                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.217686                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.386381                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015844                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.360078                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010534                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.046636                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.163966                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015844                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.360078                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010534                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.046636                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.163966                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67982.436408                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 45149.263468                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76641.295760                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 67737.005198                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 46624.700631                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   225.660229                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2078.210428                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   549.283995                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4271.186441                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   686.868687                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2025.316456                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65355.717272                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88180.563907                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 68182.780385                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 67982.436408                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 50809.410038                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76641.295760                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 85851.903262                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52975.337873                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 67982.436408                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 50809.410038                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76641.295760                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 85851.903262                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52975.337873                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               80731                       # number of writebacks
system.l2c.writebacks::total                    80731                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            16                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        11557                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       272086                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3781                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1923                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289347                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2537                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          537                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3074                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           59                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           99                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          158                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       105872                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        14967                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        120839                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        11557                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       377958                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3781                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        16890                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           410186                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        11557                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       377958                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3781                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        16890                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          410186                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    641619734                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   8951011686                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    243130799                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    134913103                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   9970675322                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     25435503                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5378029                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     30813532                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       621055                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1001098                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1622153                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5629376132                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1136913783                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   6766289915                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    641619734                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  14580387818                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    243130799                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1271826886                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16736965237                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    641619734                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  14580387818                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    243130799                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1271826886                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16736965237                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    929565000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    460091000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1389656000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1573030500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    890243000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2463273500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2502595500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1350334000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3852929500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015843                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.337716                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010490                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.006553                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.132181                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.953401                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.857827                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.935199                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.641304                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.750000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.705357                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.433918                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.217686                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.386381                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015843                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.360078                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010490                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.046633                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.163959                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015843                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.360078                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010490                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.046633                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.163959                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55517.844942                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 32897.729710                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64303.305739                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70157.619865                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 34459.231725                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.819078                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.951583                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10023.920625                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10526.355932                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10112.101010                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10266.791139                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53171.529130                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75961.367208                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 55994.256118                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55517.844942                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38576.740850                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64303.305739                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75300.585317                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40803.355641                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55517.844942                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38576.740850                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64303.305739                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75300.585317                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40803.355641                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41698                       # number of replacements
system.iocache.tagsinuse                     0.398700                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1706437655000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.398700                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.024919                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.024919                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
system.iocache.overall_misses::total            41728                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21267998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21267998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10658856806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10658856806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10680124804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10680124804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10680124804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10680124804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120840.897727                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120840.897727                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256518.502262                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256518.502262                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255946.242427                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255946.242427                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255946.242427                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255946.242427                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        284980                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27128                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.505013                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41522                       # number of writebacks
system.iocache.writebacks::total                41522                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12115250                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12115250                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8496857845                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8496857845                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8508973095                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8508973095                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8508973095                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8508973095                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203915.191119                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203915.191119                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               10581841                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          8959361                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           281985                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             7046138                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                4567974                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            64.829471                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 656046                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             29257                       # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7560815                       # DTB read hits
system.cpu0.dtb.read_misses                     30461                       # DTB read misses
system.cpu0.dtb.read_acv                          538                       # DTB read access violations
system.cpu0.dtb.read_accesses                  623625                       # DTB read accesses
system.cpu0.dtb.write_hits                    5040625                       # DTB write hits
system.cpu0.dtb.write_misses                     7520                       # DTB write misses
system.cpu0.dtb.write_acv                         334                       # DTB write access violations
system.cpu0.dtb.write_accesses                 206551                       # DTB write accesses
system.cpu0.dtb.data_hits                    12601440                       # DTB hits
system.cpu0.dtb.data_misses                     37981                       # DTB misses
system.cpu0.dtb.data_acv                          872                       # DTB access violations
system.cpu0.dtb.data_accesses                  830176                       # DTB accesses
system.cpu0.itb.fetch_hits                     911527                       # ITB hits
system.cpu0.itb.fetch_misses                    30644                       # ITB misses
system.cpu0.itb.fetch_acv                         921                       # ITB acv
system.cpu0.itb.fetch_accesses                 942171                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                        89753559                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          21107693                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      54367118                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   10581841                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5224020                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10262063                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1458036                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              30903552                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               30207                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       199263                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       186050                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles           96                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6657299                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               195043                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          63623646                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.854511                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.189260                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                53361583     83.87%     83.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  672459      1.06%     84.93% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1316592      2.07%     87.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  583007      0.92%     87.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2295308      3.61%     91.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  445844      0.70%     92.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  472664      0.74%     92.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  743494      1.17%     94.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3732695      5.87%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            63623646                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.117899                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.605738                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                22232367                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             30357900                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9303163                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               825009                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                905206                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              419214                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                29823                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              53368764                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts                92723                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                905206                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                23093913                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               11627753                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      15736016                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  8768275                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3492481                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              50503220                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6655                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                393829                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1341574                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           33876980                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             61564678                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        61250531                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           314147                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             29813717                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4063255                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1268860                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        187899                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  9409132                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7922191                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5257693                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads           964170                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          651506                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  44858999                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1558626                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 43884207                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            67322                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        4967350                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2566909                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1055206                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     63623646                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.689747                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.329677                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           43919799     69.03%     69.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            9075335     14.26%     83.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4098408      6.44%     89.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2614119      4.11%     93.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2006211      3.15%     97.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1055812      1.66%     98.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             551217      0.87%     99.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             263467      0.41%     99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              39278      0.06%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       63623646                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  62740     10.88%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                271097     47.03%     57.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               242616     42.09%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3777      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             30137882     68.68%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               45897      0.10%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              14285      0.03%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1879      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             7870096     17.93%     86.76% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5096964     11.61%     98.37% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            713427      1.63%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              43884207                       # Type of FU issued
system.cpu0.iq.rate                          0.488941                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     576453                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.013136                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         151584762                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         51176195                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     43017955                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             451072                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            219118                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       212749                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              44220901                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 235982                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          487348                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads       958085                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2941                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        10552                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       366818                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        13186                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       117811                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                905206                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8069118                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               677733                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           49115212                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           536411                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7922191                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5257693                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1375945                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                564143                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 4652                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         10552                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        138850                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       301409                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              440259                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             43556869                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              7611218                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           327337                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      2697587                       # number of nop insts executed
system.cpu0.iew.exec_refs                    12670581                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 6879787                       # Number of branches executed
system.cpu0.iew.exec_stores                   5059363                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.485294                       # Inst execution rate
system.cpu0.iew.wb_sent                      43311636                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     43230704                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 21537449                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 28771492                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.481660                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.748569                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        5358562                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         503420                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           412035                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     62718440                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.696169                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.614251                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     46279929     73.79%     73.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      6945490     11.07%     84.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      3654930      5.83%     90.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2050520      3.27%     93.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1130391      1.80%     95.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       454158      0.72%     96.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       393863      0.63%     97.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       373108      0.59%     97.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1436051      2.29%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     62718440                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            43662606                       # Number of instructions committed
system.cpu0.commit.committedOps              43662606                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11854981                       # Number of memory references committed
system.cpu0.commit.loads                      6964106                       # Number of loads committed
system.cpu0.commit.membars                     168172                       # Number of memory barriers committed
system.cpu0.commit.branches                   6551324                       # Number of branches committed
system.cpu0.commit.fp_insts                    210613                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 40489033                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              540020                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1436051                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   110111593                       # The number of ROB reads
system.cpu0.rob.rob_writes                   98948174                       # The number of ROB writes
system.cpu0.timesIdled                         879648                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26129913                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3707863967                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   41199881                       # Number of Instructions Simulated
system.cpu0.committedOps                     41199881                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             41199881                       # Number of Instructions Simulated
system.cpu0.cpi                              2.178491                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.178491                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.459033                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.459033                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                57370310                       # number of integer regfile reads
system.cpu0.int_regfile_writes               31317782                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   104569                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  105332                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1463769                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                718581                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                728874                       # number of replacements
system.cpu0.icache.tagsinuse               510.265304                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 5890439                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                729383                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.075920                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           20962478000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   510.265304                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996612                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996612                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      5890439                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        5890439                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      5890439                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         5890439                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      5890439                       # number of overall hits
system.cpu0.icache.overall_hits::total        5890439                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       766860                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       766860                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       766860                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        766860                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       766860                       # number of overall misses
system.cpu0.icache.overall_misses::total       766860                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10795349496                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10795349496                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10795349496                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10795349496                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10795349496                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10795349496                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      6657299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      6657299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      6657299                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      6657299                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      6657299                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      6657299                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.115191                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.115191                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.115191                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.115191                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.115191                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.115191                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14077.340709                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14077.340709                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2177                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          468                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              128                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.007812                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          468                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        37318                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        37318                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        37318                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        37318                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        37318                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        37318                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       729542                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       729542                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       729542                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       729542                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       729542                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       729542                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8901782997                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   8901782997                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8901782997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   8901782997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8901782997                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   8901782997                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.109585                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.109585                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.109585                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.109585                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.109585                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.109585                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1051655                       # number of replacements
system.cpu0.dcache.tagsinuse               479.291529                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 8945957                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1052167                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.502412                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              22123000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   479.291529                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.936116                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.936116                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5529733                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5529733                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3096724                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3096724                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       145068                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       145068                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       167974                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       167974                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8626457                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8626457                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8626457                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8626457                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1297164                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1297164                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1613226                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1613226                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        15668                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        15668                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          766                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          766                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2910390                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2910390                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2910390                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2910390                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  30009249500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  30009249500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  61556935480                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  61556935480                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    231982500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    231982500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      4680500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      4680500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  91566184980                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  91566184980                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  91566184980                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  91566184980                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6826897                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6826897                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4709950                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4709950                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       160736                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       160736                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       168740                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       168740                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11536847                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11536847                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11536847                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11536847                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.190008                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.190008                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.342514                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.342514                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.097477                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.097477                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004540                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004540                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.252269                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.252269                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.252269                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.252269                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6110.313316                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6110.313316                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      2024468                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets          671                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            45038                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    44.950220                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    95.857143                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       554167                       # number of writebacks
system.cpu0.dcache.writebacks::total           554167                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       497870                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       497870                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1365575                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1365575                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3772                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3772                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1863445                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1863445                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1863445                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1863445                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       799294                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       799294                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       247651                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       247651                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        11896                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11896                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          766                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          766                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1046945                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1046945                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1046945                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1046945                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  19199342000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  19199342000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8924614838                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8924614838                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    148344000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    148344000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3148500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3148500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  28123956838                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  28123956838                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  28123956838                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  28123956838                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    991461500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    991461500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1668991999                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1668991999                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2660453499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2660453499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.117080                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.117080                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.052580                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.052580                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.074010                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.074010                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004540                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004540                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.090748                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.090748                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.090748                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.090748                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4110.313316                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4110.313316                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                4327546                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          3555815                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           137782                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2736457                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1529937                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            55.909411                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 311519                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             14646                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     3068448                       # DTB read hits
system.cpu1.dtb.read_misses                     13337                       # DTB read misses
system.cpu1.dtb.read_acv                           21                       # DTB read access violations
system.cpu1.dtb.read_accesses                  325420                       # DTB read accesses
system.cpu1.dtb.write_hits                    1915630                       # DTB write hits
system.cpu1.dtb.write_misses                     2521                       # DTB write misses
system.cpu1.dtb.write_acv                          68                       # DTB write access violations
system.cpu1.dtb.write_accesses                 132592                       # DTB write accesses
system.cpu1.dtb.data_hits                     4984078                       # DTB hits
system.cpu1.dtb.data_misses                     15858                       # DTB misses
system.cpu1.dtb.data_acv                           89                       # DTB access violations
system.cpu1.dtb.data_accesses                  458012                       # DTB accesses
system.cpu1.itb.fetch_hits                     498592                       # ITB hits
system.cpu1.itb.fetch_misses                     6957                       # ITB misses
system.cpu1.itb.fetch_acv                         210                       # ITB acv
system.cpu1.itb.fetch_accesses                 505549                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        28341850                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           9666058                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      20746660                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    4327546                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1841456                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      3769607                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 667538                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles              11516910                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               24752                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        65971                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       157862                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          117                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  2430728                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                90320                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          25638274                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.809207                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.171586                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                21868667     85.30%     85.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  217825      0.85%     86.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  471767      1.84%     87.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  290566      1.13%     89.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  572691      2.23%     91.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  192619      0.75%     92.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  225020      0.88%     92.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  283328      1.11%     94.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1515791      5.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            25638274                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.152691                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.732015                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 9733408                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             11767392                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  3496252                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               218180                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                423041                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              197160                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                14107                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              20339380                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                42509                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                423041                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                10090973                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                3436285                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       7189136                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  3265501                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              1233336                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              19035683                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  265                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                302354                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               266371                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands           12573410                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             22727510                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        22552449                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           175061                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             10671795                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1901615                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            598380                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         62207                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  3655619                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             3246585                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            2021315                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           341799                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          191681                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  16730301                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             718132                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 16236732                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            38678                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        2401085                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      1178363                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        514161                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     25638274                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.633301                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.313801                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           18618463     72.62%     72.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            3106773     12.12%     84.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            1368758      5.34%     90.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             986929      3.85%     93.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             856057      3.34%     97.26% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             349630      1.36%     98.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             219211      0.86%     99.48% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             115612      0.45%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              16841      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       25638274                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  22162      7.89%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      7.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                144030     51.29%     59.18% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               114619     40.82%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3527      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             10692350     65.85%     65.87% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               24766      0.15%     66.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.03% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              11484      0.07%     66.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1763      0.01%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.11% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             3204356     19.74%     85.84% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1945149     11.98%     97.82% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            353337      2.18%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              16236732                       # Type of FU issued
system.cpu1.iq.rate                          0.572889                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     280811                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.017295                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          58178646                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         19730507                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     15830008                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             252581                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            122599                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       119620                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              16382145                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 131871                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          151965                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       456957                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          998                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         3692                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       187617                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads         5626                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        16438                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                423041                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                2638422                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               162147                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           18437863                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           211636                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              3246585                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             2021315                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            643129                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 60084                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 2152                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          3692                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         66784                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       149088                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              215872                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             16080551                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              3090638                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           156181                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       989430                       # number of nop insts executed
system.cpu1.iew.exec_refs                     5015230                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 2535241                       # Number of branches executed
system.cpu1.iew.exec_stores                   1924592                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.567378                       # Inst execution rate
system.cpu1.iew.wb_sent                      15988482                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     15949628                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  7724743                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 10881499                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.562759                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.709897                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        2575173                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         203971                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           201824                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     25215233                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.626683                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.561616                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     19361338     76.78%     76.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      2499341      9.91%     86.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1261575      5.00%     91.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       645749      2.56%     94.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       410067      1.63%     95.89% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       193046      0.77%     96.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       184525      0.73%     97.38% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       147171      0.58%     97.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       512421      2.03%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     25215233                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            15801951                       # Number of instructions committed
system.cpu1.commit.committedOps              15801951                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       4623326                       # Number of memory references committed
system.cpu1.commit.loads                      2789628                       # Number of loads committed
system.cpu1.commit.membars                      68640                       # Number of memory barriers committed
system.cpu1.commit.branches                   2366242                       # Number of branches committed
system.cpu1.commit.fp_insts                    118314                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 14589318                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              250839                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               512421                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    42991260                       # The number of ROB reads
system.cpu1.rob.rob_writes                   37176651                       # The number of ROB writes
system.cpu1.timesIdled                         292999                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2703576                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3768655732                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   14927555                       # Number of Instructions Simulated
system.cpu1.committedOps                     14927555                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             14927555                       # Number of Instructions Simulated
system.cpu1.cpi                              1.898626                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.898626                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.526697                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.526697                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                20802804                       # number of integer regfile reads
system.cpu1.int_regfile_writes               11409368                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    63889                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   64169                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 688257                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                294653                       # number of misc regfile writes
system.cpu1.icache.replacements                359909                       # number of replacements
system.cpu1.icache.tagsinuse               505.656535                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 2054105                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                360421                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  5.699182                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           43308699500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   505.656535                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.987610                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.987610                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      2054105                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        2054105                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      2054105                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         2054105                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      2054105                       # number of overall hits
system.cpu1.icache.overall_hits::total        2054105                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       376623                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       376623                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       376623                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        376623                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       376623                       # number of overall misses
system.cpu1.icache.overall_misses::total       376623                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5258660997                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5258660997                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5258660997                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5258660997                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5258660997                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5258660997                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      2430728                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      2430728                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      2430728                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      2430728                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      2430728                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      2430728                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.154942                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.154942                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.154942                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.154942                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.154942                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.154942                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13962.665575                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13962.665575                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         2479                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets         1476                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               54                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    45.907407                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets         1476                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        16134                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        16134                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        16134                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        16134                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        16134                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        16134                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       360489                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       360489                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       360489                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       360489                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       360489                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       360489                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4342433998                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4342433998                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4342433998                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4342433998                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4342433998                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4342433998                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.148305                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.148305                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.148305                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.148305                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.148305                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.148305                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12045.954240                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.954240                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12045.954240                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                377681                       # number of replacements
system.cpu1.dcache.tagsinuse               497.778191                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 3769592                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                378084                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                  9.970250                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           35370260000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   497.778191                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.972223                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.972223                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      2307913                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2307913                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1365825                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1365825                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        47088                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        47088                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50932                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        50932                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3673738                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3673738                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3673738                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3673738                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       542018                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       542018                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       408775                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       408775                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9102                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         9102                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          780                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          780                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       950793                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        950793                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       950793                       # number of overall misses
system.cpu1.dcache.overall_misses::total       950793                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8456828000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   8456828000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  13523509258                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  13523509258                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    132387000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    132387000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      5554000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      5554000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  21980337258                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  21980337258                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  21980337258                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  21980337258                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2849931                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2849931                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1774600                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1774600                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        56190                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        56190                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        51712                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        51712                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      4624531                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      4624531                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      4624531                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      4624531                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.190186                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.190186                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.230348                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.230348                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.161986                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.161986                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.015084                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.015084                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.205598                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.205598                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.205598                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.205598                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7120.512821                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7120.512821                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23117.899751                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23117.899751                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23117.899751                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23117.899751                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       393760                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             7994                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    49.256943                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       289966                       # number of writebacks
system.cpu1.dcache.writebacks::total           289966                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       235266                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       235266                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       338145                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       338145                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1764                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1764                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       573411                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       573411                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       573411                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       573411                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       306752                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       306752                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        70630                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        70630                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7338                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7338                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          780                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          780                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       377382                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       377382                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       377382                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       377382                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   4029157000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   4029157000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2036960738                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2036960738                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87414000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87414000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      3994000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      3994000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6066117738                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   6066117738                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6066117738                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   6066117738                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    491781000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    491781000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    942840000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    942840000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1434621000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1434621000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.107635                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.107635                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.039801                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.039801                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.130593                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.130593                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.015084                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.015084                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.081604                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.081604                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.081604                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.081604                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5120.512821                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5120.512821                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4837                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    159566                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   54412     39.60%     39.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.10%     39.69% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1925      1.40%     41.09% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                     16      0.01%     41.10% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  80931     58.90%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              137415                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    53531     49.06%     49.06% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.12%     49.18% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1925      1.76%     50.94% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                      16      0.01%     50.96% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   53515     49.04%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               109118                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1866933879000     98.32%     98.32% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               62852000      0.00%     98.32% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              558860500      0.03%     98.35% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                8730000      0.00%     98.35% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            31246000500      1.65%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1898810322000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.983809                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.661242                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.794076                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         7      3.47%      3.47% # number of syscalls executed
system.cpu0.kern.syscall::3                        16      7.92%     11.39% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.98%     13.37% # number of syscalls executed
system.cpu0.kern.syscall::6                        29     14.36%     27.72% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.50%     28.22% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.46%     32.67% # number of syscalls executed
system.cpu0.kern.syscall::19                        7      3.47%     36.14% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.98%     38.12% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.50%     38.61% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.49%     40.10% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.47%     43.56% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.99%     44.55% # number of syscalls executed
system.cpu0.kern.syscall::45                       34     16.83%     61.39% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.49%     62.87% # number of syscalls executed
system.cpu0.kern.syscall::48                        8      3.96%     66.83% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.46%     71.29% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.50%     71.78% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.48%     74.26% # number of syscalls executed
system.cpu0.kern.syscall::71                       25     12.38%     86.63% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.49%     88.12% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.97%     91.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.50%     91.58% # number of syscalls executed
system.cpu0.kern.syscall::90                        2      0.99%     92.57% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.47%     96.04% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.99%     97.03% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.99%     98.02% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.50%     98.51% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.50%     99.01% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.99%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   202                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  107      0.07%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.08% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.08% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.08% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 2838      1.96%      2.03% # number of callpals executed
system.cpu0.kern.callpal::tbi                      48      0.03%      2.07% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.07% # number of callpals executed
system.cpu0.kern.callpal::swpipl               131134     90.46%     92.54% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6127      4.23%     96.76% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.76% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.77% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     8      0.01%     96.77% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.77% # number of callpals executed
system.cpu0.kern.callpal::rti                    4208      2.90%     99.68% # number of callpals executed
system.cpu0.kern.callpal::callsys                 333      0.23%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     137      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                144957                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6180                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1258                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1257                      
system.cpu0.kern.mode_good::user                 1258                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.203398                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.338129                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1896878389500     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1931924500      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    2839                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    3835                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     77998                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   27220     39.42%     39.42% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1923      2.78%     42.20% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    107      0.15%     42.36% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  39804     57.64%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               69054                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    26724     48.26%     48.26% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1923      3.47%     51.74% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     107      0.19%     51.93% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   26617     48.07%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                55371                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1869610475000     98.48%     98.48% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              533425500      0.03%     98.51% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               50588500      0.00%     98.51% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            28306196500      1.49%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1898500685500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.981778                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.668702                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.801851                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         1      0.81%      0.81% # number of syscalls executed
system.cpu1.kern.syscall::3                        14     11.29%     12.10% # number of syscalls executed
system.cpu1.kern.syscall::6                        13     10.48%     22.58% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.81%     23.39% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      4.84%     28.23% # number of syscalls executed
system.cpu1.kern.syscall::19                        3      2.42%     30.65% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.61%     32.26% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.42%     34.68% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.42%     37.10% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.23%     40.32% # number of syscalls executed
system.cpu1.kern.syscall::45                       20     16.13%     56.45% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.42%     58.87% # number of syscalls executed
system.cpu1.kern.syscall::48                        2      1.61%     60.48% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.81%     61.29% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.61%     62.90% # number of syscalls executed
system.cpu1.kern.syscall::71                       29     23.39%     86.29% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      8.06%     94.35% # number of syscalls executed
system.cpu1.kern.syscall::90                        1      0.81%     95.16% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.61%     96.77% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.42%     99.19% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.81%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   124                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                   16      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1407      1.97%      2.00% # number of callpals executed
system.cpu1.kern.callpal::tbi                       6      0.01%      2.01% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.02% # number of callpals executed
system.cpu1.kern.callpal::swpipl                64017     89.75%     91.76% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2632      3.69%     95.45% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     95.45% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     95.46% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     1      0.00%     95.46% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     95.47% # number of callpals executed
system.cpu1.kern.callpal::rti                    3006      4.21%     99.68% # number of callpals executed
system.cpu1.kern.callpal::callsys                 184      0.26%     99.94% # number of callpals executed
system.cpu1.kern.callpal::imb                      43      0.06%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 71331                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1876                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                488                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2061                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                557                      
system.cpu1.kern.mode_good::user                  488                      
system.cpu1.kern.mode_good::idle                   69                      
system.cpu1.kern.mode_switch_good::kernel     0.296908                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.033479                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.251751                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       39690497500      2.09%      2.09% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           850597000      0.04%      2.14% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1857949530000     97.86%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1408                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------