stats.txt revision 9481
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39459Ssaidi@eecs.umich.edusim_seconds 1.901720 # Number of seconds simulated 49459Ssaidi@eecs.umich.edusim_ticks 1901719660500 # Number of ticks simulated 59459Ssaidi@eecs.umich.edufinal_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79481Snilay@cs.wisc.eduhost_inst_rate 97307 # Simulator instruction rate (inst/s) 89481Snilay@cs.wisc.eduhost_op_rate 97307 # Simulator op (including micro ops) rate (op/s) 99481Snilay@cs.wisc.eduhost_tick_rate 3261646555 # Simulator tick rate (ticks/s) 109481Snilay@cs.wisc.eduhost_mem_usage 383552 # Number of bytes of host memory used 119481Snilay@cs.wisc.eduhost_seconds 583.06 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 56735321 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 56735321 # Number of ops (including micro ops) simulated 149459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory 159459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.data 24596992 # Number of bytes read from this memory 169459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory 179459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.inst 118720 # Number of bytes read from this memory 189459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.data 533440 # Number of bytes read from this memory 199459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28758656 # Number of bytes read from this memory 209459Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory 219459Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu1.inst 118720 # Number of instructions bytes read from this memory 229459Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory 239459Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 7726912 # Number of bytes written to this memory 249459Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 7726912 # Number of bytes written to this memory 259459Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory 269459Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.data 384328 # Number of read requests responded to by this memory 279459Ssaidi@eecs.umich.edusystem.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory 289459Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.inst 1855 # Number of read requests responded to by this memory 299459Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.data 8335 # Number of read requests responded to by this memory 309459Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 449354 # Number of read requests responded to by this memory 319459Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 120733 # Number of write requests responded to by this memory 329459Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 120733 # Number of write requests responded to by this memory 339459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.inst 450960 # Total read bandwidth from this memory (bytes/s) 349459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.data 12934079 # Total read bandwidth from this memory (bytes/s) 359459Ssaidi@eecs.umich.edusystem.physmem.bw_read::tsunami.ide 1394477 # Total read bandwidth from this memory (bytes/s) 369459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.inst 62428 # Total read bandwidth from this memory (bytes/s) 379459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.data 280504 # Total read bandwidth from this memory (bytes/s) 389459Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 15122448 # Total read bandwidth from this memory (bytes/s) 399459Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu0.inst 450960 # Instruction read bandwidth from this memory (bytes/s) 409459Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu1.inst 62428 # Instruction read bandwidth from this memory (bytes/s) 419459Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 513388 # Instruction read bandwidth from this memory (bytes/s) 429459Ssaidi@eecs.umich.edusystem.physmem.bw_write::writebacks 4063118 # Write bandwidth from this memory (bytes/s) 439459Ssaidi@eecs.umich.edusystem.physmem.bw_write::total 4063118 # Write bandwidth from this memory (bytes/s) 449459Ssaidi@eecs.umich.edusystem.physmem.bw_total::writebacks 4063118 # Total bandwidth to/from this memory (bytes/s) 459459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.inst 450960 # Total bandwidth to/from this memory (bytes/s) 469459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.data 12934079 # Total bandwidth to/from this memory (bytes/s) 479459Ssaidi@eecs.umich.edusystem.physmem.bw_total::tsunami.ide 1394477 # Total bandwidth to/from this memory (bytes/s) 489459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.inst 62428 # Total bandwidth to/from this memory (bytes/s) 499459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.data 280504 # Total bandwidth to/from this memory (bytes/s) 509459Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 19185566 # Total bandwidth to/from this memory (bytes/s) 519459Ssaidi@eecs.umich.edusystem.physmem.readReqs 449354 # Total number of read requests seen 529459Ssaidi@eecs.umich.edusystem.physmem.writeReqs 120733 # Total number of write requests seen 539459Ssaidi@eecs.umich.edusystem.physmem.cpureqs 587676 # Reqs generatd by CPU via cache - shady 549459Ssaidi@eecs.umich.edusystem.physmem.bytesRead 28758656 # Total number of bytes read from memory 559459Ssaidi@eecs.umich.edusystem.physmem.bytesWritten 7726912 # Total number of bytes written to memory 569459Ssaidi@eecs.umich.edusystem.physmem.bytesConsumedRd 28758656 # bytesRead derated as per pkt->getSize() 579459Ssaidi@eecs.umich.edusystem.physmem.bytesConsumedWr 7726912 # bytesWritten derated as per pkt->getSize() 589459Ssaidi@eecs.umich.edusystem.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q 599459Ssaidi@eecs.umich.edusystem.physmem.neitherReadNorWrite 4987 # Reqs where no action is needed 609459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::0 28470 # Track reads on a per bank basis 619459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::1 27991 # Track reads on a per bank basis 629459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::2 28541 # Track reads on a per bank basis 639459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::3 28079 # Track reads on a per bank basis 649459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::4 28255 # Track reads on a per bank basis 659459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::5 28278 # Track reads on a per bank basis 669459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::6 27951 # Track reads on a per bank basis 679459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::7 27937 # Track reads on a per bank basis 689459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::8 28148 # Track reads on a per bank basis 699459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::9 28118 # Track reads on a per bank basis 709459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::10 28117 # Track reads on a per bank basis 719459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::11 28100 # Track reads on a per bank basis 729459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::12 27877 # Track reads on a per bank basis 739459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::13 27800 # Track reads on a per bank basis 749459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::14 27868 # Track reads on a per bank basis 759459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::15 27749 # Track reads on a per bank basis 769459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::0 7940 # Track writes on a per bank basis 779459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::1 7547 # Track writes on a per bank basis 789459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::2 7751 # Track writes on a per bank basis 799459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::3 7437 # Track writes on a per bank basis 809459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::4 7736 # Track writes on a per bank basis 819459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::5 7593 # Track writes on a per bank basis 829459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::6 7293 # Track writes on a per bank basis 839459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::7 7361 # Track writes on a per bank basis 849459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::8 7614 # Track writes on a per bank basis 859459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::9 7612 # Track writes on a per bank basis 869459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::10 7616 # Track writes on a per bank basis 879459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::11 7622 # Track writes on a per bank basis 889459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::12 7539 # Track writes on a per bank basis 899459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::13 7418 # Track writes on a per bank basis 909459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::14 7408 # Track writes on a per bank basis 919459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::15 7246 # Track writes on a per bank basis 929312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 939459Ssaidi@eecs.umich.edusystem.physmem.numWrRetry 393 # Number of times wr buffer was full causing retry 949459Ssaidi@eecs.umich.edusystem.physmem.totGap 1901668058000 # Total gap between requests 959312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 1019459Ssaidi@eecs.umich.edusystem.physmem.readPktSize::6 449354 # Categorize read packet sizes 1029312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 1039312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 1049312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 1059312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 1069312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 1079312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 1089312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 1099312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 1109459Ssaidi@eecs.umich.edusystem.physmem.writePktSize::6 121126 # categorize write packet sizes 1119312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 1129312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 1139312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 1149312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 1159312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 1169312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 1179312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 1189312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 1199459Ssaidi@eecs.umich.edusystem.physmem.neitherpktsize::6 4987 # categorize neither packet sizes 1209312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1219312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1229459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::0 322670 # What read queue length does an incoming req see 1239459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::1 66093 # What read queue length does an incoming req see 1249459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::2 30768 # What read queue length does an incoming req see 1259459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::3 6525 # What read queue length does an incoming req see 1269459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::4 2881 # What read queue length does an incoming req see 1279459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::5 2394 # What read queue length does an incoming req see 1289459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see 1299459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see 1309459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::8 1668 # What read queue length does an incoming req see 1319459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::9 1927 # What read queue length does an incoming req see 1329459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::10 1563 # What read queue length does an incoming req see 1339459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::11 1537 # What read queue length does an incoming req see 1349459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see 1359459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::13 1779 # What read queue length does an incoming req see 1369459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::14 1228 # What read queue length does an incoming req see 1379459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::15 1454 # What read queue length does an incoming req see 1389459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::16 894 # What read queue length does an incoming req see 1399459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see 1409459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see 1419459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see 1429459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 1439459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see 1449459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see 1459459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1559459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::0 4050 # What write queue length does an incoming req see 1569459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::1 4973 # What write queue length does an incoming req see 1579459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::2 5082 # What write queue length does an incoming req see 1589459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::3 5135 # What write queue length does an incoming req see 1599459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::4 5198 # What write queue length does an incoming req see 1609459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::5 5217 # What write queue length does an incoming req see 1619459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::6 5244 # What write queue length does an incoming req see 1629459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::7 5244 # What write queue length does an incoming req see 1639459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::8 5245 # What write queue length does an incoming req see 1649459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::9 5249 # What write queue length does an incoming req see 1659459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::10 5249 # What write queue length does an incoming req see 1669459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::11 5249 # What write queue length does an incoming req see 1679459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::12 5249 # What write queue length does an incoming req see 1689459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::13 5249 # What write queue length does an incoming req see 1699459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::14 5249 # What write queue length does an incoming req see 1709459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::15 5249 # What write queue length does an incoming req see 1719459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::16 5249 # What write queue length does an incoming req see 1729459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::17 5249 # What write queue length does an incoming req see 1739459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::18 5249 # What write queue length does an incoming req see 1749459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::19 5249 # What write queue length does an incoming req see 1759459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::20 5249 # What write queue length does an incoming req see 1769459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::21 5249 # What write queue length does an incoming req see 1779459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::22 5249 # What write queue length does an incoming req see 1789459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see 1799459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::24 277 # What write queue length does an incoming req see 1809459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see 1819459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::26 115 # What write queue length does an incoming req see 1829459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see 1839459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see 1849459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see 1859459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see 1869459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see 1879312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1889459Ssaidi@eecs.umich.edusystem.physmem.totQLat 6361514382 # Total cycles spent in queuing delays 1899459Ssaidi@eecs.umich.edusystem.physmem.totMemAccLat 13649024382 # Sum of mem lat for all requests 1909459Ssaidi@eecs.umich.edusystem.physmem.totBusLat 1797116000 # Total cycles spent in databus access 1919459Ssaidi@eecs.umich.edusystem.physmem.totBankLat 5490394000 # Total cycles spent in bank access 1929459Ssaidi@eecs.umich.edusystem.physmem.avgQLat 14159.39 # Average queueing delay per request 1939459Ssaidi@eecs.umich.edusystem.physmem.avgBankLat 12220.46 # Average bank access latency per request 1949312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1959459Ssaidi@eecs.umich.edusystem.physmem.avgMemAccLat 30379.84 # Average memory access latency 1969459Ssaidi@eecs.umich.edusystem.physmem.avgRdBW 15.12 # Average achieved read bandwidth in MB/s 1979459Ssaidi@eecs.umich.edusystem.physmem.avgWrBW 4.06 # Average achieved write bandwidth in MB/s 1989459Ssaidi@eecs.umich.edusystem.physmem.avgConsumedRdBW 15.12 # Average consumed read bandwidth in MB/s 1999459Ssaidi@eecs.umich.edusystem.physmem.avgConsumedWrBW 4.06 # Average consumed write bandwidth in MB/s 2009312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 2019312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.12 # Data bus utilization in percentage 2029312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.01 # Average read queue length over time 2039459Ssaidi@eecs.umich.edusystem.physmem.avgWrQLen 13.85 # Average write queue length over time 2049459Ssaidi@eecs.umich.edusystem.physmem.readRowHits 429052 # Number of row buffer hits during reads 2059459Ssaidi@eecs.umich.edusystem.physmem.writeRowHits 77896 # Number of row buffer hits during writes 2069459Ssaidi@eecs.umich.edusystem.physmem.readRowHitRate 95.50 # Row buffer hit rate for reads 2079459Ssaidi@eecs.umich.edusystem.physmem.writeRowHitRate 64.52 # Row buffer hit rate for writes 2089459Ssaidi@eecs.umich.edusystem.physmem.avgGap 3335750.61 # Average gap between requests 2099459Ssaidi@eecs.umich.edusystem.l2c.replacements 342488 # number of replacements 2109459Ssaidi@eecs.umich.edusystem.l2c.tagsinuse 65273.985795 # Cycle average of tags in use 2119459Ssaidi@eecs.umich.edusystem.l2c.total_refs 2579319 # Total number of references to valid blocks. 2129459Ssaidi@eecs.umich.edusystem.l2c.sampled_refs 407454 # Sample count of references to valid blocks. 2139459Ssaidi@eecs.umich.edusystem.l2c.avg_refs 6.330332 # Average number of references to valid blocks. 2149312Sandreas.hansson@arm.comsystem.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. 2159459Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::writebacks 53688.105683 # Average occupied blocks per requestor 2169459Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu0.inst 5378.814643 # Average occupied blocks per requestor 2179459Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu0.data 5989.071273 # Average occupied blocks per requestor 2189459Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.inst 150.579784 # Average occupied blocks per requestor 2199459Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.data 67.414412 # Average occupied blocks per requestor 2209459Ssaidi@eecs.umich.edusystem.l2c.occ_percent::writebacks 0.819215 # Average percentage of cache occupancy 2219459Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu0.inst 0.082074 # Average percentage of cache occupancy 2229459Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu0.data 0.091386 # Average percentage of cache occupancy 2239459Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu1.inst 0.002298 # Average percentage of cache occupancy 2249459Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy 2259459Ssaidi@eecs.umich.edusystem.l2c.occ_percent::total 0.996002 # Average percentage of cache occupancy 2269459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.inst 855139 # number of ReadReq hits 2279459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.data 732341 # number of ReadReq hits 2289459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.inst 222061 # number of ReadReq hits 2299459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.data 70684 # number of ReadReq hits 2309459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::total 1880225 # number of ReadReq hits 2319459Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::writebacks 820780 # number of Writeback hits 2329459Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::total 820780 # number of Writeback hits 2339459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits 2349459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits 2359459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::total 437 # number of UpgradeReq hits 2369459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits 2379459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits 2389459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits 2399459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::cpu0.data 155166 # number of ReadExReq hits 2409459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::cpu1.data 26038 # number of ReadExReq hits 2419459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::total 181204 # number of ReadExReq hits 2429459Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.inst 855139 # number of demand (read+write) hits 2439459Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.data 887507 # number of demand (read+write) hits 2449459Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.inst 222061 # number of demand (read+write) hits 2459459Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.data 96722 # number of demand (read+write) hits 2469459Ssaidi@eecs.umich.edusystem.l2c.demand_hits::total 2061429 # number of demand (read+write) hits 2479459Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.inst 855139 # number of overall hits 2489459Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.data 887507 # number of overall hits 2499459Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.inst 222061 # number of overall hits 2509459Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.data 96722 # number of overall hits 2519459Ssaidi@eecs.umich.edusystem.l2c.overall_hits::total 2061429 # number of overall hits 2529459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.inst 13402 # number of ReadReq misses 2539459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.data 273000 # number of ReadReq misses 2549459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.inst 1871 # number of ReadReq misses 2559459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.data 879 # number of ReadReq misses 2569459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::total 289152 # number of ReadReq misses 2579459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu0.data 2698 # number of UpgradeReq misses 2589459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu1.data 1127 # number of UpgradeReq misses 2599459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::total 3825 # number of UpgradeReq misses 2609459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu0.data 423 # number of SCUpgradeReq misses 2619459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu1.data 448 # number of SCUpgradeReq misses 2629459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::total 871 # number of SCUpgradeReq misses 2639459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::cpu0.data 111862 # number of ReadExReq misses 2649459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::cpu1.data 7571 # number of ReadExReq misses 2659459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::total 119433 # number of ReadExReq misses 2669459Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.inst 13402 # number of demand (read+write) misses 2679459Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.data 384862 # number of demand (read+write) misses 2689459Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.inst 1871 # number of demand (read+write) misses 2699459Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.data 8450 # number of demand (read+write) misses 2709459Ssaidi@eecs.umich.edusystem.l2c.demand_misses::total 408585 # number of demand (read+write) misses 2719459Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.inst 13402 # number of overall misses 2729459Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.data 384862 # number of overall misses 2739459Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.inst 1871 # number of overall misses 2749459Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.data 8450 # number of overall misses 2759459Ssaidi@eecs.umich.edusystem.l2c.overall_misses::total 408585 # number of overall misses 2769459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_latency::cpu0.inst 813261500 # number of ReadReq miss cycles 2779459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_latency::cpu0.data 11720735498 # number of ReadReq miss cycles 2789459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_latency::cpu1.inst 126107500 # number of ReadReq miss cycles 2799459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_latency::cpu1.data 66824498 # number of ReadReq miss cycles 2809459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_latency::total 12726928996 # number of ReadReq miss cycles 2819459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_latency::cpu0.data 1011000 # number of UpgradeReq miss cycles 2829459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_latency::cpu1.data 4739996 # number of UpgradeReq miss cycles 2839459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_latency::total 5750996 # number of UpgradeReq miss cycles 2849459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 1139500 # number of SCUpgradeReq miss cycles 2859459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 114000 # number of SCUpgradeReq miss cycles 2869459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_latency::total 1253500 # number of SCUpgradeReq miss cycles 2879459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_latency::cpu0.data 7926259499 # number of ReadExReq miss cycles 2889459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_latency::cpu1.data 948720500 # number of ReadExReq miss cycles 2899459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_latency::total 8874979999 # number of ReadExReq miss cycles 2909459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_latency::cpu0.inst 813261500 # number of demand (read+write) miss cycles 2919459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_latency::cpu0.data 19646994997 # number of demand (read+write) miss cycles 2929459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_latency::cpu1.inst 126107500 # number of demand (read+write) miss cycles 2939459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_latency::cpu1.data 1015544998 # number of demand (read+write) miss cycles 2949459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_latency::total 21601908995 # number of demand (read+write) miss cycles 2959459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_latency::cpu0.inst 813261500 # number of overall miss cycles 2969459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_latency::cpu0.data 19646994997 # number of overall miss cycles 2979459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_latency::cpu1.inst 126107500 # number of overall miss cycles 2989459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_latency::cpu1.data 1015544998 # number of overall miss cycles 2999459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_latency::total 21601908995 # number of overall miss cycles 3009459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.inst 868541 # number of ReadReq accesses(hits+misses) 3019459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.data 1005341 # number of ReadReq accesses(hits+misses) 3029459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.inst 223932 # number of ReadReq accesses(hits+misses) 3039459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.data 71563 # number of ReadReq accesses(hits+misses) 3049459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::total 2169377 # number of ReadReq accesses(hits+misses) 3059459Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::writebacks 820780 # number of Writeback accesses(hits+misses) 3069459Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::total 820780 # number of Writeback accesses(hits+misses) 3079459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu0.data 2861 # number of UpgradeReq accesses(hits+misses) 3089459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu1.data 1401 # number of UpgradeReq accesses(hits+misses) 3099459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::total 4262 # number of UpgradeReq accesses(hits+misses) 3109459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu0.data 471 # number of SCUpgradeReq accesses(hits+misses) 3119459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) 3129459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::total 945 # number of SCUpgradeReq accesses(hits+misses) 3139459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu0.data 267028 # number of ReadExReq accesses(hits+misses) 3149459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu1.data 33609 # number of ReadExReq accesses(hits+misses) 3159459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::total 300637 # number of ReadExReq accesses(hits+misses) 3169459Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.inst 868541 # number of demand (read+write) accesses 3179459Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.data 1272369 # number of demand (read+write) accesses 3189459Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.inst 223932 # number of demand (read+write) accesses 3199459Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.data 105172 # number of demand (read+write) accesses 3209459Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::total 2470014 # number of demand (read+write) accesses 3219459Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.inst 868541 # number of overall (read+write) accesses 3229459Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.data 1272369 # number of overall (read+write) accesses 3239459Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.inst 223932 # number of overall (read+write) accesses 3249459Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.data 105172 # number of overall (read+write) accesses 3259459Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::total 2470014 # number of overall (read+write) accesses 3269459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.inst 0.015430 # miss rate for ReadReq accesses 3279459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.data 0.271550 # miss rate for ReadReq accesses 3289459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.inst 0.008355 # miss rate for ReadReq accesses 3299459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.data 0.012283 # miss rate for ReadReq accesses 3309459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::total 0.133288 # miss rate for ReadReq accesses 3319459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.943027 # miss rate for UpgradeReq accesses 3329459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.804425 # miss rate for UpgradeReq accesses 3339459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::total 0.897466 # miss rate for UpgradeReq accesses 3349459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.898089 # miss rate for SCUpgradeReq accesses 3359459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945148 # miss rate for SCUpgradeReq accesses 3369459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::total 0.921693 # miss rate for SCUpgradeReq accesses 3379459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::cpu0.data 0.418915 # miss rate for ReadExReq accesses 3389459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::cpu1.data 0.225267 # miss rate for ReadExReq accesses 3399459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::total 0.397266 # miss rate for ReadExReq accesses 3409459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.inst 0.015430 # miss rate for demand accesses 3419459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.data 0.302477 # miss rate for demand accesses 3429459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.inst 0.008355 # miss rate for demand accesses 3439459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.data 0.080345 # miss rate for demand accesses 3449459Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::total 0.165418 # miss rate for demand accesses 3459459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.inst 0.015430 # miss rate for overall accesses 3469459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.data 0.302477 # miss rate for overall accesses 3479459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.inst 0.008355 # miss rate for overall accesses 3489459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.data 0.080345 # miss rate for overall accesses 3499459Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::total 0.165418 # miss rate for overall accesses 3509459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 60682.099687 # average ReadReq miss latency 3519459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_miss_latency::cpu0.data 42933.097062 # average ReadReq miss latency 3529459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 67401.122394 # average ReadReq miss latency 3539459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_miss_latency::cpu1.data 76023.319681 # average ReadReq miss latency 3549459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_miss_latency::total 44014.667013 # average ReadReq miss latency 3559459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 374.722016 # average UpgradeReq miss latency 3569459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4205.852706 # average UpgradeReq miss latency 3579459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_avg_miss_latency::total 1503.528366 # average UpgradeReq miss latency 3589459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2693.853428 # average SCUpgradeReq miss latency 3599459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 254.464286 # average SCUpgradeReq miss latency 3609459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_avg_miss_latency::total 1439.150402 # average SCUpgradeReq miss latency 3619459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 70857.480637 # average ReadExReq miss latency 3629459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 125309.800555 # average ReadExReq miss latency 3639459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_avg_miss_latency::total 74309.277997 # average ReadExReq miss latency 3649459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_miss_latency::cpu0.inst 60682.099687 # average overall miss latency 3659459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_miss_latency::cpu0.data 51049.454082 # average overall miss latency 3669459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_miss_latency::cpu1.inst 67401.122394 # average overall miss latency 3679459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_miss_latency::cpu1.data 120182.840000 # average overall miss latency 3689459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_miss_latency::total 52870.049060 # average overall miss latency 3699459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_miss_latency::cpu0.inst 60682.099687 # average overall miss latency 3709459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_miss_latency::cpu0.data 51049.454082 # average overall miss latency 3719459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_miss_latency::cpu1.inst 67401.122394 # average overall miss latency 3729459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_miss_latency::cpu1.data 120182.840000 # average overall miss latency 3739459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_miss_latency::total 52870.049060 # average overall miss latency 3748464SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3758464SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3768464SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3778464SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 3788983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3798983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3808464SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 3818464SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 3829459Ssaidi@eecs.umich.edusystem.l2c.writebacks::writebacks 79213 # number of writebacks 3839459Ssaidi@eecs.umich.edusystem.l2c.writebacks::total 79213 # number of writebacks 3848844SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 3859348SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 3869348SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 3878835SAli.Saidi@ARM.comsystem.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 3888844SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 3899348SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 3909348SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 3918835SAli.Saidi@ARM.comsystem.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 3928844SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 3939348SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 3949348SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 3958835SAli.Saidi@ARM.comsystem.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 3969459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_misses::cpu0.inst 13401 # number of ReadReq MSHR misses 3979459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_misses::cpu0.data 273000 # number of ReadReq MSHR misses 3989459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_misses::cpu1.inst 1855 # number of ReadReq MSHR misses 3999459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_misses::cpu1.data 878 # number of ReadReq MSHR misses 4009459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses 4019459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_misses::cpu0.data 2698 # number of UpgradeReq MSHR misses 4029459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_misses::cpu1.data 1127 # number of UpgradeReq MSHR misses 4039459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_misses::total 3825 # number of UpgradeReq MSHR misses 4049459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 423 # number of SCUpgradeReq MSHR misses 4059459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 448 # number of SCUpgradeReq MSHR misses 4069459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_misses::total 871 # number of SCUpgradeReq MSHR misses 4079459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_misses::cpu0.data 111862 # number of ReadExReq MSHR misses 4089459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_misses::cpu1.data 7571 # number of ReadExReq MSHR misses 4099459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_misses::total 119433 # number of ReadExReq MSHR misses 4109459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_misses::cpu0.inst 13401 # number of demand (read+write) MSHR misses 4119459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_misses::cpu0.data 384862 # number of demand (read+write) MSHR misses 4129459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_misses::cpu1.inst 1855 # number of demand (read+write) MSHR misses 4139459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_misses::cpu1.data 8449 # number of demand (read+write) MSHR misses 4149459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_misses::total 408567 # number of demand (read+write) MSHR misses 4159459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_misses::cpu0.inst 13401 # number of overall MSHR misses 4169459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_misses::cpu0.data 384862 # number of overall MSHR misses 4179459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_misses::cpu1.inst 1855 # number of overall MSHR misses 4189459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_misses::cpu1.data 8449 # number of overall MSHR misses 4199459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_misses::total 408567 # number of overall MSHR misses 4209459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 644081442 # number of ReadReq MSHR miss cycles 4219459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_latency::cpu0.data 8187744767 # number of ReadReq MSHR miss cycles 4229459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_latency::cpu1.inst 101989522 # number of ReadReq MSHR miss cycles 4239459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_latency::cpu1.data 55676772 # number of ReadReq MSHR miss cycles 4249459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_latency::total 8989492503 # number of ReadReq MSHR miss cycles 4259459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27208158 # number of UpgradeReq MSHR miss cycles 4269459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11300121 # number of UpgradeReq MSHR miss cycles 4279459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_miss_latency::total 38508279 # number of UpgradeReq MSHR miss cycles 4289459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4442418 # number of SCUpgradeReq MSHR miss cycles 4299459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4488947 # number of SCUpgradeReq MSHR miss cycles 4309459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_miss_latency::total 8931365 # number of SCUpgradeReq MSHR miss cycles 4319459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6555553694 # number of ReadExReq MSHR miss cycles 4329459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 854426889 # number of ReadExReq MSHR miss cycles 4339459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_miss_latency::total 7409980583 # number of ReadExReq MSHR miss cycles 4349459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_latency::cpu0.inst 644081442 # number of demand (read+write) MSHR miss cycles 4359459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_latency::cpu0.data 14743298461 # number of demand (read+write) MSHR miss cycles 4369459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_latency::cpu1.inst 101989522 # number of demand (read+write) MSHR miss cycles 4379459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_latency::cpu1.data 910103661 # number of demand (read+write) MSHR miss cycles 4389459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_latency::total 16399473086 # number of demand (read+write) MSHR miss cycles 4399459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_latency::cpu0.inst 644081442 # number of overall MSHR miss cycles 4409459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_latency::cpu0.data 14743298461 # number of overall MSHR miss cycles 4419459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_latency::cpu1.inst 101989522 # number of overall MSHR miss cycles 4429459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_latency::cpu1.data 910103661 # number of overall MSHR miss cycles 4439459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_latency::total 16399473086 # number of overall MSHR miss cycles 4449459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363910000 # number of ReadReq MSHR uncacheable cycles 4459459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28770000 # number of ReadReq MSHR uncacheable cycles 4469459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_uncacheable_latency::total 1392680000 # number of ReadReq MSHR uncacheable cycles 4479459Ssaidi@eecs.umich.edusystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2007132500 # number of WriteReq MSHR uncacheable cycles 4489459Ssaidi@eecs.umich.edusystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 609318500 # number of WriteReq MSHR uncacheable cycles 4499459Ssaidi@eecs.umich.edusystem.l2c.WriteReq_mshr_uncacheable_latency::total 2616451000 # number of WriteReq MSHR uncacheable cycles 4509459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 3371042500 # number of overall MSHR uncacheable cycles 4519459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 638088500 # number of overall MSHR uncacheable cycles 4529459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_uncacheable_latency::total 4009131000 # number of overall MSHR uncacheable cycles 4539459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for ReadReq accesses 4549459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271550 # mshr miss rate for ReadReq accesses 4559459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for ReadReq accesses 4569459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012269 # mshr miss rate for ReadReq accesses 4579459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_mshr_miss_rate::total 0.133280 # mshr miss rate for ReadReq accesses 4589459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943027 # mshr miss rate for UpgradeReq accesses 4599459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.804425 # mshr miss rate for UpgradeReq accesses 4609459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_mshr_miss_rate::total 0.897466 # mshr miss rate for UpgradeReq accesses 4619459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.898089 # mshr miss rate for SCUpgradeReq accesses 4629459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945148 # mshr miss rate for SCUpgradeReq accesses 4639459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.921693 # mshr miss rate for SCUpgradeReq accesses 4649459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.418915 # mshr miss rate for ReadExReq accesses 4659459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.225267 # mshr miss rate for ReadExReq accesses 4669459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_mshr_miss_rate::total 0.397266 # mshr miss rate for ReadExReq accesses 4679459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for demand accesses 4689459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::cpu0.data 0.302477 # mshr miss rate for demand accesses 4699459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for demand accesses 4709459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::cpu1.data 0.080335 # mshr miss rate for demand accesses 4719459Ssaidi@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::total 0.165411 # mshr miss rate for demand accesses 4729459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for overall accesses 4739459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::cpu0.data 0.302477 # mshr miss rate for overall accesses 4749459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for overall accesses 4759459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::cpu1.data 0.080335 # mshr miss rate for overall accesses 4769459Ssaidi@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::total 0.165411 # mshr miss rate for overall accesses 4779459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average ReadReq mshr miss latency 4789459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29991.739073 # average ReadReq mshr miss latency 4799459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average ReadReq mshr miss latency 4809459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63413.179954 # average ReadReq mshr miss latency 4819459Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_miss_latency::total 31091.094451 # average ReadReq mshr miss latency 4829459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10084.565604 # average UpgradeReq mshr miss latency 4839459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10026.726708 # average UpgradeReq mshr miss latency 4849459Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.523922 # average UpgradeReq mshr miss latency 4859459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10502.170213 # average SCUpgradeReq mshr miss latency 4869459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.970982 # average SCUpgradeReq mshr miss latency 4879459Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10254.150402 # average SCUpgradeReq mshr miss latency 4889459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58603.937834 # average ReadExReq mshr miss latency 4899459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 112855.222428 # average ReadExReq mshr miss latency 4909459Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_avg_mshr_miss_latency::total 62042.991326 # average ReadExReq mshr miss latency 4919459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average overall mshr miss latency 4929459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 38308.012901 # average overall mshr miss latency 4939459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average overall mshr miss latency 4949459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 107717.322878 # average overall mshr miss latency 4959459Ssaidi@eecs.umich.edusystem.l2c.demand_avg_mshr_miss_latency::total 40139.005563 # average overall mshr miss latency 4969459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average overall mshr miss latency 4979459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 38308.012901 # average overall mshr miss latency 4989459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average overall mshr miss latency 4999459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 107717.322878 # average overall mshr miss latency 5009459Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_miss_latency::total 40139.005563 # average overall mshr miss latency 5018835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 5028835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 5039055Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 5048835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 5058835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 5069055Ssaidi@eecs.umich.edusystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 5078835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 5088835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 5099055Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 5108464SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 5119459Ssaidi@eecs.umich.edusystem.iocache.replacements 41699 # number of replacements 5129459Ssaidi@eecs.umich.edusystem.iocache.tagsinuse 0.510808 # Cycle average of tags in use 5138464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 5149459Ssaidi@eecs.umich.edusystem.iocache.sampled_refs 41715 # Sample count of references to valid blocks. 5158464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 5169459Ssaidi@eecs.umich.edusystem.iocache.warmup_cycle 1705448726000 # Cycle when the warmup percentage was hit. 5179459Ssaidi@eecs.umich.edusystem.iocache.occ_blocks::tsunami.ide 0.510808 # Average occupied blocks per requestor 5189459Ssaidi@eecs.umich.edusystem.iocache.occ_percent::tsunami.ide 0.031925 # Average percentage of cache occupancy 5199459Ssaidi@eecs.umich.edusystem.iocache.occ_percent::total 0.031925 # Average percentage of cache occupancy 5209459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 5219459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 5228835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 5238464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 5249459Ssaidi@eecs.umich.edusystem.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 5259459Ssaidi@eecs.umich.edusystem.iocache.demand_misses::total 41731 # number of demand (read+write) misses 5269459Ssaidi@eecs.umich.edusystem.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 5279459Ssaidi@eecs.umich.edusystem.iocache.overall_misses::total 41731 # number of overall misses 5289459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_latency::tsunami.ide 21606998 # number of ReadReq miss cycles 5299459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_latency::total 21606998 # number of ReadReq miss cycles 5309459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_latency::tsunami.ide 9515470806 # number of WriteReq miss cycles 5319459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_latency::total 9515470806 # number of WriteReq miss cycles 5329459Ssaidi@eecs.umich.edusystem.iocache.demand_miss_latency::tsunami.ide 9537077804 # number of demand (read+write) miss cycles 5339459Ssaidi@eecs.umich.edusystem.iocache.demand_miss_latency::total 9537077804 # number of demand (read+write) miss cycles 5349459Ssaidi@eecs.umich.edusystem.iocache.overall_miss_latency::tsunami.ide 9537077804 # number of overall miss cycles 5359459Ssaidi@eecs.umich.edusystem.iocache.overall_miss_latency::total 9537077804 # number of overall miss cycles 5369459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 5379459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 5388835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 5398464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 5409459Ssaidi@eecs.umich.edusystem.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 5419459Ssaidi@eecs.umich.edusystem.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 5429459Ssaidi@eecs.umich.edusystem.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 5439459Ssaidi@eecs.umich.edusystem.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 5448835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 5459055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 5468835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 5479055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 5488835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 5499055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 5508835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 5519055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 5529459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 120709.486034 # average ReadReq miss latency 5539459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_avg_miss_latency::total 120709.486034 # average ReadReq miss latency 5549459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 229001.511504 # average WriteReq miss latency 5559459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_avg_miss_latency::total 229001.511504 # average WriteReq miss latency 5569459Ssaidi@eecs.umich.edusystem.iocache.demand_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency 5579459Ssaidi@eecs.umich.edusystem.iocache.demand_avg_miss_latency::total 228537.006158 # average overall miss latency 5589459Ssaidi@eecs.umich.edusystem.iocache.overall_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency 5599459Ssaidi@eecs.umich.edusystem.iocache.overall_avg_miss_latency::total 228537.006158 # average overall miss latency 5609459Ssaidi@eecs.umich.edusystem.iocache.blocked_cycles::no_mshrs 190616 # number of cycles access was blocked 5618464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5629459Ssaidi@eecs.umich.edusystem.iocache.blocked::no_mshrs 22877 # number of cycles access was blocked 5638464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 5649459Ssaidi@eecs.umich.edusystem.iocache.avg_blocked_cycles::no_mshrs 8.332211 # average number of cycles each access was blocked 5658983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5668464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 5678464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 5689459Ssaidi@eecs.umich.edusystem.iocache.writebacks::writebacks 41520 # number of writebacks 5699459Ssaidi@eecs.umich.edusystem.iocache.writebacks::total 41520 # number of writebacks 5709459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 5719459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 5728835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 5738835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 5749459Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 5759459Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 5769459Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 5779459Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses 5789459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12298000 # number of ReadReq MSHR miss cycles 5799459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_latency::total 12298000 # number of ReadReq MSHR miss cycles 5809459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7352694535 # number of WriteReq MSHR miss cycles 5819459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_latency::total 7352694535 # number of WriteReq MSHR miss cycles 5829459Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_latency::tsunami.ide 7364992535 # number of demand (read+write) MSHR miss cycles 5839459Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_latency::total 7364992535 # number of demand (read+write) MSHR miss cycles 5849459Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_latency::tsunami.ide 7364992535 # number of overall MSHR miss cycles 5859459Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_latency::total 7364992535 # number of overall MSHR miss cycles 5868835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 5879055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 5888835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 5899055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 5908835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 5919055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 5928835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 5939055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 5949459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68703.910615 # average ReadReq mshr miss latency 5959459Ssaidi@eecs.umich.edusystem.iocache.ReadReq_avg_mshr_miss_latency::total 68703.910615 # average ReadReq mshr miss latency 5969459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176951.639753 # average WriteReq mshr miss latency 5979459Ssaidi@eecs.umich.edusystem.iocache.WriteReq_avg_mshr_miss_latency::total 176951.639753 # average WriteReq mshr miss latency 5989459Ssaidi@eecs.umich.edusystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency 5999459Ssaidi@eecs.umich.edusystem.iocache.demand_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency 6009459Ssaidi@eecs.umich.edusystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency 6019459Ssaidi@eecs.umich.edusystem.iocache.overall_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency 6028464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 6038464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 6048464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 6058464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 6068464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 6078464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 6088464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 6098464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 6108464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 6118464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 6128464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 6138464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 6148464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 6159481Snilay@cs.wisc.edusystem.cpu0.branchPred.lookups 12372868 # Number of BP lookups 6169481Snilay@cs.wisc.edusystem.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted 6179481Snilay@cs.wisc.edusystem.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect 6189481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups 6199481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits 6209481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 6219481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage 6229481Snilay@cs.wisc.edusystem.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target. 6239481Snilay@cs.wisc.edusystem.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions. 6248464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 6258464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 6268464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 6278464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 6289459Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_hits 8796431 # DTB read hits 6299459Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_misses 31428 # DTB read misses 6309459Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_acv 541 # DTB read access violations 6319459Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_accesses 625134 # DTB read accesses 6329459Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_hits 5759616 # DTB write hits 6339459Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_misses 8293 # DTB write misses 6349459Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_acv 340 # DTB write access violations 6359459Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_accesses 208056 # DTB write accesses 6369459Ssaidi@eecs.umich.edusystem.cpu0.dtb.data_hits 14556047 # DTB hits 6379459Ssaidi@eecs.umich.edusystem.cpu0.dtb.data_misses 39721 # DTB misses 6389459Ssaidi@eecs.umich.edusystem.cpu0.dtb.data_acv 881 # DTB access violations 6399459Ssaidi@eecs.umich.edusystem.cpu0.dtb.data_accesses 833190 # DTB accesses 6409459Ssaidi@eecs.umich.edusystem.cpu0.itb.fetch_hits 984271 # ITB hits 6419459Ssaidi@eecs.umich.edusystem.cpu0.itb.fetch_misses 30098 # ITB misses 6429459Ssaidi@eecs.umich.edusystem.cpu0.itb.fetch_acv 957 # ITB acv 6439459Ssaidi@eecs.umich.edusystem.cpu0.itb.fetch_accesses 1014369 # ITB accesses 6448464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 6458464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 6468464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 6478464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 6488464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 6498464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 6508464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 6518464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 6528464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 6538464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 6548464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 6558464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 6569459Ssaidi@eecs.umich.edusystem.cpu0.numCycles 101814962 # number of cpu cycles simulated 6578464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 6588464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 6599459Ssaidi@eecs.umich.edusystem.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss 6609459Ssaidi@eecs.umich.edusystem.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed 6619459Ssaidi@eecs.umich.edusystem.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered 6629459Ssaidi@eecs.umich.edusystem.cpu0.fetch.predictedBranches 6062114 # Number of branches that fetch has predicted taken 6639459Ssaidi@eecs.umich.edusystem.cpu0.fetch.Cycles 11958171 # Number of cycles fetch has run and was not squashing or blocked 6649459Ssaidi@eecs.umich.edusystem.cpu0.fetch.SquashCycles 1721751 # Number of cycles fetch has spent squashing 6659459Ssaidi@eecs.umich.edusystem.cpu0.fetch.BlockedCycles 36639586 # Number of cycles fetch has spent blocked 6669459Ssaidi@eecs.umich.edusystem.cpu0.fetch.MiscStallCycles 31996 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 6679459Ssaidi@eecs.umich.edusystem.cpu0.fetch.PendingTrapStallCycles 197160 # Number of stall cycles due to pending traps 6689459Ssaidi@eecs.umich.edusystem.cpu0.fetch.PendingQuiesceStallCycles 291451 # Number of stall cycles due to pending quiesce instructions 6699459Ssaidi@eecs.umich.edusystem.cpu0.fetch.IcacheWaitRetryStallCycles 250 # Number of stall cycles due to full MSHR 6709459Ssaidi@eecs.umich.edusystem.cpu0.fetch.CacheLines 7650026 # Number of cache lines fetched 6719459Ssaidi@eecs.umich.edusystem.cpu0.fetch.IcacheSquashes 223701 # Number of outstanding Icache misses that were squashed 6729459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::samples 75155119 # Number of instructions fetched each cycle (Total) 6739459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::mean 0.846620 # Number of instructions fetched each cycle (Total) 6749459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::stdev 2.185016 # Number of instructions fetched each cycle (Total) 6758464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 6769459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::0 63196948 84.09% 84.09% # Number of instructions fetched each cycle (Total) 6779459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::1 760434 1.01% 85.10% # Number of instructions fetched each cycle (Total) 6789459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::2 1555219 2.07% 87.17% # Number of instructions fetched each cycle (Total) 6799459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::3 695943 0.93% 88.10% # Number of instructions fetched each cycle (Total) 6809459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::4 2597980 3.46% 91.55% # Number of instructions fetched each cycle (Total) 6819459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::5 515321 0.69% 92.24% # Number of instructions fetched each cycle (Total) 6829459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::6 570202 0.76% 93.00% # Number of instructions fetched each cycle (Total) 6839459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::7 825200 1.10% 94.10% # Number of instructions fetched each cycle (Total) 6849459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::8 4437872 5.90% 100.00% # Number of instructions fetched each cycle (Total) 6858464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 6868464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 6878464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 6889459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rateDist::total 75155119 # Number of instructions fetched each cycle (Total) 6899459Ssaidi@eecs.umich.edusystem.cpu0.fetch.branchRate 0.121523 # Number of branch fetches per cycle 6909459Ssaidi@eecs.umich.edusystem.cpu0.fetch.rate 0.624936 # Number of inst fetches per cycle 6919459Ssaidi@eecs.umich.edusystem.cpu0.decode.IdleCycles 26159678 # Number of cycles decode is idle 6929459Ssaidi@eecs.umich.edusystem.cpu0.decode.BlockedCycles 36134055 # Number of cycles decode is blocked 6939459Ssaidi@eecs.umich.edusystem.cpu0.decode.RunCycles 10861438 # Number of cycles decode is running 6949459Ssaidi@eecs.umich.edusystem.cpu0.decode.UnblockCycles 929510 # Number of cycles decode is unblocking 6959459Ssaidi@eecs.umich.edusystem.cpu0.decode.SquashCycles 1070437 # Number of cycles decode is squashing 6969459Ssaidi@eecs.umich.edusystem.cpu0.decode.BranchResolved 506952 # Number of times decode resolved a branch 6979459Ssaidi@eecs.umich.edusystem.cpu0.decode.BranchMispred 35177 # Number of times decode detected a branch misprediction 6989459Ssaidi@eecs.umich.edusystem.cpu0.decode.DecodedInsts 62384726 # Number of instructions handled by decode 6999459Ssaidi@eecs.umich.edusystem.cpu0.decode.SquashedInsts 105081 # Number of squashed instructions handled by decode 7009459Ssaidi@eecs.umich.edusystem.cpu0.rename.SquashCycles 1070437 # Number of cycles rename is squashing 7019459Ssaidi@eecs.umich.edusystem.cpu0.rename.IdleCycles 27188236 # Number of cycles rename is idle 7029459Ssaidi@eecs.umich.edusystem.cpu0.rename.BlockCycles 14621537 # Number of cycles rename is blocking 7039459Ssaidi@eecs.umich.edusystem.cpu0.rename.serializeStallCycles 18000496 # count of cycles rename stalled for serializing inst 7049459Ssaidi@eecs.umich.edusystem.cpu0.rename.RunCycles 10158555 # Number of cycles rename is running 7059459Ssaidi@eecs.umich.edusystem.cpu0.rename.UnblockCycles 4115856 # Number of cycles rename is unblocking 7069459Ssaidi@eecs.umich.edusystem.cpu0.rename.RenamedInsts 58951339 # Number of instructions processed by rename 7079459Ssaidi@eecs.umich.edusystem.cpu0.rename.ROBFullEvents 6767 # Number of times rename has blocked due to ROB full 7089459Ssaidi@eecs.umich.edusystem.cpu0.rename.IQFullEvents 643786 # Number of times rename has blocked due to IQ full 7099459Ssaidi@eecs.umich.edusystem.cpu0.rename.LSQFullEvents 1455498 # Number of times rename has blocked due to LSQ full 7109459Ssaidi@eecs.umich.edusystem.cpu0.rename.RenamedOperands 39478397 # Number of destination operands rename has renamed 7119459Ssaidi@eecs.umich.edusystem.cpu0.rename.RenameLookups 71801839 # Number of register rename lookups that rename has made 7129459Ssaidi@eecs.umich.edusystem.cpu0.rename.int_rename_lookups 71417626 # Number of integer rename lookups 7139459Ssaidi@eecs.umich.edusystem.cpu0.rename.fp_rename_lookups 384213 # Number of floating rename lookups 7149459Ssaidi@eecs.umich.edusystem.cpu0.rename.CommittedMaps 34623741 # Number of HB maps that are committed 7159459Ssaidi@eecs.umich.edusystem.cpu0.rename.UndoneMaps 4854648 # Number of HB maps that are undone due to squashing 7169459Ssaidi@eecs.umich.edusystem.cpu0.rename.serializingInsts 1439423 # count of serializing insts renamed 7179459Ssaidi@eecs.umich.edusystem.cpu0.rename.tempSerializingInsts 209577 # count of temporary serializing insts renamed 7189459Ssaidi@eecs.umich.edusystem.cpu0.rename.skidInsts 11309679 # count of insts added to the skid buffer 7199459Ssaidi@eecs.umich.edusystem.cpu0.memDep0.insertedLoads 9204846 # Number of loads inserted to the mem dependence unit. 7209459Ssaidi@eecs.umich.edusystem.cpu0.memDep0.insertedStores 6035425 # Number of stores inserted to the mem dependence unit. 7219459Ssaidi@eecs.umich.edusystem.cpu0.memDep0.conflictingLoads 1140474 # Number of conflicting loads. 7229459Ssaidi@eecs.umich.edusystem.cpu0.memDep0.conflictingStores 743155 # Number of conflicting stores. 7239459Ssaidi@eecs.umich.edusystem.cpu0.iq.iqInstsAdded 52262338 # Number of instructions added to the IQ (excludes non-spec) 7249459Ssaidi@eecs.umich.edusystem.cpu0.iq.iqNonSpecInstsAdded 1790513 # Number of non-speculative instructions added to the IQ 7259459Ssaidi@eecs.umich.edusystem.cpu0.iq.iqInstsIssued 51072320 # Number of instructions issued 7269459Ssaidi@eecs.umich.edusystem.cpu0.iq.iqSquashedInstsIssued 91453 # Number of squashed instructions issued 7279459Ssaidi@eecs.umich.edusystem.cpu0.iq.iqSquashedInstsExamined 5903524 # Number of squashed instructions iterated over during squash; mainly for profiling 7289459Ssaidi@eecs.umich.edusystem.cpu0.iq.iqSquashedOperandsExamined 3097982 # Number of squashed operands that are examined and possibly removed from graph 7299459Ssaidi@eecs.umich.edusystem.cpu0.iq.iqSquashedNonSpecRemoved 1211963 # Number of squashed non-spec instructions that were removed 7309459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::samples 75155119 # Number of insts issued each cycle 7319459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::mean 0.679559 # Number of insts issued each cycle 7329459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::stdev 1.328921 # Number of insts issued each cycle 7338464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 7349459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::0 52460165 69.80% 69.80% # Number of insts issued each cycle 7359459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::1 10326519 13.74% 83.54% # Number of insts issued each cycle 7369459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::2 4642920 6.18% 89.72% # Number of insts issued each cycle 7379459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::3 3073584 4.09% 93.81% # Number of insts issued each cycle 7389459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::4 2437230 3.24% 97.05% # Number of insts issued each cycle 7399459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::5 1208862 1.61% 98.66% # Number of insts issued each cycle 7409459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::6 646282 0.86% 99.52% # Number of insts issued each cycle 7419459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::7 308169 0.41% 99.93% # Number of insts issued each cycle 7429459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::8 51388 0.07% 100.00% # Number of insts issued each cycle 7438464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 7448464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 7458464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 7469459Ssaidi@eecs.umich.edusystem.cpu0.iq.issued_per_cycle::total 75155119 # Number of insts issued each cycle 7478464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 7489459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::IntAlu 82854 12.32% 12.32% # attempts to use FU when none available 7499459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::IntMult 1 0.00% 12.32% # attempts to use FU when none available 7509459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::IntDiv 0 0.00% 12.32% # attempts to use FU when none available 7519459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.32% # attempts to use FU when none available 7529459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available 7539459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.32% # attempts to use FU when none available 7549459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::FloatMult 0 0.00% 12.32% # attempts to use FU when none available 7559459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.32% # attempts to use FU when none available 7569459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.32% # attempts to use FU when none available 7579459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.32% # attempts to use FU when none available 7589459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.32% # attempts to use FU when none available 7599459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.32% # attempts to use FU when none available 7609459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.32% # attempts to use FU when none available 7619459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.32% # attempts to use FU when none available 7629459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.32% # attempts to use FU when none available 7639459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdMult 0 0.00% 12.32% # attempts to use FU when none available 7649459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.32% # attempts to use FU when none available 7659459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdShift 0 0.00% 12.32% # attempts to use FU when none available 7669459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.32% # attempts to use FU when none available 7679459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.32% # attempts to use FU when none available 7689459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.32% # attempts to use FU when none available 7699459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.32% # attempts to use FU when none available 7709459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.32% # attempts to use FU when none available 7719459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.32% # attempts to use FU when none available 7729459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.32% # attempts to use FU when none available 7739459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.32% # attempts to use FU when none available 7749459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.32% # attempts to use FU when none available 7759459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.32% # attempts to use FU when none available 7769459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.32% # attempts to use FU when none available 7779459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::MemRead 311669 46.35% 58.67% # attempts to use FU when none available 7789459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_full::MemWrite 277938 41.33% 100.00% # attempts to use FU when none available 7798464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 7808464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 7819459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued 7829459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::IntAlu 35204584 68.93% 68.94% # Type of FU issued 7839459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::IntMult 56105 0.11% 69.05% # Type of FU issued 7849459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.05% # Type of FU issued 7859459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 69.08% # Type of FU issued 7869459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.08% # Type of FU issued 7879459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.08% # Type of FU issued 7889459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.08% # Type of FU issued 7899459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.08% # Type of FU issued 7909459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.08% # Type of FU issued 7919459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.08% # Type of FU issued 7929459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.08% # Type of FU issued 7939459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.08% # Type of FU issued 7949459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.08% # Type of FU issued 7959459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.08% # Type of FU issued 7969459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.08% # Type of FU issued 7979459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.08% # Type of FU issued 7989459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.08% # Type of FU issued 7999459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.08% # Type of FU issued 8009459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.08% # Type of FU issued 8019459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.08% # Type of FU issued 8029459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.08% # Type of FU issued 8039459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.08% # Type of FU issued 8049459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.08% # Type of FU issued 8059459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.08% # Type of FU issued 8069459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.08% # Type of FU issued 8079459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.08% # Type of FU issued 8089459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.08% # Type of FU issued 8099459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.08% # Type of FU issued 8109459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.08% # Type of FU issued 8119459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::MemRead 9153958 17.92% 87.01% # Type of FU issued 8129459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::MemWrite 5827340 11.41% 98.42% # Type of FU issued 8139459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::IprAccess 808994 1.58% 100.00% # Type of FU issued 8148464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 8159459Ssaidi@eecs.umich.edusystem.cpu0.iq.FU_type_0::total 51072320 # Type of FU issued 8169459Ssaidi@eecs.umich.edusystem.cpu0.iq.rate 0.501619 # Inst issue rate 8179459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_busy_cnt 672462 # FU busy when requested 8189459Ssaidi@eecs.umich.edusystem.cpu0.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst) 8199459Ssaidi@eecs.umich.edusystem.cpu0.iq.int_inst_queue_reads 177512873 # Number of integer instruction queue reads 8209459Ssaidi@eecs.umich.edusystem.cpu0.iq.int_inst_queue_writes 59702358 # Number of integer instruction queue writes 8219459Ssaidi@eecs.umich.edusystem.cpu0.iq.int_inst_queue_wakeup_accesses 50032811 # Number of integer instruction queue wakeup accesses 8229459Ssaidi@eecs.umich.edusystem.cpu0.iq.fp_inst_queue_reads 550800 # Number of floating instruction queue reads 8239459Ssaidi@eecs.umich.edusystem.cpu0.iq.fp_inst_queue_writes 266343 # Number of floating instruction queue writes 8249459Ssaidi@eecs.umich.edusystem.cpu0.iq.fp_inst_queue_wakeup_accesses 260046 # Number of floating instruction queue wakeup accesses 8259459Ssaidi@eecs.umich.edusystem.cpu0.iq.int_alu_accesses 51452584 # Number of integer alu accesses 8269459Ssaidi@eecs.umich.edusystem.cpu0.iq.fp_alu_accesses 288424 # Number of floating point alu accesses 8279459Ssaidi@eecs.umich.edusystem.cpu0.iew.lsq.thread0.forwLoads 541788 # Number of loads that had data forwarded from stores 8288464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 8299459Ssaidi@eecs.umich.edusystem.cpu0.iew.lsq.thread0.squashedLoads 1120800 # Number of loads squashed 8309459Ssaidi@eecs.umich.edusystem.cpu0.iew.lsq.thread0.ignoredResponses 2789 # Number of memory responses ignored because the instruction is squashed 8319459Ssaidi@eecs.umich.edusystem.cpu0.iew.lsq.thread0.memOrderViolation 12579 # Number of memory ordering violations 8329459Ssaidi@eecs.umich.edusystem.cpu0.iew.lsq.thread0.squashedStores 457772 # Number of stores squashed 8338464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 8348464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 8359459Ssaidi@eecs.umich.edusystem.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled 8369459Ssaidi@eecs.umich.edusystem.cpu0.iew.lsq.thread0.cacheBlocked 147130 # Number of times an access to memory failed due to the cache being blocked 8378464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 8389459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewSquashCycles 1070437 # Number of cycles IEW is squashing 8399459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewBlockCycles 10393328 # Number of cycles IEW is blocking 8409459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewUnblockCycles 793846 # Number of cycles IEW is unblocking 8419459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewDispatchedInsts 57261563 # Number of instructions dispatched to IQ 8429459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewDispSquashedInsts 642303 # Number of squashed instructions skipped by dispatch 8439459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewDispLoadInsts 9204846 # Number of dispatched load instructions 8449459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewDispStoreInsts 6035425 # Number of dispatched store instructions 8459459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewDispNonSpecInsts 1577054 # Number of dispatched non-speculative instructions 8469459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewIQFullEvents 582295 # Number of times the IQ has become full, causing a stall 8479459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewLSQFullEvents 5281 # Number of times the LSQ has become full, causing a stall 8489459Ssaidi@eecs.umich.edusystem.cpu0.iew.memOrderViolationEvents 12579 # Number of memory order violations 8499459Ssaidi@eecs.umich.edusystem.cpu0.iew.predictedTakenIncorrect 164111 # Number of branches that were predicted taken incorrectly 8509459Ssaidi@eecs.umich.edusystem.cpu0.iew.predictedNotTakenIncorrect 347239 # Number of branches that were predicted not taken incorrectly 8519459Ssaidi@eecs.umich.edusystem.cpu0.iew.branchMispredicts 511350 # Number of branch mispredicts detected at execute 8529459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewExecutedInsts 50686887 # Number of executed instructions 8539459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewExecLoadInsts 8851053 # Number of load instructions executed 8549459Ssaidi@eecs.umich.edusystem.cpu0.iew.iewExecSquashedInsts 385432 # Number of squashed instructions skipped in execute 8558464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 8569459Ssaidi@eecs.umich.edusystem.cpu0.iew.exec_nop 3208712 # number of nop insts executed 8579459Ssaidi@eecs.umich.edusystem.cpu0.iew.exec_refs 14632506 # number of memory reference insts executed 8589459Ssaidi@eecs.umich.edusystem.cpu0.iew.exec_branches 8068479 # Number of branches executed 8599459Ssaidi@eecs.umich.edusystem.cpu0.iew.exec_stores 5781453 # Number of stores executed 8609459Ssaidi@eecs.umich.edusystem.cpu0.iew.exec_rate 0.497833 # Inst execution rate 8619459Ssaidi@eecs.umich.edusystem.cpu0.iew.wb_sent 50383937 # cumulative count of insts sent to commit 8629459Ssaidi@eecs.umich.edusystem.cpu0.iew.wb_count 50292857 # cumulative count of insts written-back 8639459Ssaidi@eecs.umich.edusystem.cpu0.iew.wb_producers 25094352 # num instructions producing a value 8649459Ssaidi@eecs.umich.edusystem.cpu0.iew.wb_consumers 33818001 # num instructions consuming a value 8658464SN/Asystem.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 8669459Ssaidi@eecs.umich.edusystem.cpu0.iew.wb_rate 0.493963 # insts written-back per cycle 8679459Ssaidi@eecs.umich.edusystem.cpu0.iew.wb_fanout 0.742041 # average fanout of values written-back 8688464SN/Asystem.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 8699459Ssaidi@eecs.umich.edusystem.cpu0.commit.commitSquashedInsts 6371688 # The number of squashed insts skipped by commit 8709459Ssaidi@eecs.umich.edusystem.cpu0.commit.commitNonSpecStalls 578550 # The number of times commit has been forced to stall to communicate backwards 8719459Ssaidi@eecs.umich.edusystem.cpu0.commit.branchMispredicts 477828 # The number of times a branch was mispredicted 8729459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::samples 74084682 # Number of insts commited each cycle 8739459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::mean 0.685601 # Number of insts commited each cycle 8749459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::stdev 1.604018 # Number of insts commited each cycle 8758241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 8769459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::0 55026515 74.28% 74.28% # Number of insts commited each cycle 8779459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::1 7939418 10.72% 84.99% # Number of insts commited each cycle 8789459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::2 4342581 5.86% 90.85% # Number of insts commited each cycle 8799459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::3 2354466 3.18% 94.03% # Number of insts commited each cycle 8809459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::4 1312338 1.77% 95.80% # Number of insts commited each cycle 8819459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::5 550007 0.74% 96.55% # Number of insts commited each cycle 8829459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::6 466229 0.63% 97.17% # Number of insts commited each cycle 8839459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::7 437204 0.59% 97.76% # Number of insts commited each cycle 8849459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::8 1655924 2.24% 100.00% # Number of insts commited each cycle 8858241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 8868241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 8878241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 8889459Ssaidi@eecs.umich.edusystem.cpu0.commit.committed_per_cycle::total 74084682 # Number of insts commited each cycle 8899459Ssaidi@eecs.umich.edusystem.cpu0.commit.committedInsts 50792559 # Number of instructions committed 8909459Ssaidi@eecs.umich.edusystem.cpu0.commit.committedOps 50792559 # Number of ops (including micro ops) committed 8918241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 8929459Ssaidi@eecs.umich.edusystem.cpu0.commit.refs 13661699 # Number of memory references committed 8939459Ssaidi@eecs.umich.edusystem.cpu0.commit.loads 8084046 # Number of loads committed 8949459Ssaidi@eecs.umich.edusystem.cpu0.commit.membars 197074 # Number of memory barriers committed 8959459Ssaidi@eecs.umich.edusystem.cpu0.commit.branches 7671683 # Number of branches committed 8969459Ssaidi@eecs.umich.edusystem.cpu0.commit.fp_insts 257823 # Number of committed floating point instructions. 8979459Ssaidi@eecs.umich.edusystem.cpu0.commit.int_insts 47034170 # Number of committed integer instructions. 8989459Ssaidi@eecs.umich.edusystem.cpu0.commit.function_calls 648346 # Number of function calls committed. 8999459Ssaidi@eecs.umich.edusystem.cpu0.commit.bw_lim_events 1655924 # number cycles where commit BW limit reached 9008464SN/Asystem.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 9019459Ssaidi@eecs.umich.edusystem.cpu0.rob.rob_reads 129398549 # The number of ROB reads 9029459Ssaidi@eecs.umich.edusystem.cpu0.rob.rob_writes 115399767 # The number of ROB writes 9039459Ssaidi@eecs.umich.edusystem.cpu0.timesIdled 1054205 # Number of times that the entire CPU went into an idle state and unscheduled itself 9049459Ssaidi@eecs.umich.edusystem.cpu0.idleCycles 26659843 # Total number of cycles that the CPU has spent unscheduled due to idling 9059459Ssaidi@eecs.umich.edusystem.cpu0.quiesceCycles 3701617819 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 9069459Ssaidi@eecs.umich.edusystem.cpu0.committedInsts 47867129 # Number of Instructions Simulated 9079459Ssaidi@eecs.umich.edusystem.cpu0.committedOps 47867129 # Number of Ops (including micro ops) Simulated 9089459Ssaidi@eecs.umich.edusystem.cpu0.committedInsts_total 47867129 # Number of Instructions Simulated 9099459Ssaidi@eecs.umich.edusystem.cpu0.cpi 2.127033 # CPI: Cycles Per Instruction 9109459Ssaidi@eecs.umich.edusystem.cpu0.cpi_total 2.127033 # CPI: Total CPI of All Threads 9119459Ssaidi@eecs.umich.edusystem.cpu0.ipc 0.470138 # IPC: Instructions Per Cycle 9129459Ssaidi@eecs.umich.edusystem.cpu0.ipc_total 0.470138 # IPC: Total IPC of All Threads 9139459Ssaidi@eecs.umich.edusystem.cpu0.int_regfile_reads 66695316 # number of integer regfile reads 9149459Ssaidi@eecs.umich.edusystem.cpu0.int_regfile_writes 36408183 # number of integer regfile writes 9159459Ssaidi@eecs.umich.edusystem.cpu0.fp_regfile_reads 127649 # number of floating regfile reads 9169459Ssaidi@eecs.umich.edusystem.cpu0.fp_regfile_writes 129302 # number of floating regfile writes 9179459Ssaidi@eecs.umich.edusystem.cpu0.misc_regfile_reads 1695809 # number of misc regfile reads 9189459Ssaidi@eecs.umich.edusystem.cpu0.misc_regfile_writes 808592 # number of misc regfile writes 9195703SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 9205703SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 9215703SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 9225703SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 9238464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 9248983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 9258464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 9268464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 9278983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 9288464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 9298464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 9308983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 9318464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 9328464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 9338983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 9348464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 9358464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 9368983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 9378464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 9388464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 9398983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 9408464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 9418464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 9428983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 9438464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 9448464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 9458983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 9468464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 9478983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 9488464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 9495703SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 9509459Ssaidi@eecs.umich.edusystem.cpu0.icache.replacements 867960 # number of replacements 9519459Ssaidi@eecs.umich.edusystem.cpu0.icache.tagsinuse 510.328414 # Cycle average of tags in use 9529459Ssaidi@eecs.umich.edusystem.cpu0.icache.total_refs 6737923 # Total number of references to valid blocks. 9539459Ssaidi@eecs.umich.edusystem.cpu0.icache.sampled_refs 868472 # Sample count of references to valid blocks. 9549459Ssaidi@eecs.umich.edusystem.cpu0.icache.avg_refs 7.758365 # Average number of references to valid blocks. 9559459Ssaidi@eecs.umich.edusystem.cpu0.icache.warmup_cycle 20312098000 # Cycle when the warmup percentage was hit. 9569459Ssaidi@eecs.umich.edusystem.cpu0.icache.occ_blocks::cpu0.inst 510.328414 # Average occupied blocks per requestor 9579348SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy 9589348SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy 9599459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::cpu0.inst 6737923 # number of ReadReq hits 9609459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::total 6737923 # number of ReadReq hits 9619459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::cpu0.inst 6737923 # number of demand (read+write) hits 9629459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::total 6737923 # number of demand (read+write) hits 9639459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::cpu0.inst 6737923 # number of overall hits 9649459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::total 6737923 # number of overall hits 9659459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::cpu0.inst 912101 # number of ReadReq misses 9669459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::total 912101 # number of ReadReq misses 9679459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::cpu0.inst 912101 # number of demand (read+write) misses 9689459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::total 912101 # number of demand (read+write) misses 9699459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::cpu0.inst 912101 # number of overall misses 9709459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::total 912101 # number of overall misses 9719459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12723011493 # number of ReadReq miss cycles 9729459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_latency::total 12723011493 # number of ReadReq miss cycles 9739459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_latency::cpu0.inst 12723011493 # number of demand (read+write) miss cycles 9749459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_latency::total 12723011493 # number of demand (read+write) miss cycles 9759459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_latency::cpu0.inst 12723011493 # number of overall miss cycles 9769459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_latency::total 12723011493 # number of overall miss cycles 9779459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::cpu0.inst 7650024 # number of ReadReq accesses(hits+misses) 9789459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::total 7650024 # number of ReadReq accesses(hits+misses) 9799459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::cpu0.inst 7650024 # number of demand (read+write) accesses 9809459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::total 7650024 # number of demand (read+write) accesses 9819459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::cpu0.inst 7650024 # number of overall (read+write) accesses 9829459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::total 7650024 # number of overall (read+write) accesses 9839459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119229 # miss rate for ReadReq accesses 9849459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::total 0.119229 # miss rate for ReadReq accesses 9859459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.119229 # miss rate for demand accesses 9869459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::total 0.119229 # miss rate for demand accesses 9879459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.119229 # miss rate for overall accesses 9889459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::total 0.119229 # miss rate for overall accesses 9899459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13949.125692 # average ReadReq miss latency 9909459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_avg_miss_latency::total 13949.125692 # average ReadReq miss latency 9919459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency 9929459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_avg_miss_latency::total 13949.125692 # average overall miss latency 9939459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency 9949459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_avg_miss_latency::total 13949.125692 # average overall miss latency 9959459Ssaidi@eecs.umich.edusystem.cpu0.icache.blocked_cycles::no_mshrs 3314 # number of cycles access was blocked 9969459Ssaidi@eecs.umich.edusystem.cpu0.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked 9979459Ssaidi@eecs.umich.edusystem.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked 9989459Ssaidi@eecs.umich.edusystem.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked 9999459Ssaidi@eecs.umich.edusystem.cpu0.icache.avg_blocked_cycles::no_mshrs 23.013889 # average number of cycles each access was blocked 10009459Ssaidi@eecs.umich.edusystem.cpu0.icache.avg_blocked_cycles::no_targets 438 # average number of cycles each access was blocked 10018464SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 10028464SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 10039459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43445 # number of ReadReq MSHR hits 10049459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_hits::total 43445 # number of ReadReq MSHR hits 10059459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_hits::cpu0.inst 43445 # number of demand (read+write) MSHR hits 10069459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_hits::total 43445 # number of demand (read+write) MSHR hits 10079459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_hits::cpu0.inst 43445 # number of overall MSHR hits 10089459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_hits::total 43445 # number of overall MSHR hits 10099459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868656 # number of ReadReq MSHR misses 10109459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_misses::total 868656 # number of ReadReq MSHR misses 10119459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_misses::cpu0.inst 868656 # number of demand (read+write) MSHR misses 10129459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_misses::total 868656 # number of demand (read+write) MSHR misses 10139459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_misses::cpu0.inst 868656 # number of overall MSHR misses 10149459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_misses::total 868656 # number of overall MSHR misses 10159459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10487782996 # number of ReadReq MSHR miss cycles 10169459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_miss_latency::total 10487782996 # number of ReadReq MSHR miss cycles 10179459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10487782996 # number of demand (read+write) MSHR miss cycles 10189459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_miss_latency::total 10487782996 # number of demand (read+write) MSHR miss cycles 10199459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10487782996 # number of overall MSHR miss cycles 10209459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_miss_latency::total 10487782996 # number of overall MSHR miss cycles 10219459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for ReadReq accesses 10229459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113549 # mshr miss rate for ReadReq accesses 10239459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for demand accesses 10249459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_miss_rate::total 0.113549 # mshr miss rate for demand accesses 10259459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for overall accesses 10269459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_mshr_miss_rate::total 0.113549 # mshr miss rate for overall accesses 10279459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average ReadReq mshr miss latency 10289459Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12073.574575 # average ReadReq mshr miss latency 10299459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency 10309459Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency 10319459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency 10329459Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency 10338464SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 10349459Ssaidi@eecs.umich.edusystem.cpu0.dcache.replacements 1274576 # number of replacements 10359459Ssaidi@eecs.umich.edusystem.cpu0.dcache.tagsinuse 505.658053 # Cycle average of tags in use 10369459Ssaidi@eecs.umich.edusystem.cpu0.dcache.total_refs 10359284 # Total number of references to valid blocks. 10379459Ssaidi@eecs.umich.edusystem.cpu0.dcache.sampled_refs 1275088 # Sample count of references to valid blocks. 10389459Ssaidi@eecs.umich.edusystem.cpu0.dcache.avg_refs 8.124368 # Average number of references to valid blocks. 10399348SAli.Saidi@ARM.comsystem.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. 10409459Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_blocks::cpu0.data 505.658053 # Average occupied blocks per requestor 10419459Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_percent::cpu0.data 0.987613 # Average percentage of cache occupancy 10429459Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_percent::total 0.987613 # Average percentage of cache occupancy 10439459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::cpu0.data 6368256 # number of ReadReq hits 10449459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::total 6368256 # number of ReadReq hits 10459459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::cpu0.data 3633863 # number of WriteReq hits 10469459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::total 3633863 # number of WriteReq hits 10479459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160621 # number of LoadLockedReq hits 10489459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::total 160621 # number of LoadLockedReq hits 10499459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 185111 # number of StoreCondReq hits 10509459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::total 185111 # number of StoreCondReq hits 10519459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::cpu0.data 10002119 # number of demand (read+write) hits 10529459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::total 10002119 # number of demand (read+write) hits 10539459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::cpu0.data 10002119 # number of overall hits 10549459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::total 10002119 # number of overall hits 10559459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::cpu0.data 1588144 # number of ReadReq misses 10569459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::total 1588144 # number of ReadReq misses 10579459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::cpu0.data 1741180 # number of WriteReq misses 10589459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::total 1741180 # number of WriteReq misses 10599459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20406 # number of LoadLockedReq misses 10609459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::total 20406 # number of LoadLockedReq misses 10619459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 2921 # number of StoreCondReq misses 10629459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::total 2921 # number of StoreCondReq misses 10639459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::cpu0.data 3329324 # number of demand (read+write) misses 10649459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::total 3329324 # number of demand (read+write) misses 10659459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::cpu0.data 3329324 # number of overall misses 10669459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::total 3329324 # number of overall misses 10679459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34092049500 # number of ReadReq miss cycles 10689459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_latency::total 34092049500 # number of ReadReq miss cycles 10699459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69554473067 # number of WriteReq miss cycles 10709459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_latency::total 69554473067 # number of WriteReq miss cycles 10719459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288471000 # number of LoadLockedReq miss cycles 10729459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_latency::total 288471000 # number of LoadLockedReq miss cycles 10739459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21390500 # number of StoreCondReq miss cycles 10749459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_latency::total 21390500 # number of StoreCondReq miss cycles 10759459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_latency::cpu0.data 103646522567 # number of demand (read+write) miss cycles 10769459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_latency::total 103646522567 # number of demand (read+write) miss cycles 10779459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_latency::cpu0.data 103646522567 # number of overall miss cycles 10789459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_latency::total 103646522567 # number of overall miss cycles 10799459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7956400 # number of ReadReq accesses(hits+misses) 10809459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::total 7956400 # number of ReadReq accesses(hits+misses) 10819459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5375043 # number of WriteReq accesses(hits+misses) 10829459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::total 5375043 # number of WriteReq accesses(hits+misses) 10839459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181027 # number of LoadLockedReq accesses(hits+misses) 10849459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::total 181027 # number of LoadLockedReq accesses(hits+misses) 10859459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188032 # number of StoreCondReq accesses(hits+misses) 10869459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::total 188032 # number of StoreCondReq accesses(hits+misses) 10879459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::cpu0.data 13331443 # number of demand (read+write) accesses 10889459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::total 13331443 # number of demand (read+write) accesses 10899459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::cpu0.data 13331443 # number of overall (read+write) accesses 10909459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::total 13331443 # number of overall (read+write) accesses 10919459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199606 # miss rate for ReadReq accesses 10929459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::total 0.199606 # miss rate for ReadReq accesses 10939459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323938 # miss rate for WriteReq accesses 10949459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::total 0.323938 # miss rate for WriteReq accesses 10959459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112724 # miss rate for LoadLockedReq accesses 10969459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112724 # miss rate for LoadLockedReq accesses 10979459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015535 # miss rate for StoreCondReq accesses 10989459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.015535 # miss rate for StoreCondReq accesses 10999459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.249735 # miss rate for demand accesses 11009459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::total 0.249735 # miss rate for demand accesses 11019459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.249735 # miss rate for overall accesses 11029459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::total 0.249735 # miss rate for overall accesses 11039459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21466.598432 # average ReadReq miss latency 11049459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_miss_latency::total 21466.598432 # average ReadReq miss latency 11059459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39946.744775 # average WriteReq miss latency 11069459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_miss_latency::total 39946.744775 # average WriteReq miss latency 11079459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14136.577477 # average LoadLockedReq miss latency 11089459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14136.577477 # average LoadLockedReq miss latency 11099459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7323.005820 # average StoreCondReq miss latency 11109459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7323.005820 # average StoreCondReq miss latency 11119459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency 11129459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_avg_miss_latency::total 31131.401620 # average overall miss latency 11139459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency 11149459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_miss_latency::total 31131.401620 # average overall miss latency 11159459Ssaidi@eecs.umich.edusystem.cpu0.dcache.blocked_cycles::no_mshrs 2393556 # number of cycles access was blocked 11169459Ssaidi@eecs.umich.edusystem.cpu0.dcache.blocked_cycles::no_targets 1763 # number of cycles access was blocked 11179459Ssaidi@eecs.umich.edusystem.cpu0.dcache.blocked::no_mshrs 48538 # number of cycles access was blocked 11189289Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 11199459Ssaidi@eecs.umich.edusystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 49.313033 # average number of cycles each access was blocked 11209459Ssaidi@eecs.umich.edusystem.cpu0.dcache.avg_blocked_cycles::no_targets 251.857143 # average number of cycles each access was blocked 11218464SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 11228464SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 11239459Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::writebacks 749955 # number of writebacks 11249459Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::total 749955 # number of writebacks 11259459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 587926 # number of ReadReq MSHR hits 11269459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_hits::total 587926 # number of ReadReq MSHR hits 11279459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1468148 # number of WriteReq MSHR hits 11289459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_hits::total 1468148 # number of WriteReq MSHR hits 11299459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4517 # number of LoadLockedReq MSHR hits 11309459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 4517 # number of LoadLockedReq MSHR hits 11319459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_hits::cpu0.data 2056074 # number of demand (read+write) MSHR hits 11329459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_hits::total 2056074 # number of demand (read+write) MSHR hits 11339459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_hits::cpu0.data 2056074 # number of overall MSHR hits 11349459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_hits::total 2056074 # number of overall MSHR hits 11359459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1000218 # number of ReadReq MSHR misses 11369459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_misses::total 1000218 # number of ReadReq MSHR misses 11379459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273032 # number of WriteReq MSHR misses 11389459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_misses::total 273032 # number of WriteReq MSHR misses 11399459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15889 # number of LoadLockedReq MSHR misses 11409459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 15889 # number of LoadLockedReq MSHR misses 11419459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2921 # number of StoreCondReq MSHR misses 11429459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_mshr_misses::total 2921 # number of StoreCondReq MSHR misses 11439459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1273250 # number of demand (read+write) MSHR misses 11449459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_misses::total 1273250 # number of demand (read+write) MSHR misses 11459459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1273250 # number of overall MSHR misses 11469459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_misses::total 1273250 # number of overall MSHR misses 11479459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21325955000 # number of ReadReq MSHR miss cycles 11489459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 21325955000 # number of ReadReq MSHR miss cycles 11499459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10169026713 # number of WriteReq MSHR miss cycles 11509459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 10169026713 # number of WriteReq MSHR miss cycles 11519459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181062500 # number of LoadLockedReq MSHR miss cycles 11529459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181062500 # number of LoadLockedReq MSHR miss cycles 11539459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15548500 # number of StoreCondReq MSHR miss cycles 11549459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15548500 # number of StoreCondReq MSHR miss cycles 11559459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31494981713 # number of demand (read+write) MSHR miss cycles 11569459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_miss_latency::total 31494981713 # number of demand (read+write) MSHR miss cycles 11579459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31494981713 # number of overall MSHR miss cycles 11589459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_miss_latency::total 31494981713 # number of overall MSHR miss cycles 11599459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1455479000 # number of ReadReq MSHR uncacheable cycles 11609459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1455479000 # number of ReadReq MSHR uncacheable cycles 11619459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128324998 # number of WriteReq MSHR uncacheable cycles 11629459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128324998 # number of WriteReq MSHR uncacheable cycles 11639459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3583803998 # number of overall MSHR uncacheable cycles 11649459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 3583803998 # number of overall MSHR uncacheable cycles 11659459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125712 # mshr miss rate for ReadReq accesses 11669459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125712 # mshr miss rate for ReadReq accesses 11679459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050796 # mshr miss rate for WriteReq accesses 11689459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050796 # mshr miss rate for WriteReq accesses 11699459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087771 # mshr miss rate for LoadLockedReq accesses 11709459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087771 # mshr miss rate for LoadLockedReq accesses 11719459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015535 # mshr miss rate for StoreCondReq accesses 11729459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015535 # mshr miss rate for StoreCondReq accesses 11739459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for demand accesses 11749459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_mshr_miss_rate::total 0.095507 # mshr miss rate for demand accesses 11759459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for overall accesses 11769459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_mshr_miss_rate::total 0.095507 # mshr miss rate for overall accesses 11779459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21321.306955 # average ReadReq mshr miss latency 11789459Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21321.306955 # average ReadReq mshr miss latency 11799459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37244.816406 # average WriteReq mshr miss latency 11809459Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37244.816406 # average WriteReq mshr miss latency 11819459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11395.462269 # average LoadLockedReq mshr miss latency 11829459Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.462269 # average LoadLockedReq mshr miss latency 11839459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5323.005820 # average StoreCondReq mshr miss latency 11849459Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5323.005820 # average StoreCondReq mshr miss latency 11859459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency 11869459Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency 11879459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency 11889459Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency 11898835SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 11909055Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 11918835SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 11929055Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 11938835SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 11949055Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 11958464SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 11969481Snilay@cs.wisc.edusystem.cpu1.branchPred.lookups 2617746 # Number of BP lookups 11979481Snilay@cs.wisc.edusystem.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted 11989481Snilay@cs.wisc.edusystem.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect 11999481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups 12009481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBHits 873996 # Number of BTB hits 12019481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12029481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage 12039481Snilay@cs.wisc.edusystem.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target. 12049481Snilay@cs.wisc.edusystem.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions. 12058464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 12068464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 12078464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 12088464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 12099459Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_hits 1943067 # DTB read hits 12109459Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_misses 10795 # DTB read misses 12119459Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_acv 23 # DTB read access violations 12129459Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_accesses 324453 # DTB read accesses 12139459Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_hits 1254400 # DTB write hits 12149459Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_misses 2201 # DTB write misses 12159348SAli.Saidi@ARM.comsystem.cpu1.dtb.write_acv 63 # DTB write access violations 12169459Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_accesses 132933 # DTB write accesses 12179459Ssaidi@eecs.umich.edusystem.cpu1.dtb.data_hits 3197467 # DTB hits 12189459Ssaidi@eecs.umich.edusystem.cpu1.dtb.data_misses 12996 # DTB misses 12199459Ssaidi@eecs.umich.edusystem.cpu1.dtb.data_acv 86 # DTB access violations 12209459Ssaidi@eecs.umich.edusystem.cpu1.dtb.data_accesses 457386 # DTB accesses 12219459Ssaidi@eecs.umich.edusystem.cpu1.itb.fetch_hits 434450 # ITB hits 12229459Ssaidi@eecs.umich.edusystem.cpu1.itb.fetch_misses 7705 # ITB misses 12239459Ssaidi@eecs.umich.edusystem.cpu1.itb.fetch_acv 232 # ITB acv 12249459Ssaidi@eecs.umich.edusystem.cpu1.itb.fetch_accesses 442155 # ITB accesses 12258464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 12268464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 12278464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 12288464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 12298464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 12308464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 12318464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 12328464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 12338464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 12348464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 12358464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 12368464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 12379459Ssaidi@eecs.umich.edusystem.cpu1.numCycles 16039611 # number of cpu cycles simulated 12388464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 12398464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 12409459Ssaidi@eecs.umich.edusystem.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss 12419459Ssaidi@eecs.umich.edusystem.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed 12429459Ssaidi@eecs.umich.edusystem.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered 12439459Ssaidi@eecs.umich.edusystem.cpu1.fetch.predictedBranches 1056208 # Number of branches that fetch has predicted taken 12449459Ssaidi@eecs.umich.edusystem.cpu1.fetch.Cycles 2219979 # Number of cycles fetch has run and was not squashing or blocked 12459459Ssaidi@eecs.umich.edusystem.cpu1.fetch.SquashCycles 406574 # Number of cycles fetch has spent squashing 12469459Ssaidi@eecs.umich.edusystem.cpu1.fetch.BlockedCycles 6282819 # Number of cycles fetch has spent blocked 12479459Ssaidi@eecs.umich.edusystem.cpu1.fetch.MiscStallCycles 27064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 12489459Ssaidi@eecs.umich.edusystem.cpu1.fetch.PendingTrapStallCycles 67109 # Number of stall cycles due to pending traps 12499459Ssaidi@eecs.umich.edusystem.cpu1.fetch.PendingQuiesceStallCycles 53469 # Number of stall cycles due to pending quiesce instructions 12509459Ssaidi@eecs.umich.edusystem.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR 12519459Ssaidi@eecs.umich.edusystem.cpu1.fetch.CacheLines 1501296 # Number of cache lines fetched 12529459Ssaidi@eecs.umich.edusystem.cpu1.fetch.IcacheSquashes 52568 # Number of outstanding Icache misses that were squashed 12539459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::samples 14943285 # Number of instructions fetched each cycle (Total) 12549459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::mean 0.828159 # Number of instructions fetched each cycle (Total) 12559459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::stdev 2.202626 # Number of instructions fetched each cycle (Total) 12568464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 12579459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::0 12723306 85.14% 85.14% # Number of instructions fetched each cycle (Total) 12589459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::1 143447 0.96% 86.10% # Number of instructions fetched each cycle (Total) 12599459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::2 238457 1.60% 87.70% # Number of instructions fetched each cycle (Total) 12609459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::3 178791 1.20% 88.90% # Number of instructions fetched each cycle (Total) 12619459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::4 308600 2.07% 90.96% # Number of instructions fetched each cycle (Total) 12629459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::5 118341 0.79% 91.75% # Number of instructions fetched each cycle (Total) 12639459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::6 133550 0.89% 92.65% # Number of instructions fetched each cycle (Total) 12649459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::7 199066 1.33% 93.98% # Number of instructions fetched each cycle (Total) 12659459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::8 899727 6.02% 100.00% # Number of instructions fetched each cycle (Total) 12668464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 12678464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 12688464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 12699459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rateDist::total 14943285 # Number of instructions fetched each cycle (Total) 12709459Ssaidi@eecs.umich.edusystem.cpu1.fetch.branchRate 0.163205 # Number of branch fetches per cycle 12719459Ssaidi@eecs.umich.edusystem.cpu1.fetch.rate 0.771553 # Number of inst fetches per cycle 12729459Ssaidi@eecs.umich.edusystem.cpu1.decode.IdleCycles 5967965 # Number of cycles decode is idle 12739459Ssaidi@eecs.umich.edusystem.cpu1.decode.BlockedCycles 6534138 # Number of cycles decode is blocked 12749459Ssaidi@eecs.umich.edusystem.cpu1.decode.RunCycles 2076282 # Number of cycles decode is running 12759459Ssaidi@eecs.umich.edusystem.cpu1.decode.UnblockCycles 111928 # Number of cycles decode is unblocking 12769459Ssaidi@eecs.umich.edusystem.cpu1.decode.SquashCycles 252971 # Number of cycles decode is squashing 12779459Ssaidi@eecs.umich.edusystem.cpu1.decode.BranchResolved 114663 # Number of times decode resolved a branch 12789459Ssaidi@eecs.umich.edusystem.cpu1.decode.BranchMispred 7593 # Number of times decode detected a branch misprediction 12799459Ssaidi@eecs.umich.edusystem.cpu1.decode.DecodedInsts 12129871 # Number of instructions handled by decode 12809459Ssaidi@eecs.umich.edusystem.cpu1.decode.SquashedInsts 22496 # Number of squashed instructions handled by decode 12819459Ssaidi@eecs.umich.edusystem.cpu1.rename.SquashCycles 252971 # Number of cycles rename is squashing 12829459Ssaidi@eecs.umich.edusystem.cpu1.rename.IdleCycles 6175430 # Number of cycles rename is idle 12839459Ssaidi@eecs.umich.edusystem.cpu1.rename.BlockCycles 499012 # Number of cycles rename is blocking 12849459Ssaidi@eecs.umich.edusystem.cpu1.rename.serializeStallCycles 5393527 # count of cycles rename stalled for serializing inst 12859459Ssaidi@eecs.umich.edusystem.cpu1.rename.RunCycles 1978606 # Number of cycles rename is running 12869459Ssaidi@eecs.umich.edusystem.cpu1.rename.UnblockCycles 643737 # Number of cycles rename is unblocking 12879459Ssaidi@eecs.umich.edusystem.cpu1.rename.RenamedInsts 11250530 # Number of instructions processed by rename 12889459Ssaidi@eecs.umich.edusystem.cpu1.rename.ROBFullEvents 66 # Number of times rename has blocked due to ROB full 12899459Ssaidi@eecs.umich.edusystem.cpu1.rename.IQFullEvents 56207 # Number of times rename has blocked due to IQ full 12909459Ssaidi@eecs.umich.edusystem.cpu1.rename.LSQFullEvents 157985 # Number of times rename has blocked due to LSQ full 12919459Ssaidi@eecs.umich.edusystem.cpu1.rename.RenamedOperands 7407591 # Number of destination operands rename has renamed 12929459Ssaidi@eecs.umich.edusystem.cpu1.rename.RenameLookups 13449617 # Number of register rename lookups that rename has made 12939459Ssaidi@eecs.umich.edusystem.cpu1.rename.int_rename_lookups 13309138 # Number of integer rename lookups 12949459Ssaidi@eecs.umich.edusystem.cpu1.rename.fp_rename_lookups 140479 # Number of floating rename lookups 12959459Ssaidi@eecs.umich.edusystem.cpu1.rename.CommittedMaps 6324692 # Number of HB maps that are committed 12969459Ssaidi@eecs.umich.edusystem.cpu1.rename.UndoneMaps 1082899 # Number of HB maps that are undone due to squashing 12979459Ssaidi@eecs.umich.edusystem.cpu1.rename.serializingInsts 450684 # count of serializing insts renamed 12989459Ssaidi@eecs.umich.edusystem.cpu1.rename.tempSerializingInsts 43314 # count of temporary serializing insts renamed 12999459Ssaidi@eecs.umich.edusystem.cpu1.rename.skidInsts 1976964 # count of insts added to the skid buffer 13009459Ssaidi@eecs.umich.edusystem.cpu1.memDep0.insertedLoads 2055976 # Number of loads inserted to the mem dependence unit. 13019459Ssaidi@eecs.umich.edusystem.cpu1.memDep0.insertedStores 1329039 # Number of stores inserted to the mem dependence unit. 13029459Ssaidi@eecs.umich.edusystem.cpu1.memDep0.conflictingLoads 193469 # Number of conflicting loads. 13039459Ssaidi@eecs.umich.edusystem.cpu1.memDep0.conflictingStores 109268 # Number of conflicting stores. 13049459Ssaidi@eecs.umich.edusystem.cpu1.iq.iqInstsAdded 9879442 # Number of instructions added to the IQ (excludes non-spec) 13059459Ssaidi@eecs.umich.edusystem.cpu1.iq.iqNonSpecInstsAdded 495628 # Number of non-speculative instructions added to the IQ 13069459Ssaidi@eecs.umich.edusystem.cpu1.iq.iqInstsIssued 9611427 # Number of instructions issued 13079459Ssaidi@eecs.umich.edusystem.cpu1.iq.iqSquashedInstsIssued 29957 # Number of squashed instructions issued 13089459Ssaidi@eecs.umich.edusystem.cpu1.iq.iqSquashedInstsExamined 1443490 # Number of squashed instructions iterated over during squash; mainly for profiling 13099459Ssaidi@eecs.umich.edusystem.cpu1.iq.iqSquashedOperandsExamined 718060 # Number of squashed operands that are examined and possibly removed from graph 13109459Ssaidi@eecs.umich.edusystem.cpu1.iq.iqSquashedNonSpecRemoved 356268 # Number of squashed non-spec instructions that were removed 13119459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::samples 14943285 # Number of insts issued each cycle 13129459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::mean 0.643194 # Number of insts issued each cycle 13139459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::stdev 1.319140 # Number of insts issued each cycle 13148464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 13159459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::0 10722627 71.76% 71.76% # Number of insts issued each cycle 13169459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::1 1934278 12.94% 84.70% # Number of insts issued each cycle 13179459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::2 829364 5.55% 90.25% # Number of insts issued each cycle 13189459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::3 551304 3.69% 93.94% # Number of insts issued each cycle 13199459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::4 470726 3.15% 97.09% # Number of insts issued each cycle 13209459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::5 216087 1.45% 98.54% # Number of insts issued each cycle 13219459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::6 139402 0.93% 99.47% # Number of insts issued each cycle 13229459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::7 71218 0.48% 99.94% # Number of insts issued each cycle 13239459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::8 8279 0.06% 100.00% # Number of insts issued each cycle 13248464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 13258464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 13268464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 13279459Ssaidi@eecs.umich.edusystem.cpu1.iq.issued_per_cycle::total 14943285 # Number of insts issued each cycle 13288464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 13299459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::IntAlu 3634 1.84% 1.84% # attempts to use FU when none available 13309459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available 13319459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available 13329459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available 13339459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available 13349459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available 13359459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available 13369459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available 13379459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available 13389459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available 13399459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available 13409459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available 13419459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available 13429459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available 13439459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available 13449459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available 13459459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available 13469459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available 13479459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available 13489459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available 13499459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available 13509459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available 13519459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available 13529459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available 13539459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available 13549459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available 13559459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available 13569459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available 13579459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available 13589459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::MemRead 107033 54.32% 56.16% # attempts to use FU when none available 13599459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_full::MemWrite 86373 43.84% 100.00% # attempts to use FU when none available 13608464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 13618464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 13629459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued 13639459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::IntAlu 5997328 62.40% 62.43% # Type of FU issued 13649459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::IntMult 16465 0.17% 62.61% # Type of FU issued 13659459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued 13669459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::FloatAdd 10793 0.11% 62.72% # Type of FU issued 13679459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.72% # Type of FU issued 13689459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.72% # Type of FU issued 13699459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.72% # Type of FU issued 13709459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.74% # Type of FU issued 13719459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued 13729459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued 13739459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued 13749459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued 13759459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued 13769459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued 13779459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued 13789459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued 13799459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued 13809459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued 13819459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued 13829459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued 13839459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued 13849459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued 13859459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued 13869459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued 13879459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued 13889459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% # Type of FU issued 13899459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% # Type of FU issued 13909459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% # Type of FU issued 13919459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% # Type of FU issued 13929459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::MemRead 2032935 21.15% 83.89% # Type of FU issued 13939459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::MemWrite 1277891 13.30% 97.18% # Type of FU issued 13949459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::IprAccess 270726 2.82% 100.00% # Type of FU issued 13958464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 13969459Ssaidi@eecs.umich.edusystem.cpu1.iq.FU_type_0::total 9611427 # Type of FU issued 13979459Ssaidi@eecs.umich.edusystem.cpu1.iq.rate 0.599231 # Inst issue rate 13989459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_busy_cnt 197040 # FU busy when requested 13999459Ssaidi@eecs.umich.edusystem.cpu1.iq.fu_busy_rate 0.020501 # FU busy rate (busy events/executed inst) 14009459Ssaidi@eecs.umich.edusystem.cpu1.iq.int_inst_queue_reads 34189984 # Number of integer instruction queue reads 14019459Ssaidi@eecs.umich.edusystem.cpu1.iq.int_inst_queue_writes 11721176 # Number of integer instruction queue writes 14029459Ssaidi@eecs.umich.edusystem.cpu1.iq.int_inst_queue_wakeup_accesses 9344184 # Number of integer instruction queue wakeup accesses 14039459Ssaidi@eecs.umich.edusystem.cpu1.iq.fp_inst_queue_reads 203152 # Number of floating instruction queue reads 14049459Ssaidi@eecs.umich.edusystem.cpu1.iq.fp_inst_queue_writes 99152 # Number of floating instruction queue writes 14059459Ssaidi@eecs.umich.edusystem.cpu1.iq.fp_inst_queue_wakeup_accesses 96176 # Number of floating instruction queue wakeup accesses 14069459Ssaidi@eecs.umich.edusystem.cpu1.iq.int_alu_accesses 9699010 # Number of integer alu accesses 14079459Ssaidi@eecs.umich.edusystem.cpu1.iq.fp_alu_accesses 105931 # Number of floating point alu accesses 14089459Ssaidi@eecs.umich.edusystem.cpu1.iew.lsq.thread0.forwLoads 93506 # Number of loads that had data forwarded from stores 14098464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 14109459Ssaidi@eecs.umich.edusystem.cpu1.iew.lsq.thread0.squashedLoads 286352 # Number of loads squashed 14119459Ssaidi@eecs.umich.edusystem.cpu1.iew.lsq.thread0.ignoredResponses 1028 # Number of memory responses ignored because the instruction is squashed 14129459Ssaidi@eecs.umich.edusystem.cpu1.iew.lsq.thread0.memOrderViolation 1836 # Number of memory ordering violations 14139459Ssaidi@eecs.umich.edusystem.cpu1.iew.lsq.thread0.squashedStores 129863 # Number of stores squashed 14148464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 14158464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 14169459Ssaidi@eecs.umich.edusystem.cpu1.iew.lsq.thread0.rescheduledLoads 382 # Number of loads that were rescheduled 14179459Ssaidi@eecs.umich.edusystem.cpu1.iew.lsq.thread0.cacheBlocked 9210 # Number of times an access to memory failed due to the cache being blocked 14188464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 14199459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewSquashCycles 252971 # Number of cycles IEW is squashing 14209459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewBlockCycles 330484 # Number of cycles IEW is blocking 14219459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewUnblockCycles 40597 # Number of cycles IEW is unblocking 14229459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewDispatchedInsts 10884350 # Number of instructions dispatched to IQ 14239459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewDispSquashedInsts 145943 # Number of squashed instructions skipped by dispatch 14249459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewDispLoadInsts 2055976 # Number of dispatched load instructions 14259459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewDispStoreInsts 1329039 # Number of dispatched store instructions 14269459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewDispNonSpecInsts 449000 # Number of dispatched non-speculative instructions 14279459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewIQFullEvents 33362 # Number of times the IQ has become full, causing a stall 14289459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewLSQFullEvents 2246 # Number of times the LSQ has become full, causing a stall 14299459Ssaidi@eecs.umich.edusystem.cpu1.iew.memOrderViolationEvents 1836 # Number of memory order violations 14309459Ssaidi@eecs.umich.edusystem.cpu1.iew.predictedTakenIncorrect 35752 # Number of branches that were predicted taken incorrectly 14319459Ssaidi@eecs.umich.edusystem.cpu1.iew.predictedNotTakenIncorrect 100142 # Number of branches that were predicted not taken incorrectly 14329459Ssaidi@eecs.umich.edusystem.cpu1.iew.branchMispredicts 135894 # Number of branch mispredicts detected at execute 14339459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewExecutedInsts 9521603 # Number of executed instructions 14349459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewExecLoadInsts 1961135 # Number of load instructions executed 14359459Ssaidi@eecs.umich.edusystem.cpu1.iew.iewExecSquashedInsts 89824 # Number of squashed instructions skipped in execute 14368464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 14379459Ssaidi@eecs.umich.edusystem.cpu1.iew.exec_nop 509280 # number of nop insts executed 14389459Ssaidi@eecs.umich.edusystem.cpu1.iew.exec_refs 3223669 # number of memory reference insts executed 14399459Ssaidi@eecs.umich.edusystem.cpu1.iew.exec_branches 1421889 # Number of branches executed 14409459Ssaidi@eecs.umich.edusystem.cpu1.iew.exec_stores 1262534 # Number of stores executed 14419459Ssaidi@eecs.umich.edusystem.cpu1.iew.exec_rate 0.593631 # Inst execution rate 14429459Ssaidi@eecs.umich.edusystem.cpu1.iew.wb_sent 9469121 # cumulative count of insts sent to commit 14439459Ssaidi@eecs.umich.edusystem.cpu1.iew.wb_count 9440360 # cumulative count of insts written-back 14449459Ssaidi@eecs.umich.edusystem.cpu1.iew.wb_producers 4419848 # num instructions producing a value 14459459Ssaidi@eecs.umich.edusystem.cpu1.iew.wb_consumers 6207573 # num instructions consuming a value 14468464SN/Asystem.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 14479459Ssaidi@eecs.umich.edusystem.cpu1.iew.wb_rate 0.588565 # insts written-back per cycle 14489459Ssaidi@eecs.umich.edusystem.cpu1.iew.wb_fanout 0.712009 # average fanout of values written-back 14498464SN/Asystem.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 14509459Ssaidi@eecs.umich.edusystem.cpu1.commit.commitSquashedInsts 1489613 # The number of squashed insts skipped by commit 14519459Ssaidi@eecs.umich.edusystem.cpu1.commit.commitNonSpecStalls 139360 # The number of times commit has been forced to stall to communicate backwards 14529459Ssaidi@eecs.umich.edusystem.cpu1.commit.branchMispredicts 127942 # The number of times a branch was mispredicted 14539459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::samples 14690314 # Number of insts commited each cycle 14549459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::mean 0.634143 # Number of insts commited each cycle 14559459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::stdev 1.577922 # Number of insts commited each cycle 14568464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 14579459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::0 11205689 76.28% 76.28% # Number of insts commited each cycle 14589459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::1 1626477 11.07% 87.35% # Number of insts commited each cycle 14599459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::2 606444 4.13% 91.48% # Number of insts commited each cycle 14609459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::3 368240 2.51% 93.99% # Number of insts commited each cycle 14619459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::4 264133 1.80% 95.78% # Number of insts commited each cycle 14629459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::5 104886 0.71% 96.50% # Number of insts commited each cycle 14639459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::6 108759 0.74% 97.24% # Number of insts commited each cycle 14649459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::7 107326 0.73% 97.97% # Number of insts commited each cycle 14659459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::8 298360 2.03% 100.00% # Number of insts commited each cycle 14668464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 14678464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 14688464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 14699459Ssaidi@eecs.umich.edusystem.cpu1.commit.committed_per_cycle::total 14690314 # Number of insts commited each cycle 14709459Ssaidi@eecs.umich.edusystem.cpu1.commit.committedInsts 9315763 # Number of instructions committed 14719459Ssaidi@eecs.umich.edusystem.cpu1.commit.committedOps 9315763 # Number of ops (including micro ops) committed 14728464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 14739459Ssaidi@eecs.umich.edusystem.cpu1.commit.refs 2968800 # Number of memory references committed 14749459Ssaidi@eecs.umich.edusystem.cpu1.commit.loads 1769624 # Number of loads committed 14759459Ssaidi@eecs.umich.edusystem.cpu1.commit.membars 44277 # Number of memory barriers committed 14769459Ssaidi@eecs.umich.edusystem.cpu1.commit.branches 1334383 # Number of branches committed 14779459Ssaidi@eecs.umich.edusystem.cpu1.commit.fp_insts 94889 # Number of committed floating point instructions. 14789459Ssaidi@eecs.umich.edusystem.cpu1.commit.int_insts 8635888 # Number of committed integer instructions. 14799459Ssaidi@eecs.umich.edusystem.cpu1.commit.function_calls 148923 # Number of function calls committed. 14809459Ssaidi@eecs.umich.edusystem.cpu1.commit.bw_lim_events 298360 # number cycles where commit BW limit reached 14818464SN/Asystem.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 14829459Ssaidi@eecs.umich.edusystem.cpu1.rob.rob_reads 25106022 # The number of ROB reads 14839459Ssaidi@eecs.umich.edusystem.cpu1.rob.rob_writes 21862282 # The number of ROB writes 14849459Ssaidi@eecs.umich.edusystem.cpu1.timesIdled 131003 # Number of times that the entire CPU went into an idle state and unscheduled itself 14859459Ssaidi@eecs.umich.edusystem.cpu1.idleCycles 1096326 # Total number of cycles that the CPU has spent unscheduled due to idling 14869459Ssaidi@eecs.umich.edusystem.cpu1.quiesceCycles 3786825078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 14879459Ssaidi@eecs.umich.edusystem.cpu1.committedInsts 8868192 # Number of Instructions Simulated 14889459Ssaidi@eecs.umich.edusystem.cpu1.committedOps 8868192 # Number of Ops (including micro ops) Simulated 14899459Ssaidi@eecs.umich.edusystem.cpu1.committedInsts_total 8868192 # Number of Instructions Simulated 14909459Ssaidi@eecs.umich.edusystem.cpu1.cpi 1.808668 # CPI: Cycles Per Instruction 14919459Ssaidi@eecs.umich.edusystem.cpu1.cpi_total 1.808668 # CPI: Total CPI of All Threads 14929459Ssaidi@eecs.umich.edusystem.cpu1.ipc 0.552893 # IPC: Instructions Per Cycle 14939459Ssaidi@eecs.umich.edusystem.cpu1.ipc_total 0.552893 # IPC: Total IPC of All Threads 14949459Ssaidi@eecs.umich.edusystem.cpu1.int_regfile_reads 12288735 # number of integer regfile reads 14959459Ssaidi@eecs.umich.edusystem.cpu1.int_regfile_writes 6719305 # number of integer regfile writes 14969459Ssaidi@eecs.umich.edusystem.cpu1.fp_regfile_reads 52595 # number of floating regfile reads 14979459Ssaidi@eecs.umich.edusystem.cpu1.fp_regfile_writes 52295 # number of floating regfile writes 14989459Ssaidi@eecs.umich.edusystem.cpu1.misc_regfile_reads 519807 # number of misc regfile reads 14999459Ssaidi@eecs.umich.edusystem.cpu1.misc_regfile_writes 218837 # number of misc regfile writes 15009459Ssaidi@eecs.umich.edusystem.cpu1.icache.replacements 223384 # number of replacements 15019459Ssaidi@eecs.umich.edusystem.cpu1.icache.tagsinuse 470.911172 # Cycle average of tags in use 15029459Ssaidi@eecs.umich.edusystem.cpu1.icache.total_refs 1268764 # Total number of references to valid blocks. 15039459Ssaidi@eecs.umich.edusystem.cpu1.icache.sampled_refs 223896 # Sample count of references to valid blocks. 15049459Ssaidi@eecs.umich.edusystem.cpu1.icache.avg_refs 5.666756 # Average number of references to valid blocks. 15059459Ssaidi@eecs.umich.edusystem.cpu1.icache.warmup_cycle 1876151234000 # Cycle when the warmup percentage was hit. 15069459Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_blocks::cpu1.inst 470.911172 # Average occupied blocks per requestor 15079459Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_percent::cpu1.inst 0.919748 # Average percentage of cache occupancy 15089459Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_percent::total 0.919748 # Average percentage of cache occupancy 15099459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::cpu1.inst 1268764 # number of ReadReq hits 15109459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::total 1268764 # number of ReadReq hits 15119459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::cpu1.inst 1268764 # number of demand (read+write) hits 15129459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::total 1268764 # number of demand (read+write) hits 15139459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::cpu1.inst 1268764 # number of overall hits 15149459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::total 1268764 # number of overall hits 15159459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::cpu1.inst 232532 # number of ReadReq misses 15169459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::total 232532 # number of ReadReq misses 15179459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::cpu1.inst 232532 # number of demand (read+write) misses 15189459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::total 232532 # number of demand (read+write) misses 15199459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::cpu1.inst 232532 # number of overall misses 15209459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::total 232532 # number of overall misses 15219459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3191119498 # number of ReadReq miss cycles 15229459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_latency::total 3191119498 # number of ReadReq miss cycles 15239459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_latency::cpu1.inst 3191119498 # number of demand (read+write) miss cycles 15249459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_latency::total 3191119498 # number of demand (read+write) miss cycles 15259459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_latency::cpu1.inst 3191119498 # number of overall miss cycles 15269459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_latency::total 3191119498 # number of overall miss cycles 15279459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1501296 # number of ReadReq accesses(hits+misses) 15289459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::total 1501296 # number of ReadReq accesses(hits+misses) 15299459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::cpu1.inst 1501296 # number of demand (read+write) accesses 15309459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::total 1501296 # number of demand (read+write) accesses 15319459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::cpu1.inst 1501296 # number of overall (read+write) accesses 15329459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::total 1501296 # number of overall (read+write) accesses 15339459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154888 # miss rate for ReadReq accesses 15349459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::total 0.154888 # miss rate for ReadReq accesses 15359459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.154888 # miss rate for demand accesses 15369459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::total 0.154888 # miss rate for demand accesses 15379459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.154888 # miss rate for overall accesses 15389459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::total 0.154888 # miss rate for overall accesses 15399459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13723.356347 # average ReadReq miss latency 15409459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_avg_miss_latency::total 13723.356347 # average ReadReq miss latency 15419459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency 15429459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_avg_miss_latency::total 13723.356347 # average overall miss latency 15439459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency 15449459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_avg_miss_latency::total 13723.356347 # average overall miss latency 15459459Ssaidi@eecs.umich.edusystem.cpu1.icache.blocked_cycles::no_mshrs 852 # number of cycles access was blocked 15469459Ssaidi@eecs.umich.edusystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 15479459Ssaidi@eecs.umich.edusystem.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked 15489459Ssaidi@eecs.umich.edusystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 15499459Ssaidi@eecs.umich.edusystem.cpu1.icache.avg_blocked_cycles::no_mshrs 37.043478 # average number of cycles each access was blocked 15509459Ssaidi@eecs.umich.edusystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 15518464SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 15528464SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 15539459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits 15549459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits 15559459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits 15569459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits 15579459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits 15589459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits 15599459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223964 # number of ReadReq MSHR misses 15609459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_misses::total 223964 # number of ReadReq MSHR misses 15619459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_misses::cpu1.inst 223964 # number of demand (read+write) MSHR misses 15629459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_misses::total 223964 # number of demand (read+write) MSHR misses 15639459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_misses::cpu1.inst 223964 # number of overall MSHR misses 15649459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_misses::total 223964 # number of overall MSHR misses 15659459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2651052998 # number of ReadReq MSHR miss cycles 15669459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_miss_latency::total 2651052998 # number of ReadReq MSHR miss cycles 15679459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2651052998 # number of demand (read+write) MSHR miss cycles 15689459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_miss_latency::total 2651052998 # number of demand (read+write) MSHR miss cycles 15699459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2651052998 # number of overall MSHR miss cycles 15709459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_miss_latency::total 2651052998 # number of overall MSHR miss cycles 15719459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for ReadReq accesses 15729459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.149180 # mshr miss rate for ReadReq accesses 15739459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for demand accesses 15749459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_mshr_miss_rate::total 0.149180 # mshr miss rate for demand accesses 15759459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for overall accesses 15769459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_mshr_miss_rate::total 0.149180 # mshr miss rate for overall accesses 15779459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average ReadReq mshr miss latency 15789459Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11836.960395 # average ReadReq mshr miss latency 15799459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency 15809459Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency 15819459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency 15829459Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency 15838464SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 15849459Ssaidi@eecs.umich.edusystem.cpu1.dcache.replacements 107089 # number of replacements 15859459Ssaidi@eecs.umich.edusystem.cpu1.dcache.tagsinuse 492.773988 # Cycle average of tags in use 15869459Ssaidi@eecs.umich.edusystem.cpu1.dcache.total_refs 2615920 # Total number of references to valid blocks. 15879459Ssaidi@eecs.umich.edusystem.cpu1.dcache.sampled_refs 107493 # Sample count of references to valid blocks. 15889459Ssaidi@eecs.umich.edusystem.cpu1.dcache.avg_refs 24.335724 # Average number of references to valid blocks. 15899459Ssaidi@eecs.umich.edusystem.cpu1.dcache.warmup_cycle 38980492000 # Cycle when the warmup percentage was hit. 15909459Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_blocks::cpu1.data 492.773988 # Average occupied blocks per requestor 15919459Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_percent::cpu1.data 0.962449 # Average percentage of cache occupancy 15929459Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_percent::total 0.962449 # Average percentage of cache occupancy 15939459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::cpu1.data 1604976 # number of ReadReq hits 15949459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::total 1604976 # number of ReadReq hits 15959459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::cpu1.data 940707 # number of WriteReq hits 15969459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::total 940707 # number of WriteReq hits 15979459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33481 # number of LoadLockedReq hits 15989459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::total 33481 # number of LoadLockedReq hits 15999459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 32051 # number of StoreCondReq hits 16009459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::total 32051 # number of StoreCondReq hits 16019459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::cpu1.data 2545683 # number of demand (read+write) hits 16029459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::total 2545683 # number of demand (read+write) hits 16039459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::cpu1.data 2545683 # number of overall hits 16049459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::total 2545683 # number of overall hits 16059459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::cpu1.data 206048 # number of ReadReq misses 16069459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::total 206048 # number of ReadReq misses 16079459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::cpu1.data 217271 # number of WriteReq misses 16089459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::total 217271 # number of WriteReq misses 16099459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5237 # number of LoadLockedReq misses 16109459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::total 5237 # number of LoadLockedReq misses 16119459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 3060 # number of StoreCondReq misses 16129459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::total 3060 # number of StoreCondReq misses 16139459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::cpu1.data 423319 # number of demand (read+write) misses 16149459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::total 423319 # number of demand (read+write) misses 16159459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::cpu1.data 423319 # number of overall misses 16169459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::total 423319 # number of overall misses 16179459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3148302000 # number of ReadReq miss cycles 16189459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_latency::total 3148302000 # number of ReadReq miss cycles 16199459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8860772084 # number of WriteReq miss cycles 16209459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_latency::total 8860772084 # number of WriteReq miss cycles 16219459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54690000 # number of LoadLockedReq miss cycles 16229459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_latency::total 54690000 # number of LoadLockedReq miss cycles 16239459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22134000 # number of StoreCondReq miss cycles 16249459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_latency::total 22134000 # number of StoreCondReq miss cycles 16259459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_latency::cpu1.data 12009074084 # number of demand (read+write) miss cycles 16269459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_latency::total 12009074084 # number of demand (read+write) miss cycles 16279459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_latency::cpu1.data 12009074084 # number of overall miss cycles 16289459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_latency::total 12009074084 # number of overall miss cycles 16299459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1811024 # number of ReadReq accesses(hits+misses) 16309459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::total 1811024 # number of ReadReq accesses(hits+misses) 16319459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1157978 # number of WriteReq accesses(hits+misses) 16329459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::total 1157978 # number of WriteReq accesses(hits+misses) 16339459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38718 # number of LoadLockedReq accesses(hits+misses) 16349459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::total 38718 # number of LoadLockedReq accesses(hits+misses) 16359459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35111 # number of StoreCondReq accesses(hits+misses) 16369459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::total 35111 # number of StoreCondReq accesses(hits+misses) 16379459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::cpu1.data 2969002 # number of demand (read+write) accesses 16389459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::total 2969002 # number of demand (read+write) accesses 16399459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::cpu1.data 2969002 # number of overall (read+write) accesses 16409459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::total 2969002 # number of overall (read+write) accesses 16419459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.113774 # miss rate for ReadReq accesses 16429459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::total 0.113774 # miss rate for ReadReq accesses 16439459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187630 # miss rate for WriteReq accesses 16449459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::total 0.187630 # miss rate for WriteReq accesses 16459459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135260 # miss rate for LoadLockedReq accesses 16469459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135260 # miss rate for LoadLockedReq accesses 16479459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087152 # miss rate for StoreCondReq accesses 16489459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.087152 # miss rate for StoreCondReq accesses 16499459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.142580 # miss rate for demand accesses 16509459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::total 0.142580 # miss rate for demand accesses 16519459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.142580 # miss rate for overall accesses 16529459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::total 0.142580 # miss rate for overall accesses 16539459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15279.459155 # average ReadReq miss latency 16549459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15279.459155 # average ReadReq miss latency 16559459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40782.120412 # average WriteReq miss latency 16569459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_miss_latency::total 40782.120412 # average WriteReq miss latency 16579459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10443.001719 # average LoadLockedReq miss latency 16589459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10443.001719 # average LoadLockedReq miss latency 16599459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7233.333333 # average StoreCondReq miss latency 16609459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7233.333333 # average StoreCondReq miss latency 16619459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency 16629459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_avg_miss_latency::total 28368.852057 # average overall miss latency 16639459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency 16649459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_miss_latency::total 28368.852057 # average overall miss latency 16659459Ssaidi@eecs.umich.edusystem.cpu1.dcache.blocked_cycles::no_mshrs 339060 # number of cycles access was blocked 16669459Ssaidi@eecs.umich.edusystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 16679459Ssaidi@eecs.umich.edusystem.cpu1.dcache.blocked::no_mshrs 3910 # number of cycles access was blocked 16689459Ssaidi@eecs.umich.edusystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 16699459Ssaidi@eecs.umich.edusystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 86.716113 # average number of cycles each access was blocked 16709459Ssaidi@eecs.umich.edusystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 16718464SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 16728464SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 16739459Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::writebacks 70825 # number of writebacks 16749459Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::total 70825 # number of writebacks 16759459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 127864 # number of ReadReq MSHR hits 16769459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_hits::total 127864 # number of ReadReq MSHR hits 16779459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 178553 # number of WriteReq MSHR hits 16789459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_hits::total 178553 # number of WriteReq MSHR hits 16799459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 567 # number of LoadLockedReq MSHR hits 16809459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 567 # number of LoadLockedReq MSHR hits 16819459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_hits::cpu1.data 306417 # number of demand (read+write) MSHR hits 16829459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_hits::total 306417 # number of demand (read+write) MSHR hits 16839459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_hits::cpu1.data 306417 # number of overall MSHR hits 16849459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_hits::total 306417 # number of overall MSHR hits 16859459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 78184 # number of ReadReq MSHR misses 16869459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_misses::total 78184 # number of ReadReq MSHR misses 16879459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 38718 # number of WriteReq MSHR misses 16889459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_misses::total 38718 # number of WriteReq MSHR misses 16899459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4670 # number of LoadLockedReq MSHR misses 16909459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 4670 # number of LoadLockedReq MSHR misses 16919459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3058 # number of StoreCondReq MSHR misses 16929459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_mshr_misses::total 3058 # number of StoreCondReq MSHR misses 16939459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_misses::cpu1.data 116902 # number of demand (read+write) MSHR misses 16949459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_misses::total 116902 # number of demand (read+write) MSHR misses 16959459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_misses::cpu1.data 116902 # number of overall MSHR misses 16969459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_misses::total 116902 # number of overall MSHR misses 16979459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 956868500 # number of ReadReq MSHR miss cycles 16989459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 956868500 # number of ReadReq MSHR miss cycles 16999459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1322831987 # number of WriteReq MSHR miss cycles 17009459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1322831987 # number of WriteReq MSHR miss cycles 17019459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38016500 # number of LoadLockedReq MSHR miss cycles 17029459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38016500 # number of LoadLockedReq MSHR miss cycles 17039459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16018000 # number of StoreCondReq MSHR miss cycles 17049459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16018000 # number of StoreCondReq MSHR miss cycles 17059459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2279700487 # number of demand (read+write) MSHR miss cycles 17069459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_miss_latency::total 2279700487 # number of demand (read+write) MSHR miss cycles 17079459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2279700487 # number of overall MSHR miss cycles 17089459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_miss_latency::total 2279700487 # number of overall MSHR miss cycles 17099459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30982500 # number of ReadReq MSHR uncacheable cycles 17109459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30982500 # number of ReadReq MSHR uncacheable cycles 17119459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 645432500 # number of WriteReq MSHR uncacheable cycles 17129459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 645432500 # number of WriteReq MSHR uncacheable cycles 17139459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676415000 # number of overall MSHR uncacheable cycles 17149459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 676415000 # number of overall MSHR uncacheable cycles 17159459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043171 # mshr miss rate for ReadReq accesses 17169459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043171 # mshr miss rate for ReadReq accesses 17179459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033436 # mshr miss rate for WriteReq accesses 17189459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033436 # mshr miss rate for WriteReq accesses 17199459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120616 # mshr miss rate for LoadLockedReq accesses 17209459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120616 # mshr miss rate for LoadLockedReq accesses 17219459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087095 # mshr miss rate for StoreCondReq accesses 17229459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087095 # mshr miss rate for StoreCondReq accesses 17239459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for demand accesses 17249459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_mshr_miss_rate::total 0.039374 # mshr miss rate for demand accesses 17259459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for overall accesses 17269459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_mshr_miss_rate::total 0.039374 # mshr miss rate for overall accesses 17279459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12238.674153 # average ReadReq mshr miss latency 17289459Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12238.674153 # average ReadReq mshr miss latency 17299459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34165.814014 # average WriteReq mshr miss latency 17309459Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34165.814014 # average WriteReq mshr miss latency 17319459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8140.578158 # average LoadLockedReq mshr miss latency 17329459Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.578158 # average LoadLockedReq mshr miss latency 17339459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5238.064094 # average StoreCondReq mshr miss latency 17349459Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5238.064094 # average StoreCondReq mshr miss latency 17359459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency 17369459Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency 17379459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency 17389459Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency 17398835SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 17409055Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 17418835SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 17429055Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 17438835SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 17449055Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 17458464SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 17468464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 17479459Ssaidi@eecs.umich.edusystem.cpu0.kern.inst.quiesce 6541 # number of quiesce instructions executed 17489459Ssaidi@eecs.umich.edusystem.cpu0.kern.inst.hwrei 182292 # number of hwrei instructions executed 17499459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_count::0 64399 40.43% 40.43% # number of times we switched to this ipl 17509459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_count::21 137 0.09% 40.52% # number of times we switched to this ipl 17519459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_count::22 1928 1.21% 41.73% # number of times we switched to this ipl 17529459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_count::30 188 0.12% 41.85% # number of times we switched to this ipl 17539459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_count::31 92618 58.15% 100.00% # number of times we switched to this ipl 17549459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_count::total 159270 # number of times we switched to this ipl 17559459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_good::0 63397 49.20% 49.20% # number of times we switched to this ipl from a different ipl 17569459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_good::21 137 0.11% 49.30% # number of times we switched to this ipl from a different ipl 17579459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_good::22 1928 1.50% 50.80% # number of times we switched to this ipl from a different ipl 17589459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl 17599459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_good::31 63212 49.05% 100.00% # number of times we switched to this ipl from a different ipl 17609459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_good::total 128862 # number of times we switched to this ipl from a different ipl 17619459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_ticks::0 1866521704000 98.15% 98.15% # number of cycles we spent at this ipl 17629459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_ticks::21 63425000 0.00% 98.15% # number of cycles we spent at this ipl 17639459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_ticks::22 571234500 0.03% 98.18% # number of cycles we spent at this ipl 17649459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_ticks::30 91794500 0.00% 98.19% # number of cycles we spent at this ipl 17659459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_ticks::31 34470644500 1.81% 100.00% # number of cycles we spent at this ipl 17669459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_ticks::total 1901718802500 # number of cycles we spent at this ipl 17679459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_used::0 0.984441 # fraction of swpipl calls that actually changed the ipl 17688464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 17698464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 17708464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 17719459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_used::31 0.682502 # fraction of swpipl calls that actually changed the ipl 17729459Ssaidi@eecs.umich.edusystem.cpu0.kern.ipl_used::total 0.809079 # fraction of swpipl calls that actually changed the ipl 17739459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed 17749459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed 17759459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed 17769459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed 17779459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed 17789459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed 17799459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed 17809459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed 17819459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed 17829459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed 17839459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed 17849459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed 17859459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed 17869459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed 17879459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed 17889459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed 17899459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed 17909459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed 17919459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed 17929459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed 17939459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed 17949459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed 17959459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed 17969459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed 17979459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed 17989459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed 17999459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed 18009459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed 18019459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed 18029459Ssaidi@eecs.umich.edusystem.cpu0.kern.syscall::total 202 # number of syscalls executed 18038464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 18049459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::wripir 291 0.17% 0.17% # number of callpals executed 18059459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed 18069459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed 18079459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed 18089459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::swpctx 3482 2.08% 2.25% # number of callpals executed 18099459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::tbi 48 0.03% 2.28% # number of callpals executed 18109459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed 18119459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::swpipl 152520 91.05% 93.34% # number of callpals executed 18129459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::rdps 6170 3.68% 97.03% # number of callpals executed 18139459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.03% # number of callpals executed 18149459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::wrusp 3 0.00% 97.03% # number of callpals executed 18159459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed 18169459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed 18179459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::rti 4499 2.69% 99.72% # number of callpals executed 18189459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed 18199459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed 18209459Ssaidi@eecs.umich.edusystem.cpu0.kern.callpal::total 167505 # number of callpals executed 18219459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_switch::kernel 7002 # number of protection mode switches 18229459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_switch::user 1256 # number of protection mode switches 18238464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 18249459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_good::kernel 1255 18259459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_good::user 1256 18268464SN/Asystem.cpu0.kern.mode_good::idle 0 18279459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_switch_good::kernel 0.179235 # fraction of useful protection mode switches 18288464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 18298983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 18309459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_switch_good::total 0.304069 # fraction of useful protection mode switches 18319459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_ticks::kernel 1899848666000 99.90% 99.90% # number of ticks spent at the given mode 18329459Ssaidi@eecs.umich.edusystem.cpu0.kern.mode_ticks::user 1870128500 0.10% 100.00% # number of ticks spent at the given mode 18338464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 18349459Ssaidi@eecs.umich.edusystem.cpu0.kern.swap_context 3483 # number of times the context was actually changed 18358464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 18369459Ssaidi@eecs.umich.edusystem.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed 18379459Ssaidi@eecs.umich.edusystem.cpu1.kern.inst.hwrei 57520 # number of hwrei instructions executed 18389459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_count::0 17961 36.86% 36.86% # number of times we switched to this ipl 18399459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_count::22 1928 3.96% 40.82% # number of times we switched to this ipl 18409459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_count::30 291 0.60% 41.41% # number of times we switched to this ipl 18419459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_count::31 28549 58.59% 100.00% # number of times we switched to this ipl 18429459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_count::total 48729 # number of times we switched to this ipl 18439459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_good::0 17586 47.40% 47.40% # number of times we switched to this ipl from a different ipl 18449459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_good::22 1928 5.20% 52.60% # number of times we switched to this ipl from a different ipl 18459459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_good::30 291 0.78% 53.38% # number of times we switched to this ipl from a different ipl 18469459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_good::31 17296 46.62% 100.00% # number of times we switched to this ipl from a different ipl 18479459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_good::total 37101 # number of times we switched to this ipl from a different ipl 18489459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks::0 1876762048000 98.70% 98.70% # number of cycles we spent at this ipl 18499459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks::22 532687000 0.03% 98.73% # number of cycles we spent at this ipl 18509459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks::30 132052500 0.01% 98.74% # number of cycles we spent at this ipl 18519459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks::31 24006771500 1.26% 100.00% # number of cycles we spent at this ipl 18529459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks::total 1901433559000 # number of cycles we spent at this ipl 18539459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_used::0 0.979121 # fraction of swpipl calls that actually changed the ipl 18548464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 18558464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 18569459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_used::31 0.605836 # fraction of swpipl calls that actually changed the ipl 18579459Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_used::total 0.761374 # fraction of swpipl calls that actually changed the ipl 18589459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed 18599459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed 18609459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed 18619459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed 18629459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed 18639459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed 18649459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed 18659459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed 18669459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed 18679459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed 18689459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed 18699459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed 18709459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed 18719459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed 18729459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed 18739459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed 18749459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed 18759459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed 18769459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed 18779459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed 18789459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed 18799459Ssaidi@eecs.umich.edusystem.cpu1.kern.syscall::total 124 # number of syscalls executed 18808464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 18819459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed 18829459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed 18839459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed 18849459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::swpctx 1118 2.21% 2.58% # number of callpals executed 18859459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::tbi 6 0.01% 2.60% # number of callpals executed 18869459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed 18879459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::swpipl 43429 85.72% 88.33% # number of callpals executed 18889459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::rdps 2596 5.12% 93.45% # number of callpals executed 18899459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::wrkgp 1 0.00% 93.45% # number of callpals executed 18909459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::wrusp 4 0.01% 93.46% # number of callpals executed 18919459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::rdusp 1 0.00% 93.46% # number of callpals executed 18929459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::whami 3 0.01% 93.47% # number of callpals executed 18939459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::rti 3081 6.08% 99.55% # number of callpals executed 18949459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed 18959459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed 18968464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 18979459Ssaidi@eecs.umich.edusystem.cpu1.kern.callpal::total 50665 # number of callpals executed 18989459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_switch::kernel 1406 # number of protection mode switches 18999459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_switch::user 488 # number of protection mode switches 19009459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_switch::idle 2430 # number of protection mode switches 19019459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_good::kernel 704 19029459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_good::user 488 19039459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_good::idle 216 19049459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_switch_good::kernel 0.500711 # fraction of useful protection mode switches 19058464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 19069459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_switch_good::idle 0.088889 # fraction of useful protection mode switches 19079459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_switch_good::total 0.325624 # fraction of useful protection mode switches 19089459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_ticks::kernel 4780653500 0.25% 0.25% # number of ticks spent at the given mode 19099459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_ticks::user 828450500 0.04% 0.29% # number of ticks spent at the given mode 19109459Ssaidi@eecs.umich.edusystem.cpu1.kern.mode_ticks::idle 1895813783000 99.71% 100.00% # number of ticks spent at the given mode 19119459Ssaidi@eecs.umich.edusystem.cpu1.kern.swap_context 1119 # number of times the context was actually changed 19125703SN/A 19135703SN/A---------- End Simulation Statistics ---------- 1914