stats.txt revision 11680
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 1.907549 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 1907549438500 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711680SCurtis.Dunham@arm.comhost_inst_rate 120882 # Simulator instruction rate (inst/s) 811680SCurtis.Dunham@arm.comhost_op_rate 120882 # Simulator op (including micro ops) rate (op/s) 911680SCurtis.Dunham@arm.comhost_tick_rate 4068519298 # Simulator tick rate (ticks/s) 1011680SCurtis.Dunham@arm.comhost_mem_usage 339992 # Number of bytes of host memory used 1111680SCurtis.Dunham@arm.comhost_seconds 468.86 # Real time elapsed on the host 1211680SCurtis.Dunham@arm.comsim_insts 56676315 # Number of instructions simulated 1311680SCurtis.Dunham@arm.comsim_ops 56676315 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 1711680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 857728 # Number of bytes read from this memory 1811680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 24440448 # Number of bytes read from this memory 1911680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 121088 # Number of bytes read from this memory 2011680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory 2110576Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2211680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 26308480 # Number of bytes read from this memory 2311680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 857728 # Number of instructions bytes read from this memory 2411680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 121088 # Number of instructions bytes read from this memory 2511680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 978816 # Number of instructions bytes read from this memory 2611680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 7911424 # Number of bytes written to this memory 2711680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 7911424 # Number of bytes written to this memory 2811680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 13402 # Number of read requests responded to by this memory 2911680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 381882 # Number of read requests responded to by this memory 3011680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 1892 # Number of read requests responded to by this memory 3111680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory 3210576Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3311680SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 411070 # Number of read requests responded to by this memory 3411680SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 123616 # Number of write requests responded to by this memory 3511680SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 123616 # Number of write requests responded to by this memory 3611680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 449649 # Total read bandwidth from this memory (bytes/s) 3711680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 12812485 # Total read bandwidth from this memory (bytes/s) 3811680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 63478 # Total read bandwidth from this memory (bytes/s) 3911680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 465653 # Total read bandwidth from this memory (bytes/s) 4011680SCurtis.Dunham@arm.comsystem.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) 4111680SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 13791768 # Total read bandwidth from this memory (bytes/s) 4211680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 449649 # Instruction read bandwidth from this memory (bytes/s) 4311680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 63478 # Instruction read bandwidth from this memory (bytes/s) 4411680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 513127 # Instruction read bandwidth from this memory (bytes/s) 4511680SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 4147428 # Write bandwidth from this memory (bytes/s) 4611680SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 4147428 # Write bandwidth from this memory (bytes/s) 4711680SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 4147428 # Total bandwidth to/from this memory (bytes/s) 4811680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 449649 # Total bandwidth to/from this memory (bytes/s) 4911680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 12812485 # Total bandwidth to/from this memory (bytes/s) 5011680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 63478 # Total bandwidth to/from this memory (bytes/s) 5111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 465653 # Total bandwidth to/from this memory (bytes/s) 5211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) 5311680SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 17939196 # Total bandwidth to/from this memory (bytes/s) 5411680SCurtis.Dunham@arm.comsystem.physmem.readReqs 411070 # Number of read requests accepted 5511680SCurtis.Dunham@arm.comsystem.physmem.writeReqs 123616 # Number of write requests accepted 5611680SCurtis.Dunham@arm.comsystem.physmem.readBursts 411070 # Number of DRAM read bursts, including those serviced by the write queue 5711680SCurtis.Dunham@arm.comsystem.physmem.writeBursts 123616 # Number of DRAM write bursts, including those merged in the write queue 5811680SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 26300288 # Total number of bytes read from DRAM 5911680SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue 6011680SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 7909696 # Total number of bytes written to DRAM 6111680SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 26308480 # Total read bytes from the system interface side 6211680SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 7911424 # Total written bytes from the system interface side 6311680SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue 6410892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 6511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 26240 # Per bank write bursts 6711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 25986 # Per bank write bursts 6811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 25958 # Per bank write bursts 6911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 25690 # Per bank write bursts 7011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 25582 # Per bank write bursts 7111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 25570 # Per bank write bursts 7211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 25628 # Per bank write bursts 7311680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 25343 # Per bank write bursts 7411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 25590 # Per bank write bursts 7511680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 25698 # Per bank write bursts 7611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 25929 # Per bank write bursts 7711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 25525 # Per bank write bursts 7811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 26076 # Per bank write bursts 7911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 25420 # Per bank write bursts 8011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 25099 # Per bank write bursts 8111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 25608 # Per bank write bursts 8211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 8587 # Per bank write bursts 8311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 8090 # Per bank write bursts 8411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 7940 # Per bank write bursts 8511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 7436 # Per bank write bursts 8611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 7275 # Per bank write bursts 8711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 7415 # Per bank write bursts 8811680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 7544 # Per bank write bursts 8911680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 7156 # Per bank write bursts 9011680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 7532 # Per bank write bursts 9111680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 7639 # Per bank write bursts 9211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 7820 # Per bank write bursts 9311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 7739 # Per bank write bursts 9411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 8260 # Per bank write bursts 9511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 7848 # Per bank write bursts 9611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 7518 # Per bank write bursts 9711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 7790 # Per bank write bursts 989978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911680SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 73 # Number of times write queue was full causing retry 10011680SCurtis.Dunham@arm.comsystem.physmem.totGap 1907545081500 # Total gap between requests 1019978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 1069978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711680SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 411070 # Read request sizes (log2) 1089978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1099978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1109978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1119978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1129978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1139978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411680SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 123616 # Write request sizes (log2) 11511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 316681 # What read queue length does an incoming req see 11611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 38865 # What read queue length does an incoming req see 11711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 30168 # What read queue length does an incoming req see 11811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 25023 # What read queue length does an incoming req see 11911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 157 # What read queue length does an incoming req see 12011680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see 12111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see 12211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 12710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 12810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 12910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 13010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 13110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 13210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 13310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 13410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 13510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 13610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13710242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 1506 # What write queue length does an incoming req see 16311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 2688 # What write queue length does an incoming req see 16411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 3344 # What write queue length does an incoming req see 16511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 4408 # What write queue length does an incoming req see 16611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 5702 # What write queue length does an incoming req see 16711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see 16811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 7521 # What write queue length does an incoming req see 16911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 8639 # What write queue length does an incoming req see 17011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 7155 # What write queue length does an incoming req see 17111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 7738 # What write queue length does an incoming req see 17211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 8229 # What write queue length does an incoming req see 17311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 7919 # What write queue length does an incoming req see 17411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 7234 # What write queue length does an incoming req see 17511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 7253 # What write queue length does an incoming req see 17611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 7173 # What write queue length does an incoming req see 17711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 7524 # What write queue length does an incoming req see 17811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 6449 # What write queue length does an incoming req see 17911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 6711 # What write queue length does an incoming req see 18011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 778 # What write queue length does an incoming req see 18111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see 18211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see 18311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 289 # What write queue length does an incoming req see 18411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see 18511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 295 # What write queue length does an incoming req see 18611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see 18711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 277 # What write queue length does an incoming req see 18811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see 18911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 300 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see 19111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see 19211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 376 # What write queue length does an incoming req see 19311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 270 # What write queue length does an incoming req see 19411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see 19511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 284 # What write queue length does an incoming req see 19611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see 19711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 293 # What write queue length does an incoming req see 19811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 245 # What write queue length does an incoming req see 19911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 288 # What write queue length does an incoming req see 20011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see 20111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 241 # What write queue length does an incoming req see 20211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see 20311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 297 # What write queue length does an incoming req see 20411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see 20511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 243 # What write queue length does an incoming req see 20611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see 20711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 442 # What write queue length does an incoming req see 20811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 232 # What write queue length does an incoming req see 20911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 158 # What write queue length does an incoming req see 21011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see 21111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 64388 # Bytes accessed per row activation 21211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 531.308940 # Bytes accessed per row activation 21311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 323.701196 # Bytes accessed per row activation 21411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 416.289256 # Bytes accessed per row activation 21511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 14473 22.48% 22.48% # Bytes accessed per row activation 21611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 11513 17.88% 40.36% # Bytes accessed per row activation 21711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 5038 7.82% 48.18% # Bytes accessed per row activation 21811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 2819 4.38% 52.56% # Bytes accessed per row activation 21911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 2271 3.53% 56.09% # Bytes accessed per row activation 22011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 1853 2.88% 58.97% # Bytes accessed per row activation 22111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 1969 3.06% 62.02% # Bytes accessed per row activation 22211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 1608 2.50% 64.52% # Bytes accessed per row activation 22311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 22844 35.48% 100.00% # Bytes accessed per row activation 22411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 64388 # Bytes accessed per row activation 22511680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 5502 # Reads before turning the bus around for writes 22611680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 74.686478 # Reads before turning the bus around for writes 22711680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 2827.616380 # Reads before turning the bus around for writes 22811680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-8191 5499 99.95% 99.95% # Reads before turning the bus around for writes 22910726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 23010352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 23110352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 23211680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 5502 # Reads before turning the bus around for writes 23311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 5502 # Writes before turning the bus around for reads 23411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 22.462559 # Writes before turning the bus around for reads 23511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.761271 # Writes before turning the bus around for reads 23611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 24.372868 # Writes before turning the bus around for reads 23711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-23 4982 90.55% 90.55% # Writes before turning the bus around for reads 23811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-31 39 0.71% 91.26% # Writes before turning the bus around for reads 23911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-39 171 3.11% 94.37% # Writes before turning the bus around for reads 24011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-47 6 0.11% 94.47% # Writes before turning the bus around for reads 24111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-55 5 0.09% 94.57% # Writes before turning the bus around for reads 24211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-63 13 0.24% 94.80% # Writes before turning the bus around for reads 24311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-71 3 0.05% 94.86% # Writes before turning the bus around for reads 24411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-79 6 0.11% 94.97% # Writes before turning the bus around for reads 24511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-87 29 0.53% 95.49% # Writes before turning the bus around for reads 24611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-95 6 0.11% 95.60% # Writes before turning the bus around for reads 24711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-103 149 2.71% 98.31% # Writes before turning the bus around for reads 24811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-111 8 0.15% 98.46% # Writes before turning the bus around for reads 24911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::112-119 14 0.25% 98.71% # Writes before turning the bus around for reads 25011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads 25111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-135 12 0.22% 98.98% # Writes before turning the bus around for reads 25211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-143 2 0.04% 99.02% # Writes before turning the bus around for reads 25311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-151 1 0.02% 99.04% # Writes before turning the bus around for reads 25411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::152-159 1 0.02% 99.05% # Writes before turning the bus around for reads 25511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::168-175 2 0.04% 99.09% # Writes before turning the bus around for reads 25611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::176-183 11 0.20% 99.29% # Writes before turning the bus around for reads 25711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::184-191 6 0.11% 99.40% # Writes before turning the bus around for reads 25811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::192-199 14 0.25% 99.65% # Writes before turning the bus around for reads 25911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::200-207 3 0.05% 99.71% # Writes before turning the bus around for reads 26011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::208-215 1 0.02% 99.73% # Writes before turning the bus around for reads 26111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::216-223 8 0.15% 99.87% # Writes before turning the bus around for reads 26211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::224-231 5 0.09% 99.96% # Writes before turning the bus around for reads 26311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 26411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 26511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 5502 # Writes before turning the bus around for reads 26611680SCurtis.Dunham@arm.comsystem.physmem.totQLat 8174654750 # Total ticks spent queuing 26711680SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 15879817250 # Total ticks spent from burst creation until serviced by the DRAM 26811680SCurtis.Dunham@arm.comsystem.physmem.totBusLat 2054710000 # Total ticks spent in databus transfers 26911680SCurtis.Dunham@arm.comsystem.physmem.avgQLat 19892.48 # Average queueing delay per DRAM burst 2709978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27111680SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 38642.48 # Average memory access latency per DRAM burst 27211680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 13.79 # Average DRAM read bandwidth in MiByte/s 27311606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s 27411606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s 27511606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s 2769978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27710892Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 27810352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 27910892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28011680SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 2.34 # Average read queue length when enqueuing 28111680SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 26.44 # Average write queue length when enqueuing 28211680SCurtis.Dunham@arm.comsystem.physmem.readRowHits 370634 # Number of row buffer hits during reads 28311680SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 99508 # Number of row buffer hits during writes 28411680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads 28511680SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes 28611680SCurtis.Dunham@arm.comsystem.physmem.avgGap 3567598.71 # Average gap between requests 28711680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined 28811680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 229108320 # Energy for activate commands per rank (pJ) 28911680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 121773960 # Energy for precharge commands per rank (pJ) 29011680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) 29111680SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 320732460 # Energy for write commands per rank (pJ) 29211680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 3850104960.000001 # Energy for refresh commands per rank (pJ) 29311680SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 4304249550 # Energy for active background per rank (pJ) 29411680SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 244489440 # Energy for precharge background per rank (pJ) 29511680SCurtis.Dunham@arm.comsystem.physmem_0.actPowerDownEnergy 8392475940 # Energy for active power-down per rank (pJ) 29611680SCurtis.Dunham@arm.comsystem.physmem_0.prePowerDownEnergy 4645539360 # Energy for precharge power-down per rank (pJ) 29711680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 448697608680 # Energy for self refresh per rank (pJ) 29811680SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 472278008880 # Total energy per rank (pJ) 29911680SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 247.583627 # Core power per rank (mW) 30011680SCurtis.Dunham@arm.comsystem.physmem_0.totalIdleTime 1897458465500 # Total Idle time Per DRAM Rank 30111680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 385946750 # Time in different power states 30211680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 1635552000 # Time in different power states 30311680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 1866968885000 # Time in different power states 30411680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 12097849250 # Time in different power states 30511680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 8056520750 # Time in different power states 30611680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 18404684750 # Time in different power states 30711680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 230629140 # Energy for activate commands per rank (pJ) 30811680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 122578500 # Energy for precharge commands per rank (pJ) 30911680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 1463307300 # Energy for read commands per rank (pJ) 31011680SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 324402120 # Energy for write commands per rank (pJ) 31111680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 3763440720.000001 # Energy for refresh commands per rank (pJ) 31211680SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 4252821870 # Energy for active background per rank (pJ) 31311680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 240122400 # Energy for precharge background per rank (pJ) 31411680SCurtis.Dunham@arm.comsystem.physmem_1.actPowerDownEnergy 8356841250 # Energy for active power-down per rank (pJ) 31511680SCurtis.Dunham@arm.comsystem.physmem_1.prePowerDownEnergy 4387202880 # Energy for precharge power-down per rank (pJ) 31611680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 448891199505 # Energy for self refresh per rank (pJ) 31711680SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 472033988085 # Total energy per rank (pJ) 31811680SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 247.455703 # Core power per rank (mW) 31911680SCurtis.Dunham@arm.comsystem.physmem_1.totalIdleTime 1897589722250 # Total Idle time Per DRAM Rank 32011680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 380622500 # Time in different power states 32111680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 1598754000 # Time in different power states 32211680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 1867843123750 # Time in different power states 32311680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 11424948500 # Time in different power states 32411680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 7975953750 # Time in different power states 32511680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 18326036000 # Time in different power states 32611680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 32711680SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 32811680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.lookups 16746871 # Number of BP lookups 32911680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condPredicted 14324468 # Number of conditional branches predicted 33011680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condIncorrect 462281 # Number of conditional branches incorrect 33111680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBLookups 10727156 # Number of BTB lookups 33211680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHits 4756454 # Number of BTB hits 3339481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33411680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHitPct 44.340308 # BTB Hit Percentage 33511680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.usedRAS 926491 # Number of times the RAS was used to get a target. 33611680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.RASInCorrect 34071 # Number of incorrect RAS predictions. 33711680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectLookups 5119287 # Number of indirect predictor lookups. 33811680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectHits 497756 # Number of indirect target hits. 33911680SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectMisses 4621531 # Number of indirect misses. 34011680SCurtis.Dunham@arm.comsystem.cpu0.branchPredindirectMispredicted 206577 # Number of mispredicted indirect branches. 34110576Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3428464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 3438464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 3448464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 3458464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 34611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 9412979 # DTB read hits 34711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 34328 # DTB read misses 34811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_acv 621 # DTB read access violations 34911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 567042 # DTB read accesses 35011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 5709982 # DTB write hits 35111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 8326 # DTB write misses 35211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_acv 453 # DTB write access violations 35311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 184750 # DTB write accesses 35411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.data_hits 15122961 # DTB hits 35511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.data_misses 42654 # DTB misses 35611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.data_acv 1074 # DTB access violations 35711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.data_accesses 751792 # DTB accesses 35811680SCurtis.Dunham@arm.comsystem.cpu0.itb.fetch_hits 1307701 # ITB hits 35911680SCurtis.Dunham@arm.comsystem.cpu0.itb.fetch_misses 6903 # ITB misses 36011680SCurtis.Dunham@arm.comsystem.cpu0.itb.fetch_acv 605 # ITB acv 36111680SCurtis.Dunham@arm.comsystem.cpu0.itb.fetch_accesses 1314604 # ITB accesses 3628464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 3638464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 3648464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 3658464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 3668464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 3678464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 3688464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 3698464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 3708464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 3718464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 3728464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 3738464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 37411680SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 12949 # Number of power state transitions 37511680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 6475 # Distribution of time spent in the clock gated state 37611680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 285376318.378378 # Distribution of time spent in the clock gated state 37711680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 440714536.369915 # Distribution of time spent in the clock gated state 37811680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 6475 100.00% 100.00% # Distribution of time spent in the clock gated state 37911680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 79500 # Distribution of time spent in the clock gated state 38011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 38111680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 6475 # Distribution of time spent in the clock gated state 38211680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 59737777000 # Cumulative time (in ticks) in various power states 38311680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500 # Cumulative time (in ticks) in various power states 38411680SCurtis.Dunham@arm.comsystem.cpu0.numCycles 119482029 # number of cpu cycles simulated 3858464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3868464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 38711680SCurtis.Dunham@arm.comsystem.cpu0.fetch.icacheStallCycles 25760123 # Number of cycles fetch is stalled on an Icache miss 38811680SCurtis.Dunham@arm.comsystem.cpu0.fetch.Insts 73391497 # Number of instructions fetch has processed 38911680SCurtis.Dunham@arm.comsystem.cpu0.fetch.Branches 16746871 # Number of branches that fetch encountered 39011680SCurtis.Dunham@arm.comsystem.cpu0.fetch.predictedBranches 6180701 # Number of branches that fetch has predicted taken 39111680SCurtis.Dunham@arm.comsystem.cpu0.fetch.Cycles 86881424 # Number of cycles fetch has run and was not squashing or blocked 39211680SCurtis.Dunham@arm.comsystem.cpu0.fetch.SquashCycles 1333696 # Number of cycles fetch has spent squashing 39311680SCurtis.Dunham@arm.comsystem.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb 39411680SCurtis.Dunham@arm.comsystem.cpu0.fetch.MiscStallCycles 31404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39511680SCurtis.Dunham@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 137910 # Number of stall cycles due to pending traps 39611680SCurtis.Dunham@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 424032 # Number of stall cycles due to pending quiesce instructions 39711680SCurtis.Dunham@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 391 # Number of stall cycles due to full MSHR 39811680SCurtis.Dunham@arm.comsystem.cpu0.fetch.CacheLines 8451225 # Number of cache lines fetched 39911680SCurtis.Dunham@arm.comsystem.cpu0.fetch.IcacheSquashes 316387 # Number of outstanding Icache misses that were squashed 40011680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::samples 113902133 # Number of instructions fetched each cycle (Total) 40111680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::mean 0.644338 # Number of instructions fetched each cycle (Total) 40211680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::stdev 1.954525 # Number of instructions fetched each cycle (Total) 4038464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40411680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::0 100270966 88.03% 88.03% # Number of instructions fetched each cycle (Total) 40511680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::1 886228 0.78% 88.81% # Number of instructions fetched each cycle (Total) 40611680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::2 1867927 1.64% 90.45% # Number of instructions fetched each cycle (Total) 40711680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::3 772028 0.68% 91.13% # Number of instructions fetched each cycle (Total) 40811680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::4 2612142 2.29% 93.42% # Number of instructions fetched each cycle (Total) 40911680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::5 579506 0.51% 93.93% # Number of instructions fetched each cycle (Total) 41011680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::6 682297 0.60% 94.53% # Number of instructions fetched each cycle (Total) 41111680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::7 834861 0.73% 95.26% # Number of instructions fetched each cycle (Total) 41211680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::8 5396178 4.74% 100.00% # Number of instructions fetched each cycle (Total) 4138464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4148464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 4158464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 41611680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::total 113902133 # Number of instructions fetched each cycle (Total) 41711680SCurtis.Dunham@arm.comsystem.cpu0.fetch.branchRate 0.140162 # Number of branch fetches per cycle 41811680SCurtis.Dunham@arm.comsystem.cpu0.fetch.rate 0.614247 # Number of inst fetches per cycle 41911680SCurtis.Dunham@arm.comsystem.cpu0.decode.IdleCycles 20705856 # Number of cycles decode is idle 42011680SCurtis.Dunham@arm.comsystem.cpu0.decode.BlockedCycles 82013409 # Number of cycles decode is blocked 42111680SCurtis.Dunham@arm.comsystem.cpu0.decode.RunCycles 8738075 # Number of cycles decode is running 42211680SCurtis.Dunham@arm.comsystem.cpu0.decode.UnblockCycles 1805880 # Number of cycles decode is unblocking 42311680SCurtis.Dunham@arm.comsystem.cpu0.decode.SquashCycles 638912 # Number of cycles decode is squashing 42411680SCurtis.Dunham@arm.comsystem.cpu0.decode.BranchResolved 611998 # Number of times decode resolved a branch 42511680SCurtis.Dunham@arm.comsystem.cpu0.decode.BranchMispred 28528 # Number of times decode detected a branch misprediction 42611680SCurtis.Dunham@arm.comsystem.cpu0.decode.DecodedInsts 63750944 # Number of instructions handled by decode 42711680SCurtis.Dunham@arm.comsystem.cpu0.decode.SquashedInsts 85334 # Number of squashed instructions handled by decode 42811680SCurtis.Dunham@arm.comsystem.cpu0.rename.SquashCycles 638912 # Number of cycles rename is squashing 42911680SCurtis.Dunham@arm.comsystem.cpu0.rename.IdleCycles 21566893 # Number of cycles rename is idle 43011680SCurtis.Dunham@arm.comsystem.cpu0.rename.BlockCycles 55682864 # Number of cycles rename is blocking 43111680SCurtis.Dunham@arm.comsystem.cpu0.rename.serializeStallCycles 17571842 # count of cycles rename stalled for serializing inst 43211680SCurtis.Dunham@arm.comsystem.cpu0.rename.RunCycles 9616135 # Number of cycles rename is running 43311680SCurtis.Dunham@arm.comsystem.cpu0.rename.UnblockCycles 8825485 # Number of cycles rename is unblocking 43411680SCurtis.Dunham@arm.comsystem.cpu0.rename.RenamedInsts 61313705 # Number of instructions processed by rename 43511680SCurtis.Dunham@arm.comsystem.cpu0.rename.ROBFullEvents 198555 # Number of times rename has blocked due to ROB full 43611680SCurtis.Dunham@arm.comsystem.cpu0.rename.IQFullEvents 2000786 # Number of times rename has blocked due to IQ full 43711680SCurtis.Dunham@arm.comsystem.cpu0.rename.LQFullEvents 244905 # Number of times rename has blocked due to LQ full 43811680SCurtis.Dunham@arm.comsystem.cpu0.rename.SQFullEvents 4945993 # Number of times rename has blocked due to SQ full 43911680SCurtis.Dunham@arm.comsystem.cpu0.rename.RenamedOperands 41348673 # Number of destination operands rename has renamed 44011680SCurtis.Dunham@arm.comsystem.cpu0.rename.RenameLookups 74029068 # Number of register rename lookups that rename has made 44111680SCurtis.Dunham@arm.comsystem.cpu0.rename.int_rename_lookups 73897769 # Number of integer rename lookups 44211680SCurtis.Dunham@arm.comsystem.cpu0.rename.fp_rename_lookups 122571 # Number of floating rename lookups 44311680SCurtis.Dunham@arm.comsystem.cpu0.rename.CommittedMaps 33810397 # Number of HB maps that are committed 44411680SCurtis.Dunham@arm.comsystem.cpu0.rename.UndoneMaps 7538276 # Number of HB maps that are undone due to squashing 44511680SCurtis.Dunham@arm.comsystem.cpu0.rename.serializingInsts 1420468 # count of serializing insts renamed 44611680SCurtis.Dunham@arm.comsystem.cpu0.rename.tempSerializingInsts 230583 # count of temporary serializing insts renamed 44711680SCurtis.Dunham@arm.comsystem.cpu0.rename.skidInsts 12282803 # count of insts added to the skid buffer 44811680SCurtis.Dunham@arm.comsystem.cpu0.memDep0.insertedLoads 9801073 # Number of loads inserted to the mem dependence unit. 44911680SCurtis.Dunham@arm.comsystem.cpu0.memDep0.insertedStores 6065767 # Number of stores inserted to the mem dependence unit. 45011680SCurtis.Dunham@arm.comsystem.cpu0.memDep0.conflictingLoads 1438850 # Number of conflicting loads. 45111680SCurtis.Dunham@arm.comsystem.cpu0.memDep0.conflictingStores 936003 # Number of conflicting stores. 45211680SCurtis.Dunham@arm.comsystem.cpu0.iq.iqInstsAdded 54214575 # Number of instructions added to the IQ (excludes non-spec) 45311680SCurtis.Dunham@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1853218 # Number of non-speculative instructions added to the IQ 45411680SCurtis.Dunham@arm.comsystem.cpu0.iq.iqInstsIssued 52616152 # Number of instructions issued 45511680SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 74253 # Number of squashed instructions issued 45611680SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 9353064 # Number of squashed instructions iterated over during squash; mainly for profiling 45711680SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 4027640 # Number of squashed operands that are examined and possibly removed from graph 45811680SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 1289091 # Number of squashed non-spec instructions that were removed 45911680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::samples 113902133 # Number of insts issued each cycle 46011680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.461942 # Number of insts issued each cycle 46111680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.202978 # Number of insts issued each cycle 4628464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 46311680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::0 92500805 81.21% 81.21% # Number of insts issued each cycle 46411680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::1 9147500 8.03% 89.24% # Number of insts issued each cycle 46511680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::2 3821730 3.36% 92.60% # Number of insts issued each cycle 46611680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::3 2743420 2.41% 95.01% # Number of insts issued each cycle 46711680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::4 2859412 2.51% 97.52% # Number of insts issued each cycle 46811680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::5 1408857 1.24% 98.75% # Number of insts issued each cycle 46911680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::6 945269 0.83% 99.58% # Number of insts issued each cycle 47011680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::7 359735 0.32% 99.90% # Number of insts issued each cycle 47111680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::8 115405 0.10% 100.00% # Number of insts issued each cycle 4728464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4738464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4748464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 47511680SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle 4768464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47711680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::IntAlu 168885 16.84% 16.84% # attempts to use FU when none available 47811680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::IntMult 0 0.00% 16.84% # attempts to use FU when none available 47911680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 16.84% # attempts to use FU when none available 48011680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.84% # attempts to use FU when none available 48111680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.84% # attempts to use FU when none available 48211680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.84% # attempts to use FU when none available 48311680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 16.84% # attempts to use FU when none available 48411680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.84% # attempts to use FU when none available 48511680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.84% # attempts to use FU when none available 48611680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.84% # attempts to use FU when none available 48711680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.84% # attempts to use FU when none available 48811680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.84% # attempts to use FU when none available 48911680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.84% # attempts to use FU when none available 49011680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.84% # attempts to use FU when none available 49111680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.84% # attempts to use FU when none available 49211680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 16.84% # attempts to use FU when none available 49311680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.84% # attempts to use FU when none available 49411680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 16.84% # attempts to use FU when none available 49511680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.84% # attempts to use FU when none available 49611680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.84% # attempts to use FU when none available 49711680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.84% # attempts to use FU when none available 49811680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.84% # attempts to use FU when none available 49911680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.84% # attempts to use FU when none available 50011680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.84% # attempts to use FU when none available 50111680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.84% # attempts to use FU when none available 50211680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.84% # attempts to use FU when none available 50311680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.84% # attempts to use FU when none available 50411680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.84% # attempts to use FU when none available 50511680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.84% # attempts to use FU when none available 50611680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::MemRead 512937 51.15% 67.99% # attempts to use FU when none available 50711680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::MemWrite 321005 32.01% 100.00% # attempts to use FU when none available 5088464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5098464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 51011606Sandreas.sandberg@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued 51111680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 36110587 68.63% 68.64% # Type of FU issued 51211680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IntMult 55774 0.11% 68.74% # Type of FU issued 51311680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued 51411680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Type of FU issued 51511680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued 51611680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued 51711680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued 51811680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued 51911680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued 52011680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued 52111680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued 52211680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued 52311680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued 52411680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued 52511680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued 52611680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued 52711680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued 52811680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued 52911680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued 53011680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued 53111680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued 53211680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued 53311680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued 53411680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued 53511680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued 53611680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued 53711680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued 53811680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued 53911680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued 54011680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::MemRead 9844131 18.71% 87.50% # Type of FU issued 54111680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 5797742 11.02% 98.52% # Type of FU issued 54211680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued 5438464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 54411680SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued 54511680SCurtis.Dunham@arm.comsystem.cpu0.iq.rate 0.440369 # Inst issue rate 54611680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_busy_cnt 1002827 # FU busy when requested 54711680SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_busy_rate 0.019059 # FU busy rate (busy events/executed inst) 54811680SCurtis.Dunham@arm.comsystem.cpu0.iq.int_inst_queue_reads 219643662 # Number of integer instruction queue reads 54911680SCurtis.Dunham@arm.comsystem.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes 55011680SCurtis.Dunham@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses 55111680SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_inst_queue_reads 567855 # Number of floating instruction queue reads 55211680SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes 55311680SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses 55411680SCurtis.Dunham@arm.comsystem.cpu0.iq.int_alu_accesses 53309936 # Number of integer alu accesses 55511680SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_alu_accesses 306506 # Number of floating point alu accesses 55611680SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores 5578464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55811680SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed 55911680SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 4258 # Number of memory responses ignored because the instruction is squashed 56011680SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 18275 # Number of memory ordering violations 56111680SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 663361 # Number of stores squashed 5628464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5638464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 56411680SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 18355 # Number of loads that were rescheduled 56511680SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 359900 # Number of times an access to memory failed due to the cache being blocked 5668464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56711680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewSquashCycles 638912 # Number of cycles IEW is squashing 56811680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewBlockCycles 52175649 # Number of cycles IEW is blocking 56911680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewUnblockCycles 1047801 # Number of cycles IEW is unblocking 57011680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispatchedInsts 59607584 # Number of instructions dispatched to IQ 57111680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispSquashedInsts 159494 # Number of squashed instructions skipped by dispatch 57211680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispLoadInsts 9801073 # Number of dispatched load instructions 57311680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispStoreInsts 6065767 # Number of dispatched store instructions 57411680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 1641866 # Number of dispatched non-speculative instructions 57511680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewIQFullEvents 39898 # Number of times the IQ has become full, causing a stall 57611680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewLSQFullEvents 807337 # Number of times the LSQ has become full, causing a stall 57711680SCurtis.Dunham@arm.comsystem.cpu0.iew.memOrderViolationEvents 18275 # Number of memory order violations 57811680SCurtis.Dunham@arm.comsystem.cpu0.iew.predictedTakenIncorrect 179860 # Number of branches that were predicted taken incorrectly 57911680SCurtis.Dunham@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 504304 # Number of branches that were predicted not taken incorrectly 58011680SCurtis.Dunham@arm.comsystem.cpu0.iew.branchMispredicts 684164 # Number of branch mispredicts detected at execute 58111680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewExecutedInsts 51934418 # Number of executed instructions 58211680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewExecLoadInsts 9472740 # Number of load instructions executed 58311680SCurtis.Dunham@arm.comsystem.cpu0.iew.iewExecSquashedInsts 681734 # Number of squashed instructions skipped in execute 5848464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 58511680SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_nop 3539791 # number of nop insts executed 58611680SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_refs 15207952 # number of memory reference insts executed 58711680SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_branches 8258466 # Number of branches executed 58811680SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_stores 5735212 # Number of stores executed 58911680SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_rate 0.434663 # Inst execution rate 59011680SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_sent 51337506 # cumulative count of insts sent to commit 59111680SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_count 51155506 # cumulative count of insts written-back 59211680SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_producers 26224773 # num instructions producing a value 59311680SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_consumers 36250862 # num instructions consuming a value 59411680SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_rate 0.428144 # insts written-back per cycle 59511680SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_fanout 0.723425 # average fanout of values written-back 59611680SCurtis.Dunham@arm.comsystem.cpu0.commit.commitSquashedInsts 9849450 # The number of squashed insts skipped by commit 59711680SCurtis.Dunham@arm.comsystem.cpu0.commit.commitNonSpecStalls 564127 # The number of times commit has been forced to stall to communicate backwards 59811680SCurtis.Dunham@arm.comsystem.cpu0.commit.branchMispredicts 611071 # The number of times a branch was mispredicted 59911680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::samples 112190301 # Number of insts commited each cycle 60011680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.442089 # Number of insts commited each cycle 60111680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.364280 # Number of insts commited each cycle 6028241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 60311680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::0 94635636 84.35% 84.35% # Number of insts commited each cycle 60411680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::1 6985533 6.23% 90.58% # Number of insts commited each cycle 60511680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::2 3776917 3.37% 93.95% # Number of insts commited each cycle 60611680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::3 2005568 1.79% 95.73% # Number of insts commited each cycle 60711680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::4 1565673 1.40% 97.13% # Number of insts commited each cycle 60811680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::5 565948 0.50% 97.63% # Number of insts commited each cycle 60911680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::6 418764 0.37% 98.01% # Number of insts commited each cycle 61011680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::7 453132 0.40% 98.41% # Number of insts commited each cycle 61111680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::8 1783130 1.59% 100.00% # Number of insts commited each cycle 6128241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6138241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6148241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61511680SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::total 112190301 # Number of insts commited each cycle 61611680SCurtis.Dunham@arm.comsystem.cpu0.commit.committedInsts 49598051 # Number of instructions committed 61711680SCurtis.Dunham@arm.comsystem.cpu0.commit.committedOps 49598051 # Number of ops (including micro ops) committed 6188241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 61911680SCurtis.Dunham@arm.comsystem.cpu0.commit.refs 13266916 # Number of memory references committed 62011680SCurtis.Dunham@arm.comsystem.cpu0.commit.loads 7864510 # Number of loads committed 62111680SCurtis.Dunham@arm.comsystem.cpu0.commit.membars 192309 # Number of memory barriers committed 62211680SCurtis.Dunham@arm.comsystem.cpu0.commit.branches 7509354 # Number of branches committed 62311680SCurtis.Dunham@arm.comsystem.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. 62411680SCurtis.Dunham@arm.comsystem.cpu0.commit.int_insts 45907115 # Number of committed integer instructions. 62511680SCurtis.Dunham@arm.comsystem.cpu0.commit.function_calls 632192 # Number of function calls committed. 62611680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 2885858 5.82% 5.82% # Class of committed instruction 62711680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntAlu 32387672 65.30% 71.12% # Class of committed instruction 62811680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntMult 54445 0.11% 71.23% # Class of committed instruction 62911680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction 63011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction 63111680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction 63211680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction 63311680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction 63411680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction 63511680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction 63611680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction 63711680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction 63811680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction 63911680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction 64011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction 64111680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction 64211680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction 64311680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction 64411680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction 64511680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction 64611680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction 64711680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction 64811680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction 64911680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction 65011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction 65111680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction 65211680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction 65311680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction 65411680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction 65511680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction 65611680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::MemRead 8056819 16.24% 87.53% # Class of committed instruction 65711680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::MemWrite 5408346 10.90% 98.43% # Class of committed instruction 65811680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction 65910220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 66011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction 66111680SCurtis.Dunham@arm.comsystem.cpu0.commit.bw_lim_events 1783130 # number cycles where commit BW limit reached 66211680SCurtis.Dunham@arm.comsystem.cpu0.rob.rob_reads 169680194 # The number of ROB reads 66311680SCurtis.Dunham@arm.comsystem.cpu0.rob.rob_writes 120607262 # The number of ROB writes 66411680SCurtis.Dunham@arm.comsystem.cpu0.timesIdled 481372 # Number of times that the entire CPU went into an idle state and unscheduled itself 66511680SCurtis.Dunham@arm.comsystem.cpu0.idleCycles 5579896 # Total number of cycles that the CPU has spent unscheduled due to idling 66611680SCurtis.Dunham@arm.comsystem.cpu0.quiesceCycles 3694980588 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 66711680SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 46714728 # Number of Instructions Simulated 66811680SCurtis.Dunham@arm.comsystem.cpu0.committedOps 46714728 # Number of Ops (including micro ops) Simulated 66911680SCurtis.Dunham@arm.comsystem.cpu0.cpi 2.557695 # CPI: Cycles Per Instruction 67011680SCurtis.Dunham@arm.comsystem.cpu0.cpi_total 2.557695 # CPI: Total CPI of All Threads 67111680SCurtis.Dunham@arm.comsystem.cpu0.ipc 0.390977 # IPC: Instructions Per Cycle 67211680SCurtis.Dunham@arm.comsystem.cpu0.ipc_total 0.390977 # IPC: Total IPC of All Threads 67311680SCurtis.Dunham@arm.comsystem.cpu0.int_regfile_reads 68002622 # number of integer regfile reads 67411680SCurtis.Dunham@arm.comsystem.cpu0.int_regfile_writes 37262146 # number of integer regfile writes 67511680SCurtis.Dunham@arm.comsystem.cpu0.fp_regfile_reads 121389 # number of floating regfile reads 67611680SCurtis.Dunham@arm.comsystem.cpu0.fp_regfile_writes 130195 # number of floating regfile writes 67711680SCurtis.Dunham@arm.comsystem.cpu0.misc_regfile_reads 1657828 # number of misc regfile reads 67811680SCurtis.Dunham@arm.comsystem.cpu0.misc_regfile_writes 782201 # number of misc regfile writes 67911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 68011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 1253317 # number of replacements 68111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.016530 # Cycle average of tags in use 68211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 10648438 # Total number of references to valid blocks. 68311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 1253753 # Sample count of references to valid blocks. 68411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 8.493250 # Average number of references to valid blocks. 68511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. 68611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.016530 # Average occupied blocks per requestor 68711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988314 # Average percentage of cache occupancy 68811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988314 # Average percentage of cache occupancy 68911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 436 # Occupied blocks per task id 69011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 414 # Occupied blocks per task id 69111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id 69211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.851562 # Percentage of cache occupancy per task id 69311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 56881554 # Number of tag accesses 69411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 56881554 # Number of data accesses 69511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 69611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6768789 # number of ReadReq hits 69711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6768789 # number of ReadReq hits 69811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 3521179 # number of WriteReq hits 69911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 3521179 # number of WriteReq hits 70011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174329 # number of LoadLockedReq hits 70111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 174329 # number of LoadLockedReq hits 70211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 179913 # number of StoreCondReq hits 70311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 179913 # number of StoreCondReq hits 70411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10289968 # number of demand (read+write) hits 70511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 10289968 # number of demand (read+write) hits 70611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10289968 # number of overall hits 70711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 10289968 # number of overall hits 70811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1553170 # number of ReadReq misses 70911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1553170 # number of ReadReq misses 71011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1684058 # number of WriteReq misses 71111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1684058 # number of WriteReq misses 71211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20354 # number of LoadLockedReq misses 71311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 20354 # number of LoadLockedReq misses 71411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 3039 # number of StoreCondReq misses 71511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 3039 # number of StoreCondReq misses 71611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 3237228 # number of demand (read+write) misses 71711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 3237228 # number of demand (read+write) misses 71811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 3237228 # number of overall misses 71911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 3237228 # number of overall misses 72011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41477053500 # number of ReadReq miss cycles 72111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 41477053500 # number of ReadReq miss cycles 72211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85173031211 # number of WriteReq miss cycles 72311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 85173031211 # number of WriteReq miss cycles 72411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394024000 # number of LoadLockedReq miss cycles 72511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 394024000 # number of LoadLockedReq miss cycles 72611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17098500 # number of StoreCondReq miss cycles 72711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 17098500 # number of StoreCondReq miss cycles 72811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711 # number of demand (read+write) miss cycles 72911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 126650084711 # number of demand (read+write) miss cycles 73011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711 # number of overall miss cycles 73111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 126650084711 # number of overall miss cycles 73211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8321959 # number of ReadReq accesses(hits+misses) 73311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8321959 # number of ReadReq accesses(hits+misses) 73411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5205237 # number of WriteReq accesses(hits+misses) 73511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5205237 # number of WriteReq accesses(hits+misses) 73611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194683 # number of LoadLockedReq accesses(hits+misses) 73711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 194683 # number of LoadLockedReq accesses(hits+misses) 73811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182952 # number of StoreCondReq accesses(hits+misses) 73911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 182952 # number of StoreCondReq accesses(hits+misses) 74011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 13527196 # number of demand (read+write) accesses 74111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 13527196 # number of demand (read+write) accesses 74211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 13527196 # number of overall (read+write) accesses 74311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 13527196 # number of overall (read+write) accesses 74411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186635 # miss rate for ReadReq accesses 74511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.186635 # miss rate for ReadReq accesses 74611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323531 # miss rate for WriteReq accesses 74711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.323531 # miss rate for WriteReq accesses 74811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104549 # miss rate for LoadLockedReq accesses 74911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104549 # miss rate for LoadLockedReq accesses 75011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016611 # miss rate for StoreCondReq accesses 75111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.016611 # miss rate for StoreCondReq accesses 75211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.239313 # miss rate for demand accesses 75311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.239313 # miss rate for demand accesses 75411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.239313 # miss rate for overall accesses 75511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.239313 # miss rate for overall accesses 75611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785 # average ReadReq miss latency 75711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785 # average ReadReq miss latency 75811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577 # average WriteReq miss latency 75911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577 # average WriteReq miss latency 76011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601 # average LoadLockedReq miss latency 76111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601 # average LoadLockedReq miss latency 76211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.357354 # average StoreCondReq miss latency 76311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.357354 # average StoreCondReq miss latency 76411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency 76511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 39123.004222 # average overall miss latency 76611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency 76711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 39123.004222 # average overall miss latency 76811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 4484825 # number of cycles access was blocked 76911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 6096 # number of cycles access was blocked 77011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_mshrs 108156 # number of cycles access was blocked 77111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_targets 130 # number of cycles access was blocked 77211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.466262 # average number of cycles each access was blocked 77311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 46.892308 # average number of cycles each access was blocked 77411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 737739 # number of writebacks 77511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 737739 # number of writebacks 77611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 551343 # number of ReadReq MSHR hits 77711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 551343 # number of ReadReq MSHR hits 77811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432280 # number of WriteReq MSHR hits 77911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1432280 # number of WriteReq MSHR hits 78011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5686 # number of LoadLockedReq MSHR hits 78111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 5686 # number of LoadLockedReq MSHR hits 78211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1983623 # number of demand (read+write) MSHR hits 78311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1983623 # number of demand (read+write) MSHR hits 78411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1983623 # number of overall MSHR hits 78511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1983623 # number of overall MSHR hits 78611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001827 # number of ReadReq MSHR misses 78711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 1001827 # number of ReadReq MSHR misses 78811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251778 # number of WriteReq MSHR misses 78911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 251778 # number of WriteReq MSHR misses 79011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14668 # number of LoadLockedReq MSHR misses 79111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 14668 # number of LoadLockedReq MSHR misses 79211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3039 # number of StoreCondReq MSHR misses 79311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 3039 # number of StoreCondReq MSHR misses 79411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1253605 # number of demand (read+write) MSHR misses 79511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1253605 # number of demand (read+write) MSHR misses 79611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1253605 # number of overall MSHR misses 79711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1253605 # number of overall MSHR misses 79811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable 79911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable 80011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable 80111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 9906 # number of WriteReq MSHR uncacheable 80211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses 80311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 16883 # number of overall MSHR uncacheable misses 80411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31605979000 # number of ReadReq MSHR miss cycles 80511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 31605979000 # number of ReadReq MSHR miss cycles 80611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13230681248 # number of WriteReq MSHR miss cycles 80711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 13230681248 # number of WriteReq MSHR miss cycles 80811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170838000 # number of LoadLockedReq MSHR miss cycles 80911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170838000 # number of LoadLockedReq MSHR miss cycles 81011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14059500 # number of StoreCondReq MSHR miss cycles 81111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14059500 # number of StoreCondReq MSHR miss cycles 81211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44836660248 # number of demand (read+write) MSHR miss cycles 81311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 44836660248 # number of demand (read+write) MSHR miss cycles 81411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44836660248 # number of overall MSHR miss cycles 81511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 44836660248 # number of overall MSHR miss cycles 81611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1556905500 # number of ReadReq MSHR uncacheable cycles 81711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1556905500 # number of ReadReq MSHR uncacheable cycles 81811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1556905500 # number of overall MSHR uncacheable cycles 81911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 1556905500 # number of overall MSHR uncacheable cycles 82011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120384 # mshr miss rate for ReadReq accesses 82111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120384 # mshr miss rate for ReadReq accesses 82211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048370 # mshr miss rate for WriteReq accesses 82311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048370 # mshr miss rate for WriteReq accesses 82411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075343 # mshr miss rate for LoadLockedReq accesses 82511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075343 # mshr miss rate for LoadLockedReq accesses 82611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016611 # mshr miss rate for StoreCondReq accesses 82711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016611 # mshr miss rate for StoreCondReq accesses 82811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for demand accesses 82911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.092673 # mshr miss rate for demand accesses 83011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for overall accesses 83111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.092673 # mshr miss rate for overall accesses 83211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31548.340182 # average ReadReq mshr miss latency 83311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31548.340182 # average ReadReq mshr miss latency 83411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52548.996529 # average WriteReq mshr miss latency 83511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52548.996529 # average WriteReq mshr miss latency 83611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11646.986638 # average LoadLockedReq mshr miss latency 83711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638 # average LoadLockedReq mshr miss latency 83811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.357354 # average StoreCondReq mshr miss latency 83911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.357354 # average StoreCondReq mshr miss latency 84011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency 84111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency 84211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency 84311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency 84411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897 # average ReadReq mshr uncacheable latency 84511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897 # average ReadReq mshr uncacheable latency 84611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92217.348812 # average overall mshr uncacheable latency 84711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92217.348812 # average overall mshr uncacheable latency 84811680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 84911680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 894430 # number of replacements 85011680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 509.352767 # Cycle average of tags in use 85111680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 7502081 # Total number of references to valid blocks. 85211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 894941 # Sample count of references to valid blocks. 85311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 8.382766 # Average number of references to valid blocks. 85411680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 30333693500 # Cycle when the warmup percentage was hit. 85511680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352767 # Average occupied blocks per requestor 85611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.994830 # Average percentage of cache occupancy 85711680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.994830 # Average percentage of cache occupancy 85811606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 85911680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id 86011680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 86111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 86211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 9346457 # Number of tag accesses 86311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 9346457 # Number of data accesses 86411680SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 86511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 7502081 # number of ReadReq hits 86611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 7502081 # number of ReadReq hits 86711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 7502081 # number of demand (read+write) hits 86811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 7502081 # number of demand (read+write) hits 86911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 7502081 # number of overall hits 87011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 7502081 # number of overall hits 87111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 949140 # number of ReadReq misses 87211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 949140 # number of ReadReq misses 87311680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 949140 # number of demand (read+write) misses 87411680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 949140 # number of demand (read+write) misses 87511680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 949140 # number of overall misses 87611680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 949140 # number of overall misses 87711680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13882658989 # number of ReadReq miss cycles 87811680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 13882658989 # number of ReadReq miss cycles 87911680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 13882658989 # number of demand (read+write) miss cycles 88011680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 13882658989 # number of demand (read+write) miss cycles 88111680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 13882658989 # number of overall miss cycles 88211680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 13882658989 # number of overall miss cycles 88311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 8451221 # number of ReadReq accesses(hits+misses) 88411680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 8451221 # number of ReadReq accesses(hits+misses) 88511680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 8451221 # number of demand (read+write) accesses 88611680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 8451221 # number of demand (read+write) accesses 88711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 8451221 # number of overall (read+write) accesses 88811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 8451221 # number of overall (read+write) accesses 88911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112308 # miss rate for ReadReq accesses 89011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.112308 # miss rate for ReadReq accesses 89111680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.112308 # miss rate for demand accesses 89211680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.112308 # miss rate for demand accesses 89311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.112308 # miss rate for overall accesses 89411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.112308 # miss rate for overall accesses 89511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14626.566143 # average ReadReq miss latency 89611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 14626.566143 # average ReadReq miss latency 89711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency 89811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 14626.566143 # average overall miss latency 89911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency 90011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 14626.566143 # average overall miss latency 90111680SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 6715 # number of cycles access was blocked 90210576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 90311680SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_mshrs 267 # number of cycles access was blocked 90410576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 90511680SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 25.149813 # average number of cycles each access was blocked 90610576Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90711680SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 894430 # number of writebacks 90811680SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 894430 # number of writebacks 90911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53904 # number of ReadReq MSHR hits 91011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 53904 # number of ReadReq MSHR hits 91111680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 53904 # number of demand (read+write) MSHR hits 91211680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_hits::total 53904 # number of demand (read+write) MSHR hits 91311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 53904 # number of overall MSHR hits 91411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_hits::total 53904 # number of overall MSHR hits 91511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895236 # number of ReadReq MSHR misses 91611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 895236 # number of ReadReq MSHR misses 91711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 895236 # number of demand (read+write) MSHR misses 91811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 895236 # number of demand (read+write) MSHR misses 91911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 895236 # number of overall MSHR misses 92011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 895236 # number of overall MSHR misses 92111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12277660991 # number of ReadReq MSHR miss cycles 92211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 12277660991 # number of ReadReq MSHR miss cycles 92311680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12277660991 # number of demand (read+write) MSHR miss cycles 92411680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 12277660991 # number of demand (read+write) MSHR miss cycles 92511680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12277660991 # number of overall MSHR miss cycles 92611680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 12277660991 # number of overall MSHR miss cycles 92711680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for ReadReq accesses 92811680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105930 # mshr miss rate for ReadReq accesses 92911680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for demand accesses 93011680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.105930 # mshr miss rate for demand accesses 93111680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for overall accesses 93211680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.105930 # mshr miss rate for overall accesses 93311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average ReadReq mshr miss latency 93411680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651 # average ReadReq mshr miss latency 93511680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency 93611680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency 93711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency 93811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency 93911680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.lookups 4438770 # Number of BP lookups 94011680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condPredicted 3818546 # Number of conditional branches predicted 94111680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condIncorrect 113828 # Number of conditional branches incorrect 94211680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBLookups 2325021 # Number of BTB lookups 94311680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHits 880835 # Number of BTB hits 9449481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 94511680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHitPct 37.885034 # BTB Hit Percentage 94611680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.usedRAS 228893 # Number of times the RAS was used to get a target. 94711680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.RASInCorrect 8586 # Number of incorrect RAS predictions. 94811680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectLookups 1265295 # Number of indirect predictor lookups. 94911680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectHits 163281 # Number of indirect target hits. 95011680SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectMisses 1102014 # Number of indirect misses. 95111680SCurtis.Dunham@arm.comsystem.cpu1.branchPredindirectMispredicted 40695 # Number of mispredicted indirect branches. 9528464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 9538464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 9548464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 9558464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 95611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 2431495 # DTB read hits 95711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 15697 # DTB read misses 95811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_acv 126 # DTB read access violations 95911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 432376 # DTB read accesses 96011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 1439190 # DTB write hits 96111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 3913 # DTB write misses 96211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_acv 68 # DTB write access violations 96311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 163232 # DTB write accesses 96411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.data_hits 3870685 # DTB hits 96511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.data_misses 19610 # DTB misses 96611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.data_acv 194 # DTB access violations 96711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.data_accesses 595608 # DTB accesses 96811680SCurtis.Dunham@arm.comsystem.cpu1.itb.fetch_hits 677547 # ITB hits 96911680SCurtis.Dunham@arm.comsystem.cpu1.itb.fetch_misses 3477 # ITB misses 97011680SCurtis.Dunham@arm.comsystem.cpu1.itb.fetch_acv 144 # ITB acv 97111680SCurtis.Dunham@arm.comsystem.cpu1.itb.fetch_accesses 681024 # ITB accesses 9728464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 9738464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 9748464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 9758464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 9768464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 9778464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 9788464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 9798464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 9808464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 9818464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 9828464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 9838464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 98411680SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 5082 # Number of power state transitions 98511680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2541 # Distribution of time spent in the clock gated state 98611680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 747256549.980323 # Distribution of time spent in the clock gated state 98711680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 396382548.008070 # Distribution of time spent in the clock gated state 98811680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 2541 100.00% 100.00% # Distribution of time spent in the clock gated state 98911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state 99011680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state 99111680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 2541 # Distribution of time spent in the clock gated state 99211680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 8770545000 # Cumulative time (in ticks) in various power states 99311680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500 # Cumulative time (in ticks) in various power states 99411680SCurtis.Dunham@arm.comsystem.cpu1.numCycles 17543632 # number of cpu cycles simulated 9958464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 9968464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 99711680SCurtis.Dunham@arm.comsystem.cpu1.fetch.icacheStallCycles 7091057 # Number of cycles fetch is stalled on an Icache miss 99811680SCurtis.Dunham@arm.comsystem.cpu1.fetch.Insts 17620667 # Number of instructions fetch has processed 99911680SCurtis.Dunham@arm.comsystem.cpu1.fetch.Branches 4438770 # Number of branches that fetch encountered 100011680SCurtis.Dunham@arm.comsystem.cpu1.fetch.predictedBranches 1273009 # Number of branches that fetch has predicted taken 100111680SCurtis.Dunham@arm.comsystem.cpu1.fetch.Cycles 9220507 # Number of cycles fetch has run and was not squashing or blocked 100211680SCurtis.Dunham@arm.comsystem.cpu1.fetch.SquashCycles 378986 # Number of cycles fetch has spent squashing 100311680SCurtis.Dunham@arm.comsystem.cpu1.fetch.MiscStallCycles 26066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 100411680SCurtis.Dunham@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 68380 # Number of stall cycles due to pending traps 100511680SCurtis.Dunham@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 52547 # Number of stall cycles due to pending quiesce instructions 100611680SCurtis.Dunham@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR 100711680SCurtis.Dunham@arm.comsystem.cpu1.fetch.CacheLines 1980567 # Number of cache lines fetched 100811680SCurtis.Dunham@arm.comsystem.cpu1.fetch.IcacheSquashes 84330 # Number of outstanding Icache misses that were squashed 100911680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::samples 16648116 # Number of instructions fetched each cycle (Total) 101011680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::mean 1.058418 # Number of instructions fetched each cycle (Total) 101111680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::stdev 2.465473 # Number of instructions fetched each cycle (Total) 10128464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 101311680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::0 13552832 81.41% 81.41% # Number of instructions fetched each cycle (Total) 101411680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::1 195919 1.18% 82.58% # Number of instructions fetched each cycle (Total) 101511680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::2 328483 1.97% 84.56% # Number of instructions fetched each cycle (Total) 101611680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::3 235159 1.41% 85.97% # Number of instructions fetched each cycle (Total) 101711680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::4 403136 2.42% 88.39% # Number of instructions fetched each cycle (Total) 101811680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::5 149696 0.90% 89.29% # Number of instructions fetched each cycle (Total) 101911680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::6 175199 1.05% 90.34% # Number of instructions fetched each cycle (Total) 102011680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::7 211449 1.27% 91.61% # Number of instructions fetched each cycle (Total) 102111680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::8 1396243 8.39% 100.00% # Number of instructions fetched each cycle (Total) 10228464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 10238464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 10248464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 102511680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::total 16648116 # Number of instructions fetched each cycle (Total) 102611680SCurtis.Dunham@arm.comsystem.cpu1.fetch.branchRate 0.253013 # Number of branch fetches per cycle 102711680SCurtis.Dunham@arm.comsystem.cpu1.fetch.rate 1.004391 # Number of inst fetches per cycle 102811680SCurtis.Dunham@arm.comsystem.cpu1.decode.IdleCycles 5799032 # Number of cycles decode is idle 102911680SCurtis.Dunham@arm.comsystem.cpu1.decode.BlockedCycles 8189176 # Number of cycles decode is blocked 103011680SCurtis.Dunham@arm.comsystem.cpu1.decode.RunCycles 2194913 # Number of cycles decode is running 103111680SCurtis.Dunham@arm.comsystem.cpu1.decode.UnblockCycles 283013 # Number of cycles decode is unblocking 103211680SCurtis.Dunham@arm.comsystem.cpu1.decode.SquashCycles 181981 # Number of cycles decode is squashing 103311680SCurtis.Dunham@arm.comsystem.cpu1.decode.BranchResolved 153262 # Number of times decode resolved a branch 103411680SCurtis.Dunham@arm.comsystem.cpu1.decode.BranchMispred 7666 # Number of times decode detected a branch misprediction 103511680SCurtis.Dunham@arm.comsystem.cpu1.decode.DecodedInsts 14395116 # Number of instructions handled by decode 103611680SCurtis.Dunham@arm.comsystem.cpu1.decode.SquashedInsts 24052 # Number of squashed instructions handled by decode 103711680SCurtis.Dunham@arm.comsystem.cpu1.rename.SquashCycles 181981 # Number of cycles rename is squashing 103811680SCurtis.Dunham@arm.comsystem.cpu1.rename.IdleCycles 5988192 # Number of cycles rename is idle 103911680SCurtis.Dunham@arm.comsystem.cpu1.rename.BlockCycles 920488 # Number of cycles rename is blocking 104011680SCurtis.Dunham@arm.comsystem.cpu1.rename.serializeStallCycles 6008083 # count of cycles rename stalled for serializing inst 104111680SCurtis.Dunham@arm.comsystem.cpu1.rename.RunCycles 2289928 # Number of cycles rename is running 104211680SCurtis.Dunham@arm.comsystem.cpu1.rename.UnblockCycles 1259442 # Number of cycles rename is unblocking 104311680SCurtis.Dunham@arm.comsystem.cpu1.rename.RenamedInsts 13629732 # Number of instructions processed by rename 104411680SCurtis.Dunham@arm.comsystem.cpu1.rename.ROBFullEvents 4042 # Number of times rename has blocked due to ROB full 104511680SCurtis.Dunham@arm.comsystem.cpu1.rename.IQFullEvents 109065 # Number of times rename has blocked due to IQ full 104611680SCurtis.Dunham@arm.comsystem.cpu1.rename.LQFullEvents 36629 # Number of times rename has blocked due to LQ full 104711680SCurtis.Dunham@arm.comsystem.cpu1.rename.SQFullEvents 635484 # Number of times rename has blocked due to SQ full 104811680SCurtis.Dunham@arm.comsystem.cpu1.rename.RenamedOperands 9050413 # Number of destination operands rename has renamed 104911680SCurtis.Dunham@arm.comsystem.cpu1.rename.RenameLookups 16252880 # Number of register rename lookups that rename has made 105011680SCurtis.Dunham@arm.comsystem.cpu1.rename.int_rename_lookups 16186853 # Number of integer rename lookups 105111680SCurtis.Dunham@arm.comsystem.cpu1.rename.fp_rename_lookups 59441 # Number of floating rename lookups 105211680SCurtis.Dunham@arm.comsystem.cpu1.rename.CommittedMaps 7085651 # Number of HB maps that are committed 105311680SCurtis.Dunham@arm.comsystem.cpu1.rename.UndoneMaps 1964754 # Number of HB maps that are undone due to squashing 105411680SCurtis.Dunham@arm.comsystem.cpu1.rename.serializingInsts 511413 # count of serializing insts renamed 105511680SCurtis.Dunham@arm.comsystem.cpu1.rename.tempSerializingInsts 53676 # count of temporary serializing insts renamed 105611680SCurtis.Dunham@arm.comsystem.cpu1.rename.skidInsts 2285701 # count of insts added to the skid buffer 105711680SCurtis.Dunham@arm.comsystem.cpu1.memDep0.insertedLoads 2541438 # Number of loads inserted to the mem dependence unit. 105811680SCurtis.Dunham@arm.comsystem.cpu1.memDep0.insertedStores 1543271 # Number of stores inserted to the mem dependence unit. 105911680SCurtis.Dunham@arm.comsystem.cpu1.memDep0.conflictingLoads 322798 # Number of conflicting loads. 106011680SCurtis.Dunham@arm.comsystem.cpu1.memDep0.conflictingStores 171550 # Number of conflicting stores. 106111680SCurtis.Dunham@arm.comsystem.cpu1.iq.iqInstsAdded 11950332 # Number of instructions added to the IQ (excludes non-spec) 106211680SCurtis.Dunham@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 586300 # Number of non-speculative instructions added to the IQ 106311680SCurtis.Dunham@arm.comsystem.cpu1.iq.iqInstsIssued 11472464 # Number of instructions issued 106411680SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 27528 # Number of squashed instructions issued 106511680SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 2575040 # Number of squashed instructions iterated over during squash; mainly for profiling 106611680SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 1218372 # Number of squashed operands that are examined and possibly removed from graph 106711680SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 432674 # Number of squashed non-spec instructions that were removed 106811680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::samples 16648116 # Number of insts issued each cycle 106911680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.689115 # Number of insts issued each cycle 107011680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.415855 # Number of insts issued each cycle 10718464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 107211680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::0 11949949 71.78% 71.78% # Number of insts issued each cycle 107311680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::1 2021085 12.14% 83.92% # Number of insts issued each cycle 107411680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::2 863131 5.18% 89.10% # Number of insts issued each cycle 107511680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::3 621327 3.73% 92.84% # Number of insts issued each cycle 107611680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::4 572760 3.44% 96.28% # Number of insts issued each cycle 107711680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::5 302852 1.82% 98.10% # Number of insts issued each cycle 107811680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::6 196760 1.18% 99.28% # Number of insts issued each cycle 107911680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::7 86740 0.52% 99.80% # Number of insts issued each cycle 108011680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::8 33512 0.20% 100.00% # Number of insts issued each cycle 10818464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 10828464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 10838464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 108411680SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle 10858464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 108611680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::IntAlu 33628 10.30% 10.30% # attempts to use FU when none available 108711680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 10.30% # attempts to use FU when none available 108811680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 10.30% # attempts to use FU when none available 108911680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.30% # attempts to use FU when none available 109011680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.30% # attempts to use FU when none available 109111680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.30% # attempts to use FU when none available 109211680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 10.30% # attempts to use FU when none available 109311680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.30% # attempts to use FU when none available 109411680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.30% # attempts to use FU when none available 109511680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.30% # attempts to use FU when none available 109611680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.30% # attempts to use FU when none available 109711680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.30% # attempts to use FU when none available 109811680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.30% # attempts to use FU when none available 109911680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.30% # attempts to use FU when none available 110011680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.30% # attempts to use FU when none available 110111680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 10.30% # attempts to use FU when none available 110211680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.30% # attempts to use FU when none available 110311680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 10.30% # attempts to use FU when none available 110411680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.30% # attempts to use FU when none available 110511680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.30% # attempts to use FU when none available 110611680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.30% # attempts to use FU when none available 110711680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.30% # attempts to use FU when none available 110811680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.30% # attempts to use FU when none available 110911680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.30% # attempts to use FU when none available 111011680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.30% # attempts to use FU when none available 111111680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.30% # attempts to use FU when none available 111211680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.30% # attempts to use FU when none available 111311680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.30% # attempts to use FU when none available 111411680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.30% # attempts to use FU when none available 111511680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::MemRead 182347 55.85% 66.15% # attempts to use FU when none available 111611680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::MemWrite 110540 33.85% 100.00% # attempts to use FU when none available 11178464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 11188464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 111911606Sandreas.sandberg@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued 112011680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 7109835 61.97% 62.01% # Type of FU issued 112111680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IntMult 17232 0.15% 62.16% # Type of FU issued 112211680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.16% # Type of FU issued 112311680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Type of FU issued 112411680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued 112511680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued 112611680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued 112711680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued 112811680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued 112911680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued 113011680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued 113111680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued 113211680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued 113311680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued 113411680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued 113511680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued 113611680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued 113711680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued 113811680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued 113911680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued 114011680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued 114111680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued 114211680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued 114311680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued 114411680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued 114511680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued 114611680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued 114711680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued 114811680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued 114911680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::MemRead 2555661 22.28% 84.58% # Type of FU issued 115011680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 1468866 12.80% 97.39% # Type of FU issued 115111680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued 11528464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 115311680SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued 115411680SCurtis.Dunham@arm.comsystem.cpu1.iq.rate 0.653939 # Inst issue rate 115511680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_busy_cnt 326515 # FU busy when requested 115611680SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_busy_rate 0.028461 # FU busy rate (busy events/executed inst) 115711680SCurtis.Dunham@arm.comsystem.cpu1.iq.int_inst_queue_reads 39721820 # Number of integer instruction queue reads 115811680SCurtis.Dunham@arm.comsystem.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes 115911680SCurtis.Dunham@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses 116011680SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_inst_queue_reads 225266 # Number of floating instruction queue reads 116111680SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes 116211680SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses 116311680SCurtis.Dunham@arm.comsystem.cpu1.iq.int_alu_accesses 11674098 # Number of integer alu accesses 116411680SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_alu_accesses 120130 # Number of floating point alu accesses 116511680SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores 11668464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 116711680SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed 116811680SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 1124 # Number of memory responses ignored because the instruction is squashed 116911680SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 5247 # Number of memory ordering violations 117011680SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 178223 # Number of stores squashed 11718464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 11728464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 117311680SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 530 # Number of loads that were rescheduled 117411680SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 100466 # Number of times an access to memory failed due to the cache being blocked 11758464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 117611680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewSquashCycles 181981 # Number of cycles IEW is squashing 117711680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewBlockCycles 560519 # Number of cycles IEW is blocking 117811680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewUnblockCycles 287887 # Number of cycles IEW is unblocking 117911680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispatchedInsts 13187033 # Number of instructions dispatched to IQ 118011680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispSquashedInsts 58459 # Number of squashed instructions skipped by dispatch 118111680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispLoadInsts 2541438 # Number of dispatched load instructions 118211680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispStoreInsts 1543271 # Number of dispatched store instructions 118311680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 532420 # Number of dispatched non-speculative instructions 118411680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewIQFullEvents 6842 # Number of times the IQ has become full, causing a stall 118511680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewLSQFullEvents 279702 # Number of times the LSQ has become full, causing a stall 118611680SCurtis.Dunham@arm.comsystem.cpu1.iew.memOrderViolationEvents 5247 # Number of memory order violations 118711680SCurtis.Dunham@arm.comsystem.cpu1.iew.predictedTakenIncorrect 45694 # Number of branches that were predicted taken incorrectly 118811680SCurtis.Dunham@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 148663 # Number of branches that were predicted not taken incorrectly 118911680SCurtis.Dunham@arm.comsystem.cpu1.iew.branchMispredicts 194357 # Number of branch mispredicts detected at execute 119011680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewExecutedInsts 11283035 # Number of executed instructions 119111680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewExecLoadInsts 2456415 # Number of load instructions executed 119211680SCurtis.Dunham@arm.comsystem.cpu1.iew.iewExecSquashedInsts 189428 # Number of squashed instructions skipped in execute 11938464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 119411680SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_nop 650401 # number of nop insts executed 119511680SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_refs 3906085 # number of memory reference insts executed 119611680SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_branches 1687752 # Number of branches executed 119711680SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_stores 1449670 # Number of stores executed 119811680SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_rate 0.643141 # Inst execution rate 119911680SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_sent 11111703 # cumulative count of insts sent to commit 120011680SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_count 11056563 # cumulative count of insts written-back 120111680SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_producers 5287384 # num instructions producing a value 120211680SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_consumers 7447136 # num instructions consuming a value 120311680SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_rate 0.630232 # insts written-back per cycle 120411680SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_fanout 0.709989 # average fanout of values written-back 120511680SCurtis.Dunham@arm.comsystem.cpu1.commit.commitSquashedInsts 2591726 # The number of squashed insts skipped by commit 120611680SCurtis.Dunham@arm.comsystem.cpu1.commit.commitNonSpecStalls 153626 # The number of times commit has been forced to stall to communicate backwards 120711680SCurtis.Dunham@arm.comsystem.cpu1.commit.branchMispredicts 169211 # The number of times a branch was mispredicted 120811680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::samples 16186649 # Number of insts commited each cycle 120911680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.645421 # Number of insts commited each cycle 121011680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.620431 # Number of insts commited each cycle 12118464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 121211680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::0 12404611 76.63% 76.63% # Number of insts commited each cycle 121311680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::1 1746252 10.79% 87.42% # Number of insts commited each cycle 121411680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::2 623750 3.85% 91.28% # Number of insts commited each cycle 121511680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::3 386653 2.39% 93.67% # Number of insts commited each cycle 121611680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::4 297145 1.84% 95.50% # Number of insts commited each cycle 121711680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::5 125489 0.78% 96.28% # Number of insts commited each cycle 121811680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::6 112472 0.69% 96.97% # Number of insts commited each cycle 121911680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::7 119580 0.74% 97.71% # Number of insts commited each cycle 122011680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::8 370697 2.29% 100.00% # Number of insts commited each cycle 12218464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 12228464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 12238464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 122411680SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::total 16186649 # Number of insts commited each cycle 122511680SCurtis.Dunham@arm.comsystem.cpu1.commit.committedInsts 10447204 # Number of instructions committed 122611680SCurtis.Dunham@arm.comsystem.cpu1.commit.committedOps 10447204 # Number of ops (including micro ops) committed 12278464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 122811680SCurtis.Dunham@arm.comsystem.cpu1.commit.refs 3352983 # Number of memory references committed 122911680SCurtis.Dunham@arm.comsystem.cpu1.commit.loads 1987935 # Number of loads committed 123011680SCurtis.Dunham@arm.comsystem.cpu1.commit.membars 48912 # Number of memory barriers committed 123111680SCurtis.Dunham@arm.comsystem.cpu1.commit.branches 1499265 # Number of branches committed 123211680SCurtis.Dunham@arm.comsystem.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. 123311680SCurtis.Dunham@arm.comsystem.cpu1.commit.int_insts 9704534 # Number of committed integer instructions. 123411680SCurtis.Dunham@arm.comsystem.cpu1.commit.function_calls 163857 # Number of function calls committed. 123511680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 490367 4.69% 4.69% # Class of committed instruction 123611680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IntAlu 6221313 59.55% 64.24% # Class of committed instruction 123711680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IntMult 16935 0.16% 64.41% # Class of committed instruction 123811680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.41% # Class of committed instruction 123911680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Class of committed instruction 124011680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction 124111680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction 124211680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction 124311680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction 124411680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction 124511680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction 124611680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction 124711680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.56% # Class of committed instruction 124811680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.56% # Class of committed instruction 124911680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.56% # Class of committed instruction 125011680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.56% # Class of committed instruction 125111680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.56% # Class of committed instruction 125211680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.56% # Class of committed instruction 125311680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.56% # Class of committed instruction 125411680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.56% # Class of committed instruction 125511680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.56% # Class of committed instruction 125611680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.56% # Class of committed instruction 125711680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.56% # Class of committed instruction 125811680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.56% # Class of committed instruction 125911680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.56% # Class of committed instruction 126011680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.56% # Class of committed instruction 126111680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% # Class of committed instruction 126211680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction 126311680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction 126411680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction 126511680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::MemRead 2036847 19.50% 84.06% # Class of committed instruction 126611680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::MemWrite 1365632 13.07% 97.13% # Class of committed instruction 126711680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction 126810220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 126911680SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction 127011680SCurtis.Dunham@arm.comsystem.cpu1.commit.bw_lim_events 370697 # number cycles where commit BW limit reached 127111680SCurtis.Dunham@arm.comsystem.cpu1.rob.rob_reads 28744557 # The number of ROB reads 127211680SCurtis.Dunham@arm.comsystem.cpu1.rob.rob_writes 26537349 # The number of ROB writes 127311680SCurtis.Dunham@arm.comsystem.cpu1.timesIdled 134728 # Number of times that the entire CPU went into an idle state and unscheduled itself 127411680SCurtis.Dunham@arm.comsystem.cpu1.idleCycles 895516 # Total number of cycles that the CPU has spent unscheduled due to idling 127511680SCurtis.Dunham@arm.comsystem.cpu1.quiesceCycles 3797555246 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 127611680SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 9961587 # Number of Instructions Simulated 127711680SCurtis.Dunham@arm.comsystem.cpu1.committedOps 9961587 # Number of Ops (including micro ops) Simulated 127811680SCurtis.Dunham@arm.comsystem.cpu1.cpi 1.761128 # CPI: Cycles Per Instruction 127911680SCurtis.Dunham@arm.comsystem.cpu1.cpi_total 1.761128 # CPI: Total CPI of All Threads 128011680SCurtis.Dunham@arm.comsystem.cpu1.ipc 0.567818 # IPC: Instructions Per Cycle 128111680SCurtis.Dunham@arm.comsystem.cpu1.ipc_total 0.567818 # IPC: Total IPC of All Threads 128211680SCurtis.Dunham@arm.comsystem.cpu1.int_regfile_reads 14521823 # number of integer regfile reads 128311680SCurtis.Dunham@arm.comsystem.cpu1.int_regfile_writes 7909607 # number of integer regfile writes 128411680SCurtis.Dunham@arm.comsystem.cpu1.fp_regfile_reads 58779 # number of floating regfile reads 128511680SCurtis.Dunham@arm.comsystem.cpu1.fp_regfile_writes 57835 # number of floating regfile writes 128611680SCurtis.Dunham@arm.comsystem.cpu1.misc_regfile_reads 571518 # number of misc regfile reads 128711680SCurtis.Dunham@arm.comsystem.cpu1.misc_regfile_writes 244969 # number of misc regfile writes 128811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 128911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 130966 # number of replacements 129011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 487.964655 # Cycle average of tags in use 129111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 3061418 # Total number of references to valid blocks. 129211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 131478 # Sample count of references to valid blocks. 129311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 23.284641 # Average number of references to valid blocks. 129411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 49531315500 # Cycle when the warmup percentage was hit. 129511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 487.964655 # Average occupied blocks per requestor 129611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.953056 # Average percentage of cache occupancy 129711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.953056 # Average percentage of cache occupancy 129811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 129911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id 130011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 130111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 130211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 130311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 14512669 # Number of tag accesses 130411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 14512669 # Number of data accesses 130511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 130611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1946433 # number of ReadReq hits 130711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1946433 # number of ReadReq hits 130811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1026063 # number of WriteReq hits 130911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1026063 # number of WriteReq hits 131011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40785 # number of LoadLockedReq hits 131111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 40785 # number of LoadLockedReq hits 131211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 37242 # number of StoreCondReq hits 131311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 37242 # number of StoreCondReq hits 131411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 2972496 # number of demand (read+write) hits 131511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 2972496 # number of demand (read+write) hits 131611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 2972496 # number of overall hits 131711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 2972496 # number of overall hits 131811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 241711 # number of ReadReq misses 131911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 241711 # number of ReadReq misses 132011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 292248 # number of WriteReq misses 132111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 292248 # number of WriteReq misses 132211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5308 # number of LoadLockedReq misses 132311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5308 # number of LoadLockedReq misses 132411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 3094 # number of StoreCondReq misses 132511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 3094 # number of StoreCondReq misses 132611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 533959 # number of demand (read+write) misses 132711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 533959 # number of demand (read+write) misses 132811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 533959 # number of overall misses 132911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 533959 # number of overall misses 133011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3394927000 # number of ReadReq miss cycles 133111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 3394927000 # number of ReadReq miss cycles 133211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12114051455 # number of WriteReq miss cycles 133311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 12114051455 # number of WriteReq miss cycles 133411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54394000 # number of LoadLockedReq miss cycles 133511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 54394000 # number of LoadLockedReq miss cycles 133611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17165000 # number of StoreCondReq miss cycles 133711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 17165000 # number of StoreCondReq miss cycles 133811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 15508978455 # number of demand (read+write) miss cycles 133911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 15508978455 # number of demand (read+write) miss cycles 134011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 15508978455 # number of overall miss cycles 134111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 15508978455 # number of overall miss cycles 134211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2188144 # number of ReadReq accesses(hits+misses) 134311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2188144 # number of ReadReq accesses(hits+misses) 134411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1318311 # number of WriteReq accesses(hits+misses) 134511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 1318311 # number of WriteReq accesses(hits+misses) 134611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46093 # number of LoadLockedReq accesses(hits+misses) 134711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 46093 # number of LoadLockedReq accesses(hits+misses) 134811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40336 # number of StoreCondReq accesses(hits+misses) 134911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 40336 # number of StoreCondReq accesses(hits+misses) 135011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 3506455 # number of demand (read+write) accesses 135111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 3506455 # number of demand (read+write) accesses 135211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 3506455 # number of overall (read+write) accesses 135311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 3506455 # number of overall (read+write) accesses 135411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110464 # miss rate for ReadReq accesses 135511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.110464 # miss rate for ReadReq accesses 135611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221684 # miss rate for WriteReq accesses 135711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.221684 # miss rate for WriteReq accesses 135811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115158 # miss rate for LoadLockedReq accesses 135911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115158 # miss rate for LoadLockedReq accesses 136011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076706 # miss rate for StoreCondReq accesses 136111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.076706 # miss rate for StoreCondReq accesses 136211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.152279 # miss rate for demand accesses 136311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.152279 # miss rate for demand accesses 136411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.152279 # miss rate for overall accesses 136511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.152279 # miss rate for overall accesses 136611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189 # average ReadReq miss latency 136711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189 # average ReadReq miss latency 136811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395 # average WriteReq miss latency 136911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395 # average WriteReq miss latency 137011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867 # average LoadLockedReq miss latency 137111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867 # average LoadLockedReq miss latency 137211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5547.834518 # average StoreCondReq miss latency 137311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5547.834518 # average StoreCondReq miss latency 137411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency 137511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 29045.260881 # average overall miss latency 137611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency 137711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 29045.260881 # average overall miss latency 137811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 715753 # number of cycles access was blocked 137911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 884 # number of cycles access was blocked 138011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_mshrs 24925 # number of cycles access was blocked 138111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_targets 13 # number of cycles access was blocked 138211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.716269 # average number of cycles each access was blocked 138311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked 138411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 84601 # number of writebacks 138511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 84601 # number of writebacks 138611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148639 # number of ReadReq MSHR hits 138711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 148639 # number of ReadReq MSHR hits 138811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243827 # number of WriteReq MSHR hits 138911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 243827 # number of WriteReq MSHR hits 139011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 846 # number of LoadLockedReq MSHR hits 139111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 846 # number of LoadLockedReq MSHR hits 139211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 392466 # number of demand (read+write) MSHR hits 139311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 392466 # number of demand (read+write) MSHR hits 139411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 392466 # number of overall MSHR hits 139511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 392466 # number of overall MSHR hits 139611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93072 # number of ReadReq MSHR misses 139711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 93072 # number of ReadReq MSHR misses 139811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48421 # number of WriteReq MSHR misses 139911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 48421 # number of WriteReq MSHR misses 140011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4462 # number of LoadLockedReq MSHR misses 140111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 4462 # number of LoadLockedReq MSHR misses 140211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3093 # number of StoreCondReq MSHR misses 140311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 3093 # number of StoreCondReq MSHR misses 140411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 141493 # number of demand (read+write) MSHR misses 140511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 141493 # number of demand (read+write) MSHR misses 140611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 141493 # number of overall MSHR misses 140711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 141493 # number of overall MSHR misses 140811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable 140911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable 141011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable 141111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 3153 # number of WriteReq MSHR uncacheable 141211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses 141311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 3371 # number of overall MSHR uncacheable misses 141411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262526500 # number of ReadReq MSHR miss cycles 141511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262526500 # number of ReadReq MSHR miss cycles 141611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1947214752 # number of WriteReq MSHR miss cycles 141711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1947214752 # number of WriteReq MSHR miss cycles 141811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40086500 # number of LoadLockedReq MSHR miss cycles 141911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40086500 # number of LoadLockedReq MSHR miss cycles 142011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14072000 # number of StoreCondReq MSHR miss cycles 142111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14072000 # number of StoreCondReq MSHR miss cycles 142211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3209741252 # number of demand (read+write) MSHR miss cycles 142311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 3209741252 # number of demand (read+write) MSHR miss cycles 142411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3209741252 # number of overall MSHR miss cycles 142511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 3209741252 # number of overall MSHR miss cycles 142611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41866500 # number of ReadReq MSHR uncacheable cycles 142711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41866500 # number of ReadReq MSHR uncacheable cycles 142811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41866500 # number of overall MSHR uncacheable cycles 142911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 41866500 # number of overall MSHR uncacheable cycles 143011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042535 # mshr miss rate for ReadReq accesses 143111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042535 # mshr miss rate for ReadReq accesses 143211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses 143311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses 143411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096804 # mshr miss rate for LoadLockedReq accesses 143511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096804 # mshr miss rate for LoadLockedReq accesses 143611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076681 # mshr miss rate for StoreCondReq accesses 143711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076681 # mshr miss rate for StoreCondReq accesses 143811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for demand accesses 143911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.040352 # mshr miss rate for demand accesses 144011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for overall accesses 144111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.040352 # mshr miss rate for overall accesses 144211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788 # average ReadReq mshr miss latency 144311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788 # average ReadReq mshr miss latency 144411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416 # average WriteReq mshr miss latency 144511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416 # average WriteReq mshr miss latency 144611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8983.975796 # average LoadLockedReq mshr miss latency 144711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8983.975796 # average LoadLockedReq mshr miss latency 144811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.628193 # average StoreCondReq mshr miss latency 144911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.628193 # average StoreCondReq mshr miss latency 145011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency 145111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency 145211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency 145311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency 145411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138 # average ReadReq mshr uncacheable latency 145511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138 # average ReadReq mshr uncacheable latency 145611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425 # average overall mshr uncacheable latency 145711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425 # average overall mshr uncacheable latency 145811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 145911680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 256896 # number of replacements 146011680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 470.782709 # Cycle average of tags in use 146111680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 1710963 # Total number of references to valid blocks. 146211680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 257408 # Sample count of references to valid blocks. 146311680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 6.646891 # Average number of references to valid blocks. 146411680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 1882016787500 # Cycle when the warmup percentage was hit. 146511680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 470.782709 # Average occupied blocks per requestor 146611680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.919497 # Average percentage of cache occupancy 146711680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.919497 # Average percentage of cache occupancy 146811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 146911680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 147011680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 147111680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id 147211680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 147311680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 2238053 # Number of tag accesses 147411680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 2238053 # Number of data accesses 147511680SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 147611680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 1710963 # number of ReadReq hits 147711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 1710963 # number of ReadReq hits 147811680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 1710963 # number of demand (read+write) hits 147911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 1710963 # number of demand (read+write) hits 148011680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 1710963 # number of overall hits 148111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 1710963 # number of overall hits 148211680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 269604 # number of ReadReq misses 148311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 269604 # number of ReadReq misses 148411680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 269604 # number of demand (read+write) misses 148511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 269604 # number of demand (read+write) misses 148611680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 269604 # number of overall misses 148711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 269604 # number of overall misses 148811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3754413998 # number of ReadReq miss cycles 148911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 3754413998 # number of ReadReq miss cycles 149011680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 3754413998 # number of demand (read+write) miss cycles 149111680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 3754413998 # number of demand (read+write) miss cycles 149211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 3754413998 # number of overall miss cycles 149311680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 3754413998 # number of overall miss cycles 149411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1980567 # number of ReadReq accesses(hits+misses) 149511680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 1980567 # number of ReadReq accesses(hits+misses) 149611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 1980567 # number of demand (read+write) accesses 149711680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 1980567 # number of demand (read+write) accesses 149811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 1980567 # number of overall (read+write) accesses 149911680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 1980567 # number of overall (read+write) accesses 150011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136125 # miss rate for ReadReq accesses 150111680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.136125 # miss rate for ReadReq accesses 150211680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.136125 # miss rate for demand accesses 150311680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.136125 # miss rate for demand accesses 150411680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.136125 # miss rate for overall accesses 150511680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.136125 # miss rate for overall accesses 150611680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333 # average ReadReq miss latency 150711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333 # average ReadReq miss latency 150811680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency 150911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 13925.661333 # average overall miss latency 151011680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency 151111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 13925.661333 # average overall miss latency 151211680SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 473 # number of cycles access was blocked 151310576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 151411680SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked 151510576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 151611680SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 11.261905 # average number of cycles each access was blocked 151710576Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 151811680SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 256896 # number of writebacks 151911680SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 256896 # number of writebacks 152011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12118 # number of ReadReq MSHR hits 152111680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 12118 # number of ReadReq MSHR hits 152211680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 12118 # number of demand (read+write) MSHR hits 152311680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_hits::total 12118 # number of demand (read+write) MSHR hits 152411680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 12118 # number of overall MSHR hits 152511680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_hits::total 12118 # number of overall MSHR hits 152611680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257486 # number of ReadReq MSHR misses 152711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 257486 # number of ReadReq MSHR misses 152811680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 257486 # number of demand (read+write) MSHR misses 152911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 257486 # number of demand (read+write) MSHR misses 153011680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 257486 # number of overall MSHR misses 153111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 257486 # number of overall MSHR misses 153211680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3368066498 # number of ReadReq MSHR miss cycles 153311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 3368066498 # number of ReadReq MSHR miss cycles 153411680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3368066498 # number of demand (read+write) MSHR miss cycles 153511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 3368066498 # number of demand (read+write) MSHR miss cycles 153611680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3368066498 # number of overall MSHR miss cycles 153711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 3368066498 # number of overall MSHR miss cycles 153811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for ReadReq accesses 153911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.130006 # mshr miss rate for ReadReq accesses 154011680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for demand accesses 154111680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.130006 # mshr miss rate for demand accesses 154211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for overall accesses 154311680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.130006 # mshr miss rate for overall accesses 154411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average ReadReq mshr miss latency 154511680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072 # average ReadReq mshr miss latency 154611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency 154711680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency 154811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency 154911680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency 155010576Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 155110576Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 155210576Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 155310576Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 155410576Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 155510576Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 155610576Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 155710576Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 155810576Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 155910576Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 156010576Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 156110576Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 156211680SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 156311606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadReq 7374 # Transaction distribution 156411606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadResp 7374 # Transaction distribution 156511680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 54611 # Transaction distribution 156611680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 54611 # Transaction distribution 156711680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11908 # Packet count per connected master and slave (bytes) 156811606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 156910576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 157010576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 157110892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 157210892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 157310576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 157411570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 157510576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 157611680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 40508 # Packet count per connected master and slave (bytes) 157711606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 157811606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 157911680SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 123970 # Packet count per connected master and slave (bytes) 158011680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47632 # Cumulative packet size per connected master and slave (bytes) 158111606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 158210576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 158310576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 158410892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 158510892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 158610576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 158711570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 158810576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 158911680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 73858 # Cumulative packet size per connected master and slave (bytes) 159011606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 159111606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 159211680SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 2735514 # Cumulative packet size per connected master and slave (bytes) 159311680SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 12353502 # Layer occupancy (ticks) 159410576Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 159511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 824500 # Layer occupancy (ticks) 159610576Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 159711502SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 159810576Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 159911680SCurtis.Dunham@arm.comsystem.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 160010576Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 160111680SCurtis.Dunham@arm.comsystem.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) 160210576Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 160311680SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 13988000 # Layer occupancy (ticks) 160410576Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 160511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) 160610576Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 160711680SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 6060500 # Layer occupancy (ticks) 160810576Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 160911570SCurtis.Dunham@arm.comsystem.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 161010576Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 161111680SCurtis.Dunham@arm.comsystem.iobus.reqLayer27.occupancy 216282007 # Layer occupancy (ticks) 161210576Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 161311680SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) 161410576Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 161511606Sandreas.sandberg@arm.comsystem.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) 161610576Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 161711680SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 161811606Sandreas.sandberg@arm.comsystem.iocache.tags.replacements 41699 # number of replacements 161911680SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 0.490946 # Cycle average of tags in use 162010576Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 162111606Sandreas.sandberg@arm.comsystem.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 162210576Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 162311680SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 1714262123000 # Cycle when the warmup percentage was hit. 162411680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.490946 # Average occupied blocks per requestor 162511680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.030684 # Average percentage of cache occupancy 162611680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.030684 # Average percentage of cache occupancy 162710576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 162811606Sandreas.sandberg@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 162910576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 163011606Sandreas.sandberg@arm.comsystem.iocache.tags.tag_accesses 375579 # Number of tag accesses 163111606Sandreas.sandberg@arm.comsystem.iocache.tags.data_accesses 375579 # Number of data accesses 163211680SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 163311606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 163411606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 163510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 163610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 163711606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 163811606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::total 41731 # number of demand (read+write) misses 163911606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 164011606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::total 41731 # number of overall misses 164111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 22774383 # number of ReadReq miss cycles 164211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 22774383 # number of ReadReq miss cycles 164311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 4918988624 # number of WriteLineReq miss cycles 164411680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 4918988624 # number of WriteLineReq miss cycles 164511680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 4941763007 # number of demand (read+write) miss cycles 164611680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 4941763007 # number of demand (read+write) miss cycles 164711680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 4941763007 # number of overall miss cycles 164811680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 4941763007 # number of overall miss cycles 164911606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 165011606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 165110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 165210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 165311606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 165411606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 165511606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 165611606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 165710576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 165810576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 165910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 166010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 166110576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 166210576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 166310576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 166410576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 166511680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944 # average ReadReq miss latency 166611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 127231.189944 # average ReadReq miss latency 166711680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899 # average WriteLineReq miss latency 166811680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 118381.512899 # average WriteLineReq miss latency 166911680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency 167011680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 118419.472502 # average overall miss latency 167111680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency 167211680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 118419.472502 # average overall miss latency 167311680SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 1165 # number of cycles access was blocked 167410576Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 167511680SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 8 # number of cycles access was blocked 167610576Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 167711680SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 145.625000 # average number of cycles each access was blocked 167810576Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 167911103Snilay@cs.wisc.edusystem.iocache.writebacks::writebacks 41520 # number of writebacks 168011103Snilay@cs.wisc.edusystem.iocache.writebacks::total 41520 # number of writebacks 168111606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 168211606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 168310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 168410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 168511606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 168611606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 168711606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 168811606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses 168911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13824383 # number of ReadReq MSHR miss cycles 169011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13824383 # number of ReadReq MSHR miss cycles 169111680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2838948426 # number of WriteLineReq MSHR miss cycles 169211680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 2838948426 # number of WriteLineReq MSHR miss cycles 169311680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 2852772809 # number of demand (read+write) MSHR miss cycles 169411680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 2852772809 # number of demand (read+write) MSHR miss cycles 169511680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 2852772809 # number of overall MSHR miss cycles 169611680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 2852772809 # number of overall MSHR miss cycles 169710576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 169810576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 169910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 170010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 170110576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 170210576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 170310576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 170410576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 170511680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944 # average ReadReq mshr miss latency 170611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944 # average ReadReq mshr miss latency 170711680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533 # average WriteLineReq mshr miss latency 170811680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533 # average WriteLineReq mshr miss latency 170911680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency 171011680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency 171111680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency 171211680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency 171311680SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 171411680SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 345941 # number of replacements 171511680SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 65423.095027 # Cycle average of tags in use 171611680SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 4335515 # Total number of references to valid blocks. 171711680SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 411463 # Sample count of references to valid blocks. 171811680SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 10.536828 # Average number of references to valid blocks. 171911680SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 6416575000 # Cycle when the warmup percentage was hit. 172011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 293.307825 # Average occupied blocks per requestor 172111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5315.079150 # Average occupied blocks per requestor 172211680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 58827.069962 # Average occupied blocks per requestor 172311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 210.319847 # Average occupied blocks per requestor 172411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 777.318243 # Average occupied blocks per requestor 172511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.004476 # Average percentage of cache occupancy 172611680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.081102 # Average percentage of cache occupancy 172711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.897630 # Average percentage of cache occupancy 172811680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.003209 # Average percentage of cache occupancy 172911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011861 # Average percentage of cache occupancy 173011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.998277 # Average percentage of cache occupancy 173111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 173211680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 173311680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 1694 # Occupied blocks per task id 173411680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1843 # Occupied blocks per task id 173511680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5673 # Occupied blocks per task id 173611680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 56180 # Occupied blocks per task id 173711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 173811680SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 38390429 # Number of tag accesses 173911680SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 38390429 # Number of data accesses 174011680SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 174111680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 822340 # number of WritebackDirty hits 174211680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 822340 # number of WritebackDirty hits 174311680SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::writebacks 875169 # number of WritebackClean hits 174411680SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::total 875169 # number of WritebackClean hits 174511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits 174611680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 1494 # number of UpgradeReq hits 174711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 4357 # number of UpgradeReq hits 174811680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits 174911680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 467 # number of SCUpgradeReq hits 175011680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 968 # number of SCUpgradeReq hits 175111680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 145988 # number of ReadExReq hits 175211680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 30963 # number of ReadExReq hits 175311680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 176951 # number of ReadExReq hits 175411680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 881644 # number of ReadCleanReq hits 175511680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 255533 # number of ReadCleanReq hits 175611680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::total 1137177 # number of ReadCleanReq hits 175711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 722233 # number of ReadSharedReq hits 175811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 84048 # number of ReadSharedReq hits 175911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 806281 # number of ReadSharedReq hits 176011680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 881644 # number of demand (read+write) hits 176111680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 868221 # number of demand (read+write) hits 176211680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 255533 # number of demand (read+write) hits 176311680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 115011 # number of demand (read+write) hits 176411680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 2120409 # number of demand (read+write) hits 176511680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 881644 # number of overall hits 176611680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 868221 # number of overall hits 176711680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 255533 # number of overall hits 176811680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 115011 # number of overall hits 176911680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 2120409 # number of overall hits 177011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 6 # number of UpgradeReq misses 177111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses 177211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 11 # number of UpgradeReq misses 177311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses 177411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 177511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 109595 # number of ReadExReq misses 177611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 12065 # number of ReadExReq misses 177711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 121660 # number of ReadExReq misses 177811680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 13405 # number of ReadCleanReq misses 177911680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 1909 # number of ReadCleanReq misses 178011680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::total 15314 # number of ReadCleanReq misses 178111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 272577 # number of ReadSharedReq misses 178211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1964 # number of ReadSharedReq misses 178311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 274541 # number of ReadSharedReq misses 178411680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 13405 # number of demand (read+write) misses 178511680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 382172 # number of demand (read+write) misses 178611680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 1909 # number of demand (read+write) misses 178711680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 14029 # number of demand (read+write) misses 178811680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 411515 # number of demand (read+write) misses 178911680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 13405 # number of overall misses 179011680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 382172 # number of overall misses 179111680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 1909 # number of overall misses 179211680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 14029 # number of overall misses 179311680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 411515 # number of overall misses 179411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 332000 # number of UpgradeReq miss cycles 179511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 117000 # number of UpgradeReq miss cycles 179611680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::total 449000 # number of UpgradeReq miss cycles 179711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 11349867000 # number of ReadExReq miss cycles 179811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 1517430000 # number of ReadExReq miss cycles 179911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 12867297000 # number of ReadExReq miss cycles 180011680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu0.inst 1343054000 # number of ReadCleanReq miss cycles 180111680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu1.inst 191509000 # number of ReadCleanReq miss cycles 180211680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::total 1534563000 # number of ReadCleanReq miss cycles 180311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 22206710000 # number of ReadSharedReq miss cycles 180411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 230127000 # number of ReadSharedReq miss cycles 180511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 22436837000 # number of ReadSharedReq miss cycles 180611680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 1343054000 # number of demand (read+write) miss cycles 180711680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 33556577000 # number of demand (read+write) miss cycles 180811680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 191509000 # number of demand (read+write) miss cycles 180911680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 1747557000 # number of demand (read+write) miss cycles 181011680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 36838697000 # number of demand (read+write) miss cycles 181111680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 1343054000 # number of overall miss cycles 181211680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 33556577000 # number of overall miss cycles 181311680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 191509000 # number of overall miss cycles 181411680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 1747557000 # number of overall miss cycles 181511680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 36838697000 # number of overall miss cycles 181611680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 822340 # number of WritebackDirty accesses(hits+misses) 181711680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 822340 # number of WritebackDirty accesses(hits+misses) 181811680SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::writebacks 875169 # number of WritebackClean accesses(hits+misses) 181911680SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::total 875169 # number of WritebackClean accesses(hits+misses) 182011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2869 # number of UpgradeReq accesses(hits+misses) 182111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 1499 # number of UpgradeReq accesses(hits+misses) 182211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 4368 # number of UpgradeReq accesses(hits+misses) 182311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 501 # number of SCUpgradeReq accesses(hits+misses) 182411680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 468 # number of SCUpgradeReq accesses(hits+misses) 182511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 969 # number of SCUpgradeReq accesses(hits+misses) 182611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 255583 # number of ReadExReq accesses(hits+misses) 182711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 43028 # number of ReadExReq accesses(hits+misses) 182811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 298611 # number of ReadExReq accesses(hits+misses) 182911680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 895049 # number of ReadCleanReq accesses(hits+misses) 183011680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 257442 # number of ReadCleanReq accesses(hits+misses) 183111680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::total 1152491 # number of ReadCleanReq accesses(hits+misses) 183211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 994810 # number of ReadSharedReq accesses(hits+misses) 183311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 86012 # number of ReadSharedReq accesses(hits+misses) 183411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 1080822 # number of ReadSharedReq accesses(hits+misses) 183511680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 895049 # number of demand (read+write) accesses 183611680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 1250393 # number of demand (read+write) accesses 183711680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 257442 # number of demand (read+write) accesses 183811680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 129040 # number of demand (read+write) accesses 183911680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 2531924 # number of demand (read+write) accesses 184011680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 895049 # number of overall (read+write) accesses 184111680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 1250393 # number of overall (read+write) accesses 184211680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 257442 # number of overall (read+write) accesses 184311680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 129040 # number of overall (read+write) accesses 184411680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 2531924 # number of overall (read+write) accesses 184511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.002091 # miss rate for UpgradeReq accesses 184611680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.003336 # miss rate for UpgradeReq accesses 184711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.002518 # miss rate for UpgradeReq accesses 184811680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002137 # miss rate for SCUpgradeReq accesses 184911680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.001032 # miss rate for SCUpgradeReq accesses 185011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.428804 # miss rate for ReadExReq accesses 185111680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.280399 # miss rate for ReadExReq accesses 185211680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.407420 # miss rate for ReadExReq accesses 185311680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014977 # miss rate for ReadCleanReq accesses 185411680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007415 # miss rate for ReadCleanReq accesses 185511680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.013288 # miss rate for ReadCleanReq accesses 185611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273999 # miss rate for ReadSharedReq accesses 185711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022834 # miss rate for ReadSharedReq accesses 185811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.254011 # miss rate for ReadSharedReq accesses 185911680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.014977 # miss rate for demand accesses 186011680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.305642 # miss rate for demand accesses 186111680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.007415 # miss rate for demand accesses 186211680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.108718 # miss rate for demand accesses 186311680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.162531 # miss rate for demand accesses 186411680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.014977 # miss rate for overall accesses 186511680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.305642 # miss rate for overall accesses 186611680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.007415 # miss rate for overall accesses 186711680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.108718 # miss rate for overall accesses 186811680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.162531 # miss rate for overall accesses 186911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 55333.333333 # average UpgradeReq miss latency 187011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23400 # average UpgradeReq miss latency 187111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 40818.181818 # average UpgradeReq miss latency 187211680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 103561.905196 # average ReadExReq miss latency 187311680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 125771.239121 # average ReadExReq miss latency 187411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 105764.400789 # average ReadExReq miss latency 187511680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100190.525923 # average ReadCleanReq miss latency 187611680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 100319.015191 # average ReadCleanReq miss latency 187711680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::total 100206.543033 # average ReadCleanReq miss latency 187811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81469.493024 # average ReadSharedReq miss latency 187911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117172.606925 # average ReadSharedReq miss latency 188011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 81724.904477 # average ReadSharedReq miss latency 188111680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency 188211680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency 188311680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency 188411680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency 188511680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 89519.694300 # average overall miss latency 188611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency 188711680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency 188811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency 188911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency 189011680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 89519.694300 # average overall miss latency 189110576Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 189210576Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 189310576Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 189410576Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 189510576Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189610576Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 189711680SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 82096 # number of writebacks 189811680SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 82096 # number of writebacks 189911606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 190011441Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits 190111606Sandreas.sandberg@arm.comsystem.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits 190211606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 190311441Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 190411606Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 190511606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 190611441Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 190711606Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 190811680SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses 190911680SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses 191011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 6 # number of UpgradeReq MSHR misses 191111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses 191211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses 191311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses 191411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 191511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 109595 # number of ReadExReq MSHR misses 191611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 12065 # number of ReadExReq MSHR misses 191711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 121660 # number of ReadExReq MSHR misses 191811680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13404 # number of ReadCleanReq MSHR misses 191911680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1892 # number of ReadCleanReq MSHR misses 192011680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::total 15296 # number of ReadCleanReq MSHR misses 192111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 272577 # number of ReadSharedReq MSHR misses 192211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 1964 # number of ReadSharedReq MSHR misses 192311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 274541 # number of ReadSharedReq MSHR misses 192411680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 13404 # number of demand (read+write) MSHR misses 192511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 382172 # number of demand (read+write) MSHR misses 192611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 1892 # number of demand (read+write) MSHR misses 192711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses 192811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 411497 # number of demand (read+write) MSHR misses 192911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 13404 # number of overall MSHR misses 193011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 382172 # number of overall MSHR misses 193111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 1892 # number of overall MSHR misses 193211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses 193311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 411497 # number of overall MSHR misses 193411680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable 193511680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable 193611606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable 193711680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable 193811680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable 193911680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 13059 # number of WriteReq MSHR uncacheable 194011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses 194111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses 194211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 20254 # number of overall MSHR uncacheable misses 194311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 272000 # number of UpgradeReq MSHR miss cycles 194411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 95500 # number of UpgradeReq MSHR miss cycles 194511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 367500 # number of UpgradeReq MSHR miss cycles 194611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles 194711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles 194811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10253916501 # number of ReadExReq MSHR miss cycles 194911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1396780000 # number of ReadExReq MSHR miss cycles 195011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 11650696501 # number of ReadExReq MSHR miss cycles 195111680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1208926000 # number of ReadCleanReq MSHR miss cycles 195211680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 171260500 # number of ReadCleanReq MSHR miss cycles 195311680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::total 1380186500 # number of ReadCleanReq MSHR miss cycles 195411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19486691503 # number of ReadSharedReq MSHR miss cycles 195511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 210487000 # number of ReadSharedReq MSHR miss cycles 195611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 19697178503 # number of ReadSharedReq MSHR miss cycles 195711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 1208926000 # number of demand (read+write) MSHR miss cycles 195811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 29740608004 # number of demand (read+write) MSHR miss cycles 195911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 171260500 # number of demand (read+write) MSHR miss cycles 196011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 1607267000 # number of demand (read+write) MSHR miss cycles 196111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 32728061504 # number of demand (read+write) MSHR miss cycles 196211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 1208926000 # number of overall MSHR miss cycles 196311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 29740608004 # number of overall MSHR miss cycles 196411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 171260500 # number of overall MSHR miss cycles 196511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 1607267000 # number of overall MSHR miss cycles 196611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 32728061504 # number of overall MSHR miss cycles 196711680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469664500 # number of ReadReq MSHR uncacheable cycles 196811680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39141500 # number of ReadReq MSHR uncacheable cycles 196911680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1508806000 # number of ReadReq MSHR uncacheable cycles 197011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469664500 # number of overall MSHR uncacheable cycles 197111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 39141500 # number of overall MSHR uncacheable cycles 197211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 1508806000 # number of overall MSHR uncacheable cycles 197310892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 197410892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 197511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002091 # mshr miss rate for UpgradeReq accesses 197611680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003336 # mshr miss rate for UpgradeReq accesses 197711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.002518 # mshr miss rate for UpgradeReq accesses 197811680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for SCUpgradeReq accesses 197911680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001032 # mshr miss rate for SCUpgradeReq accesses 198011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428804 # mshr miss rate for ReadExReq accesses 198111680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280399 # mshr miss rate for ReadExReq accesses 198211680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.407420 # mshr miss rate for ReadExReq accesses 198311680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for ReadCleanReq accesses 198411680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for ReadCleanReq accesses 198511680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::total 0.013272 # mshr miss rate for ReadCleanReq accesses 198611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273999 # mshr miss rate for ReadSharedReq accesses 198711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022834 # mshr miss rate for ReadSharedReq accesses 198811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.254011 # mshr miss rate for ReadSharedReq accesses 198911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for demand accesses 199011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for demand accesses 199111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for demand accesses 199211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for demand accesses 199311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.162523 # mshr miss rate for demand accesses 199411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for overall accesses 199511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for overall accesses 199611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for overall accesses 199711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for overall accesses 199811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.162523 # mshr miss rate for overall accesses 199911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45333.333333 # average UpgradeReq mshr miss latency 200011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19100 # average UpgradeReq mshr miss latency 200111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 33409.090909 # average UpgradeReq mshr miss latency 200211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency 200311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency 200411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93561.900643 # average ReadExReq mshr miss latency 200511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 115771.239121 # average ReadExReq mshr miss latency 200611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 95764.396687 # average ReadExReq mshr miss latency 200711680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average ReadCleanReq mshr miss latency 200811680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average ReadCleanReq mshr miss latency 200911680SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90231.858002 # average ReadCleanReq mshr miss latency 201011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71490.593495 # average ReadSharedReq mshr miss latency 201111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107172.606925 # average ReadSharedReq mshr miss latency 201211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71745.854000 # average ReadSharedReq mshr miss latency 201311680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency 201411680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency 201511680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency 201611680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency 201711680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency 201811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency 201911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency 202011680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency 202111680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency 202211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency 202311680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046 # average ReadReq mshr uncacheable latency 202411680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138 # average ReadReq mshr uncacheable latency 202511680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288 # average ReadReq mshr uncacheable latency 202611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500 # average overall mshr uncacheable latency 202711680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955 # average overall mshr uncacheable latency 202811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363 # average overall mshr uncacheable latency 202911680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 852108 # Total number of requests made to the snoop filter. 203011680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 399805 # Number of requests hitting in the snoop filter with a single holder of the requested data. 203111680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 437 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 203211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 203311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 203411502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 203511680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 203611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadReq 7195 # Transaction distribution 203711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 297167 # Transaction distribution 203811680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 13059 # Transaction distribution 203911680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 13059 # Transaction distribution 204011680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 123616 # Transaction distribution 204111680SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 263125 # Transaction distribution 204211680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 6609 # Transaction distribution 204311680SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 5164 # Transaction distribution 204411336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 204511680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 121953 # Transaction distribution 204611680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 121548 # Transaction distribution 204711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 290016 # Transaction distribution 204811680SCurtis.Dunham@arm.comsystem.membus.trans_dist::BadAddressError 44 # Transaction distribution 204910892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 205011680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40508 # Packet count per connected master and slave (bytes) 205111680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179616 # Packet count per connected master and slave (bytes) 205211680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 88 # Packet count per connected master and slave (bytes) 205311680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 1220212 # Packet count per connected master and slave (bytes) 205411606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) 205511606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) 205611680SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 1303657 # Packet count per connected master and slave (bytes) 205711680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73858 # Cumulative packet size per connected master and slave (bytes) 205811680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31561664 # Cumulative packet size per connected master and slave (bytes) 205911680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 31635522 # Cumulative packet size per connected master and slave (bytes) 206011103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 206111103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 206211680SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 34293762 # Cumulative packet size per connected master and slave (bytes) 206311680SCurtis.Dunham@arm.comsystem.membus.snoops 12507 # Total snoops (count) 206411680SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 28800 # Total snoop traffic (bytes) 206511680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 485548 # Request fanout histogram 206611680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.001427 # Request fanout histogram 206711680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.037752 # Request fanout histogram 206810576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 206911680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 484855 99.86% 99.86% # Request fanout histogram 207011680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 693 0.14% 100.00% # Request fanout histogram 207110576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 207210576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 207311502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 207410576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 207511680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 485548 # Request fanout histogram 207611680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 36350498 # Layer occupancy (ticks) 207710576Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 207811680SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 1353965073 # Layer occupancy (ticks) 207910576Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 208011680SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 55000 # Layer occupancy (ticks) 208110576Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 208211680SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2179761000 # Layer occupancy (ticks) 208310726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 208411680SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 960863 # Layer occupancy (ticks) 208510576Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 208611680SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 208711680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 5108724 # Total number of requests made to the snoop filter. 208811680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 2554049 # Number of requests hitting in the snoop filter with a single holder of the requested data. 208911680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 343728 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 209011680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. 209111680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 209211138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 209311680SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 209411606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution 209511680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 2263429 # Transaction distribution 209611680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 13059 # Transaction distribution 209711680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 13059 # Transaction distribution 209811680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 904436 # Transaction distribution 209911680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1151326 # Transaction distribution 210011680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 825788 # Transaction distribution 210111680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 10854 # Transaction distribution 210211680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 6132 # Transaction distribution 210311680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 16986 # Transaction distribution 210411680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 300014 # Transaction distribution 210511680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 300014 # Transaction distribution 210611680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1152722 # Transaction distribution 210711680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 1103559 # Transaction distribution 210811680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::BadAddressError 44 # Transaction distribution 210911680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 238 # Transaction distribution 211011680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2684715 # Packet count per connected master and slave (bytes) 211111680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3812301 # Packet count per connected master and slave (bytes) 211211680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771824 # Packet count per connected master and slave (bytes) 211311680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417816 # Packet count per connected master and slave (bytes) 211411680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 7686656 # Packet count per connected master and slave (bytes) 211511680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114526656 # Cumulative packet size per connected master and slave (bytes) 211611680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127297140 # Cumulative packet size per connected master and slave (bytes) 211711680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32917632 # Cumulative packet size per connected master and slave (bytes) 211811680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13697806 # Cumulative packet size per connected master and slave (bytes) 211911680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 288439234 # Cumulative packet size per connected master and slave (bytes) 212011680SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 382362 # Total snoops (count) 212111680SCurtis.Dunham@arm.comsystem.toL2Bus.snoopTraffic 6813696 # Total snoop traffic (bytes) 212211680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 2939714 # Request fanout histogram 212311680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.123574 # Request fanout histogram 212411680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.329478 # Request fanout histogram 212510576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 212611680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 2576793 87.65% 87.65% # Request fanout histogram 212711680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 362587 12.33% 99.99% # Request fanout histogram 212811680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 316 0.01% 100.00% # Request fanout histogram 212911680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::3 18 0.00% 100.00% # Request fanout histogram 213011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 213110576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 213211138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 213311138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 213411680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 2939714 # Request fanout histogram 213511680SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 4544765338 # Layer occupancy (ticks) 213610892Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 213711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) 213810576Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 213911680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 1344393906 # Layer occupancy (ticks) 214011103Snilay@cs.wisc.edusystem.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 214111680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 1911305093 # Layer occupancy (ticks) 214210726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 214311680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer2.occupancy 387758410 # Layer occupancy (ticks) 214410628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 214511680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer3.occupancy 217734513 # Layer occupancy (ticks) 214610576Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 214711680SCurtis.Dunham@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 214811680SCurtis.Dunham@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 214911680SCurtis.Dunham@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 215011680SCurtis.Dunham@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 215110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 215210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 215310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 215410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 215510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 215610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 215710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 215810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 215910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 216010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 216110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 216210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 216310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 216410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 216510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 216610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 216710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 216810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 216910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 217010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 217110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 217210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 217310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 217410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 217510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 217610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 217710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 217810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 217910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 218010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 218110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 218211680SCurtis.Dunham@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 218311680SCurtis.Dunham@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 218411680SCurtis.Dunham@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 218511680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 218611680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 218711680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 218811680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 218911680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219011680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219111680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219211680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219311680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219411680SCurtis.Dunham@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219511680SCurtis.Dunham@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219611680SCurtis.Dunham@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219711680SCurtis.Dunham@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219811680SCurtis.Dunham@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 219911680SCurtis.Dunham@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 220011680SCurtis.Dunham@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 220111680SCurtis.Dunham@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 220211680SCurtis.Dunham@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 220311680SCurtis.Dunham@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 220411680SCurtis.Dunham@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states 22058464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 220611680SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 6475 # number of quiesce instructions executed 220711680SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.hwrei 176726 # number of hwrei instructions executed 220811680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::0 62785 40.28% 40.28% # number of times we switched to this ipl 220911680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl 221011680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::22 1925 1.23% 41.60% # number of times we switched to this ipl 221111680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl 221211680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::31 90860 58.29% 100.00% # number of times we switched to this ipl 221311680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::total 155882 # number of times we switched to this ipl 221411680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::0 61770 49.18% 49.18% # number of times we switched to this ipl from a different ipl 221511680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl 221611680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::22 1925 1.53% 50.82% # number of times we switched to this ipl from a different ipl 221711680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl 221811680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::31 61589 49.04% 100.00% # number of times we switched to this ipl from a different ipl 221911680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl 222011680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_ticks::0 1862335551000 97.65% 97.65% # number of cycles we spent at this ipl 222111680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_ticks::21 64321000 0.00% 97.65% # number of cycles we spent at this ipl 222211680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_ticks::22 576343500 0.03% 97.68% # number of cycles we spent at this ipl 222311680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_ticks::30 87551500 0.00% 97.68% # number of cycles we spent at this ipl 222411680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_ticks::31 44167527000 2.32% 100.00% # number of cycles we spent at this ipl 222511680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_ticks::total 1907231294000 # number of cycles we spent at this ipl 222611680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_used::0 0.983834 # fraction of swpipl calls that actually changed the ipl 22278464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 22288464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 22298464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 223011680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_used::31 0.677845 # fraction of swpipl calls that actually changed the ipl 223111680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_used::total 0.805712 # fraction of swpipl calls that actually changed the ipl 223211680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::2 7 4.14% 4.14% # number of syscalls executed 223311680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::3 14 8.28% 12.43% # number of syscalls executed 223411680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::4 4 2.37% 14.79% # number of syscalls executed 223511680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::6 26 15.38% 30.18% # number of syscalls executed 223611680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::12 1 0.59% 30.77% # number of syscalls executed 223711680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::17 5 2.96% 33.73% # number of syscalls executed 223811680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::19 7 4.14% 37.87% # number of syscalls executed 223911680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::20 4 2.37% 40.24% # number of syscalls executed 224011680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::23 1 0.59% 40.83% # number of syscalls executed 224111680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::24 3 1.78% 42.60% # number of syscalls executed 224211680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::33 5 2.96% 45.56% # number of syscalls executed 224311680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::41 2 1.18% 46.75% # number of syscalls executed 224411680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::45 26 15.38% 62.13% # number of syscalls executed 224511680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::47 3 1.78% 63.91% # number of syscalls executed 224611680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::48 8 4.73% 68.64% # number of syscalls executed 224711680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::54 8 4.73% 73.37% # number of syscalls executed 224811680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::59 6 3.55% 76.92% # number of syscalls executed 224911680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::71 15 8.88% 85.80% # number of syscalls executed 225011680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::73 3 1.78% 87.57% # number of syscalls executed 225111680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::74 3 1.78% 89.35% # number of syscalls executed 225211680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::87 1 0.59% 89.94% # number of syscalls executed 225311680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::90 2 1.18% 91.12% # number of syscalls executed 225411680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::92 7 4.14% 95.27% # number of syscalls executed 225511680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::97 2 1.18% 96.45% # number of syscalls executed 225611680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::98 2 1.18% 97.63% # number of syscalls executed 225711680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::132 1 0.59% 98.22% # number of syscalls executed 225811680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::144 1 0.59% 98.82% # number of syscalls executed 225911680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::147 2 1.18% 100.00% # number of syscalls executed 226011680SCurtis.Dunham@arm.comsystem.cpu0.kern.syscall::total 169 # number of syscalls executed 22618464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 226211680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed 226311680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed 226411680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed 226511680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed 226611680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed 226711680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed 226811606Sandreas.sandberg@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed 226911680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::swpipl 149333 91.35% 93.61% # number of callpals executed 227011680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::rdps 5683 3.48% 97.09% # number of callpals executed 227111680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed 227211680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed 227311606Sandreas.sandberg@arm.comsystem.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed 227411680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed 227511680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::rti 4311 2.64% 99.73% # number of callpals executed 227611680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed 227711606Sandreas.sandberg@arm.comsystem.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed 227811680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::total 163475 # number of callpals executed 227911680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_switch::kernel 6664 # number of protection mode switches 228011680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_switch::user 1070 # number of protection mode switches 22818464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 228211680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_good::kernel 1070 228311680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_good::user 1070 22848464SN/Asystem.cpu0.kern.mode_good::idle 0 228511680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.160564 # fraction of useful protection mode switches 22868464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 22878983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 228811680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_switch_good::total 0.276700 # fraction of useful protection mode switches 228911680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_ticks::kernel 1905216688000 99.91% 99.91% # number of ticks spent at the given mode 229011680SCurtis.Dunham@arm.comsystem.cpu0.kern.mode_ticks::user 1682440000 0.09% 100.00% # number of ticks spent at the given mode 22918464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 229211680SCurtis.Dunham@arm.comsystem.cpu0.kern.swap_context 3350 # number of times the context was actually changed 22938464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 229411680SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 2541 # number of quiesce instructions executed 229511680SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.hwrei 62895 # number of hwrei instructions executed 229611680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_count::0 19560 37.60% 37.60% # number of times we switched to this ipl 229711680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_count::22 1924 3.70% 41.30% # number of times we switched to this ipl 229811680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl 229911680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_count::31 30244 58.14% 100.00% # number of times we switched to this ipl 230011680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_count::total 52021 # number of times we switched to this ipl 230111680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_good::0 19198 47.61% 47.61% # number of times we switched to this ipl from a different ipl 230211680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_good::22 1924 4.77% 52.38% # number of times we switched to this ipl from a different ipl 230311680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl 230411680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_good::31 18906 46.89% 100.00% # number of times we switched to this ipl from a different ipl 230511680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_good::total 40321 # number of times we switched to this ipl from a different ipl 230611680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_ticks::0 1872948111000 98.19% 98.19% # number of cycles we spent at this ipl 230711680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_ticks::22 564456500 0.03% 98.22% # number of cycles we spent at this ipl 230811680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_ticks::30 141435000 0.01% 98.22% # number of cycles we spent at this ipl 230911680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_ticks::31 33894599000 1.78% 100.00% # number of cycles we spent at this ipl 231011680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_ticks::total 1907548601500 # number of cycles we spent at this ipl 231111680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_used::0 0.981493 # fraction of swpipl calls that actually changed the ipl 23128464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 23138464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 231411680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_used::31 0.625116 # fraction of swpipl calls that actually changed the ipl 231511680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_used::total 0.775091 # fraction of swpipl calls that actually changed the ipl 231611680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::2 1 0.64% 0.64% # number of syscalls executed 231711680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::3 16 10.19% 10.83% # number of syscalls executed 231811680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::6 16 10.19% 21.02% # number of syscalls executed 231911680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::15 1 0.64% 21.66% # number of syscalls executed 232011680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::17 10 6.37% 28.03% # number of syscalls executed 232111680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::19 3 1.91% 29.94% # number of syscalls executed 232211680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::20 2 1.27% 31.21% # number of syscalls executed 232311680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::23 3 1.91% 33.12% # number of syscalls executed 232411680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::24 3 1.91% 35.03% # number of syscalls executed 232511680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::33 6 3.82% 38.85% # number of syscalls executed 232611680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::45 28 17.83% 56.69% # number of syscalls executed 232711680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::47 3 1.91% 58.60% # number of syscalls executed 232811680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::48 2 1.27% 59.87% # number of syscalls executed 232911680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::54 2 1.27% 61.15% # number of syscalls executed 233011680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::58 1 0.64% 61.78% # number of syscalls executed 233111680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::59 1 0.64% 62.42% # number of syscalls executed 233211680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::71 39 24.84% 87.26% # number of syscalls executed 233311680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::74 13 8.28% 95.54% # number of syscalls executed 233411680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::90 1 0.64% 96.18% # number of syscalls executed 233511680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::92 2 1.27% 97.45% # number of syscalls executed 233611680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::132 3 1.91% 99.36% # number of syscalls executed 233711680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::144 1 0.64% 100.00% # number of syscalls executed 233811680SCurtis.Dunham@arm.comsystem.cpu1.kern.syscall::total 157 # number of syscalls executed 23398464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 234011680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed 234111606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 234211606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 234311680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed 234411680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed 234511680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed 234611680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::swpipl 46558 85.31% 87.92% # number of callpals executed 234711680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::rdps 3077 5.64% 93.55% # number of callpals executed 234811680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed 234911680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrusp 6 0.01% 93.57% # number of callpals executed 235011680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed 235111680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed 235211680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::rti 3246 5.95% 99.52% # number of callpals executed 235311680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed 235411606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed 23558464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 235611680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::total 54577 # number of callpals executed 235711680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch::kernel 1699 # number of protection mode switches 235811680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch::user 669 # number of protection mode switches 235911680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch::idle 2429 # number of protection mode switches 236011680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_good::kernel 888 236111680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_good::user 669 236211680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_good::idle 219 236311680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.522660 # fraction of useful protection mode switches 23648464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 236511680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.090161 # fraction of useful protection mode switches 236611680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch_good::total 0.370231 # fraction of useful protection mode switches 236711680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_ticks::kernel 5315508000 0.28% 0.28% # number of ticks spent at the given mode 236811680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_ticks::user 1058693000 0.06% 0.33% # number of ticks spent at the given mode 236911680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_ticks::idle 1901174392500 99.67% 100.00% # number of ticks spent at the given mode 237011680SCurtis.Dunham@arm.comsystem.cpu1.kern.swap_context 1229 # number of times the context was actually changed 23715703SN/A 23725703SN/A---------- End Simulation Statistics ---------- 2373