xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.907672                       # Number of seconds simulated
sim_ticks                                1907672102500                       # Number of ticks simulated
final_tick                               1907672102500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 159928                       # Simulator instruction rate (inst/s)
host_op_rate                                   159928                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5430263290                       # Simulator tick rate (ticks/s)
host_mem_usage                                 337712                       # Number of bytes of host memory used
host_seconds                                   351.30                       # Real time elapsed on the host
sim_insts                                    56183395                       # Number of instructions simulated
sim_ops                                      56183395                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst           861632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24651584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           117952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           582656                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26214784                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       861632                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       117952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          979584                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7845056                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7845056                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13463                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            385181                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1843                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9104                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                409606                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          122579                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122579                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              451667                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12922338                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               61830                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              305428                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13741766                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         451667                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          61830                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             513497                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4112371                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4112371                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4112371                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             451667                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12922338                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              61830                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             305428                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17854137                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        409606                       # Number of read requests accepted
system.physmem.writeReqs                       122579                       # Number of write requests accepted
system.physmem.readBursts                      409606                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     122579                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26206336                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8448                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7843200                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26214784                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7845056                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      132                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               26087                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25986                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25681                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25351                       # Per bank write bursts
system.physmem.perBankRdBursts::4               24681                       # Per bank write bursts
system.physmem.perBankRdBursts::5               24934                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25045                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25140                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25540                       # Per bank write bursts
system.physmem.perBankRdBursts::9               26037                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25956                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25606                       # Per bank write bursts
system.physmem.perBankRdBursts::12              26142                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25795                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25668                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25825                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8182                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8217                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8055                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7694                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7332                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7389                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7497                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6907                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7336                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7821                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7658                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7295                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7753                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7589                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7825                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8000                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
system.physmem.totGap                    1907667754500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  409606                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 122579                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    317389                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     37968                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     29326                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     24690                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        78                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     9224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6026                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64695                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      526.308617                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     319.463735                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     416.737705                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14846     22.95%     22.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11278     17.43%     40.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5774      8.92%     49.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2666      4.12%     53.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2483      3.84%     57.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1468      2.27%     59.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1658      2.56%     62.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1459      2.26%     64.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        23063     35.65%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64695                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5527                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        74.082685                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2821.240872                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5524     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5527                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5527                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.172969                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.909622                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.446069                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4919     89.00%     89.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              36      0.65%     89.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             243      4.40%     94.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              19      0.34%     94.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55               5      0.09%     94.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              15      0.27%     94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              14      0.25%     95.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79               2      0.04%     95.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              36      0.65%     95.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              13      0.24%     95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            182      3.29%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             3      0.05%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             2      0.04%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             2      0.04%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             4      0.07%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             3      0.05%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             5      0.09%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             4      0.07%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             1      0.02%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             2      0.04%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             2      0.04%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             1      0.02%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             1      0.02%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231            12      0.22%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5527                       # Writes before turning the bus around for reads
system.physmem.totQLat                     3957301251                       # Total ticks spent queuing
system.physmem.totMemAccLat               11634938751                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2047370000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9664.35                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28414.35                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.74                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.11                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.74                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.78                       # Average write queue length when enqueuing
system.physmem.readRowHits                     368811                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     98518                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.07                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.37                       # Row buffer hit rate for writes
system.physmem.avgGap                      3584595.12                       # Average gap between requests
system.physmem.pageHitRate                      87.84                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  244392120                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  133348875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1582659000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                397049040                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           124599742800                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            57755737350                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1093939329000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1278652258185                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.268952                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1819699135250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     63701300000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     24270006000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  244702080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  133518000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1611238200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                397074960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           124599742800                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            57480963435                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1094180367000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1278647606475                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.266509                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1820097449251                       # Time in different power states
system.physmem_1.memoryStateTime::REF     63701300000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     23871705749                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups               18486901                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         15748793                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           541835                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            11639433                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5170762                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            44.424518                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                1045004                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             41208                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        5538250                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits            525213                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         5013037                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       248456                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                    10388247                       # DTB read hits
system.cpu0.dtb.read_misses                     39745                       # DTB read misses
system.cpu0.dtb.read_acv                          614                       # DTB read access violations
system.cpu0.dtb.read_accesses                  666259                       # DTB read accesses
system.cpu0.dtb.write_hits                    6304219                       # DTB write hits
system.cpu0.dtb.write_misses                     9494                       # DTB write misses
system.cpu0.dtb.write_acv                         419                       # DTB write access violations
system.cpu0.dtb.write_accesses                 221498                       # DTB write accesses
system.cpu0.dtb.data_hits                    16692466                       # DTB hits
system.cpu0.dtb.data_misses                     49239                       # DTB misses
system.cpu0.dtb.data_acv                         1033                       # DTB access violations
system.cpu0.dtb.data_accesses                  887757                       # DTB accesses
system.cpu0.itb.fetch_hits                    1498511                       # ITB hits
system.cpu0.itb.fetch_misses                     7842                       # ITB misses
system.cpu0.itb.fetch_acv                         715                       # ITB acv
system.cpu0.itb.fetch_accesses                1506353                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numPwrStateTransitions              12731                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         6366                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    290215354.618913                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   443182270.048279                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows            4      0.06%      0.06% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         6362     99.94%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           6366                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON    60161154996                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847510947504                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       120328672                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          28758768                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      80605672                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   18486901                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6740979                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     84470777                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1538724                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                        99                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               28344                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       156668                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       425628                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          282                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  9251036                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               365043                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         114609928                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.703304                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.035053                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                99708886     87.00%     87.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  974143      0.85%     87.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1998972      1.74%     89.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  868407      0.76%     90.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2758687      2.41%     92.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  641235      0.56%     93.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  755467      0.66%     93.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  978409      0.85%     94.83% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 5925722      5.17%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           114609928                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.153637                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.669879                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                23115734                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             79187494                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9649471                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1920435                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                736793                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              689182                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                33223                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              69733339                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               101960                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                736793                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                24053074                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               52045501                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      18448869                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10567955                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              8757734                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              66954427                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents               200777                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2040075                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                234878                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               4698433                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           45085797                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             80572701                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        80419250                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           143477                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             36303569                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8782228                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1592248                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        261178                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 13101083                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10872978                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6724173                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1603556                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1060240                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  59089633                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            2074933                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 57153011                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            84826                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10861661                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      4738821                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1447538                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    114609928                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.498674                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.243633                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           91405720     79.75%     79.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            9883367      8.62%     88.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4163005      3.63%     92.01% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2977529      2.60%     94.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            3083312      2.69%     97.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1549770      1.35%     98.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1029487      0.90%     99.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             389877      0.34%     99.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             127861      0.11%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      114609928                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 177461     15.95%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     15.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                577417     51.89%     67.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               357940     32.17%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3316      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             38903396     68.07%     68.07% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               60002      0.10%     68.18% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.18% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              28431      0.05%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1656      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            10881663     19.04%     87.27% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6404122     11.21%     98.48% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            870425      1.52%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              57153011                       # Type of FU issued
system.cpu0.iq.rate                          0.474974                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1112818                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.019471                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         229452003                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         71724793                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     55161872                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             661591                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            320309                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       299753                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              57905331                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 357182                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          649944                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2311061                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3974                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        19354                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       772397                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18463                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       400325                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                736793                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               48901711                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               778245                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           65010536                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           175759                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10872978                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6724173                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1839088                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 42617                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               533932                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         19354                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        209386                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       582195                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              791581                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             56370431                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             10457447                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           782580                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3845970                       # number of nop insts executed
system.cpu0.iew.exec_refs                    16790279                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8937296                       # Number of branches executed
system.cpu0.iew.exec_stores                   6332832                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.468470                       # Inst execution rate
system.cpu0.iew.wb_sent                      55678100                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     55461625                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 28192926                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 39039520                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.460918                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.722164                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       11448425                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         627395                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           706831                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    112623597                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.474128                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.409611                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     93749029     83.24%     83.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7554104      6.71%     89.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4011836      3.56%     93.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2145505      1.91%     95.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1663134      1.48%     96.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       616876      0.55%     97.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       455080      0.40%     97.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       507934      0.45%     98.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1920099      1.70%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    112623597                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            53398017                       # Number of instructions committed
system.cpu0.commit.committedOps              53398017                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14513693                       # Number of memory references committed
system.cpu0.commit.loads                      8561917                       # Number of loads committed
system.cpu0.commit.membars                     214579                       # Number of memory barriers committed
system.cpu0.commit.branches                   8068022                       # Number of branches committed
system.cpu0.commit.fp_insts                    288973                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 49410509                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              696168                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass      3098426      5.80%      5.80% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        34606705     64.81%     70.61% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          58588      0.11%     70.72% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.72% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd         27960      0.05%     70.77% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.77% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.77% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.77% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv          1656      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.78% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        8776496     16.44%     87.21% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       5957761     11.16%     98.37% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess       870425      1.63%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         53398017                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1920099                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   175358628                       # The number of ROB reads
system.cpu0.rob.rob_writes                  131681344                       # The number of ROB writes
system.cpu0.timesIdled                         541437                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        5718744                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3694399415                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   50302904                       # Number of Instructions Simulated
system.cpu0.committedOps                     50302904                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              2.392082                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.392082                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.418046                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.418046                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                73576817                       # number of integer regfile reads
system.cpu0.int_regfile_writes               40321383                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   142542                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  152983                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1859375                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                873240                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          1336574                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.845930                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11809421                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1336976                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             8.832934                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         26822500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.845930                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.987980                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.987980                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          399                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         62763513                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        62763513                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data      7501117                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7501117                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3904271                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3904271                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       200075                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       200075                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       202804                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       202804                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11405388                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11405388                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11405388                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11405388                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1695209                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1695209                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1829361                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1829361                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22067                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22067                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          927                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          927                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3524570                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3524570                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3524570                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3524570                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40549578500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  40549578500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  77276130293                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  77276130293                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    333041000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    333041000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      6753500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      6753500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 117825708793                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 117825708793                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 117825708793                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 117825708793                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      9196326                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      9196326                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5733632                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5733632                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       222142                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       222142                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       203731                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       203731                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     14929958                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14929958                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     14929958                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14929958                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.184335                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.184335                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.319058                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.319058                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.099337                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.099337                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004550                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004550                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.236074                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.236074                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.236074                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.236074                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23920.105721                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 23920.105721                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42242.143728                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42242.143728                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15092.264467                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15092.264467                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7285.329018                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7285.329018                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33429.810954                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33429.810954                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33429.810954                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33429.810954                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      4313991                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         8795                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           119168                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            132                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    36.200918                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    66.628788                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       791920                       # number of writebacks
system.cpu0.dcache.writebacks::total           791920                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       639925                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       639925                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1556053                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1556053                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         6507                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         6507                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2195978                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2195978                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2195978                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2195978                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1055284                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1055284                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       273308                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       273308                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15560                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15560                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          926                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          926                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1328592                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1328592                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1328592                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1328592                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7032                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7032                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data         9755                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total         9755                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        16787                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        16787                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  30284931500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  30284931500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  12180596213                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12180596213                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    192236000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    192236000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      5827500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      5827500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  42465527713                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  42465527713                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  42465527713                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  42465527713                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1566422000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1566422000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1566422000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1566422000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.114751                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.114751                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.047668                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.047668                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.070045                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.070045                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004545                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004545                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.088988                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.088988                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.088988                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.088988                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28698.370770                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28698.370770                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44567.287503                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44567.287503                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12354.498715                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12354.498715                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6293.196544                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6293.196544                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31962.805521                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31962.805521                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31962.805521                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31962.805521                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222756.257110                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222756.257110                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93311.610175                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93311.610175                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1014611                       # number of replacements
system.cpu0.icache.tags.tagsinuse          509.545427                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            8173897                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1015123                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             8.052125                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      28452447500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.545427                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995206                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.995206                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         10266395                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        10266395                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst      8173897                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        8173897                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      8173897                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         8173897                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      8173897                       # number of overall hits
system.cpu0.icache.overall_hits::total        8173897                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1077136                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1077136                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1077136                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1077136                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1077136                       # number of overall misses
system.cpu0.icache.overall_misses::total      1077136                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  15255278493                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  15255278493                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  15255278493                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  15255278493                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  15255278493                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  15255278493                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      9251033                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      9251033                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      9251033                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      9251033                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      9251033                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      9251033                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116434                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.116434                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116434                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.116434                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116434                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.116434                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14162.815553                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14162.815553                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14162.815553                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14162.815553                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14162.815553                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14162.815553                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         5826                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              231                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.220779                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1014611                       # number of writebacks
system.cpu0.icache.writebacks::total          1014611                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        61774                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        61774                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        61774                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        61774                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        61774                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        61774                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1015362                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1015362                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1015362                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1015362                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1015362                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1015362                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13566878495                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  13566878495                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13566878495                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  13566878495                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13566878495                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  13566878495                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.109757                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.109757                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.109757                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.109757                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.109757                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.109757                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13361.617330                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13361.617330                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13361.617330                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13361.617330                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13361.617330                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13361.617330                       # average overall mshr miss latency
system.cpu1.branchPred.lookups                2716012                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2349135                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            64284                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             1339574                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 486642                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            36.328116                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 131116                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              4300                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups         740387                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits            107863                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses          632524                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        18463                       # Number of mispredicted indirect branches.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1491854                       # DTB read hits
system.cpu1.dtb.read_misses                     11707                       # DTB read misses
system.cpu1.dtb.read_acv                           49                       # DTB read access violations
system.cpu1.dtb.read_accesses                  336889                       # DTB read accesses
system.cpu1.dtb.write_hits                     824931                       # DTB write hits
system.cpu1.dtb.write_misses                     2806                       # DTB write misses
system.cpu1.dtb.write_acv                          46                       # DTB write access violations
system.cpu1.dtb.write_accesses                 126281                       # DTB write accesses
system.cpu1.dtb.data_hits                     2316785                       # DTB hits
system.cpu1.dtb.data_misses                     14513                       # DTB misses
system.cpu1.dtb.data_acv                           95                       # DTB access violations
system.cpu1.dtb.data_accesses                  463170                       # DTB accesses
system.cpu1.itb.fetch_hits                     477856                       # ITB hits
system.cpu1.itb.fetch_misses                     2662                       # ITB misses
system.cpu1.itb.fetch_acv                          96                       # ITB acv
system.cpu1.itb.fetch_accesses                 480518                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numPwrStateTransitions               4646                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2323                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    818936669.177787                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   339506423.560652                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         2323    100.00%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value       400000                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value    975573000                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2323                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON     5282220000                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1902389882500                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                        10566764                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           3825216                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      10675597                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    2716012                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches            725621                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      5983543                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 229964                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles               23815                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        51735                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        41039                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           40                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1221851                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                48225                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          10040370                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.063267                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.470833                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                 8168289     81.35%     81.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  102687      1.02%     82.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  210133      2.09%     84.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  146343      1.46%     85.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  249317      2.48%     88.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   97935      0.98%     89.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  113554      1.13%     90.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                   71548      0.71%     91.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  880564      8.77%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            10040370                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.257033                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.010300                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 3212898                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              5233388                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1306839                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               176592                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                110652                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved               87490                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 4477                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts               8611500                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                14236                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                110652                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 3332108                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 534859                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       3861101                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1363516                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               838132                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts               8128723                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  840                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 81504                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 20811                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents                431912                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands            5442265                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups              9792683                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups         9760108                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            27875                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              4220598                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1221659                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            323796                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         24055                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1462372                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1548375                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores             895151                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           190303                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          111620                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   7151730                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             356002                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  6823456                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            19520                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1627236                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       806919                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        274884                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     10040370                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.679602                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.404814                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0            7219551     71.91%     71.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1226248     12.21%     84.12% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             523144      5.21%     89.33% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             383300      3.82%     93.15% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             329501      3.28%     96.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             173963      1.73%     98.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             102712      1.02%     99.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              58679      0.58%     99.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              23272      0.23%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       10040370                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  25321     11.84%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     11.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                118979     55.64%     67.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                69548     32.52%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3973      0.06%      0.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              4192346     61.44%     61.50% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               10770      0.16%     61.66% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10332      0.15%     61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1986      0.03%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1560504     22.87%     84.71% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite             845461     12.39%     97.10% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            198084      2.90%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               6823456                       # Type of FU issued
system.cpu1.iq.rate                          0.645747                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     213848                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.031340                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          23830038                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes          9093503                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      6518367                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              90611                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             45521                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        43008                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               6985974                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  47357                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           77493                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       335188                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          932                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         4197                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       122462                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          439                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        72925                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                110652                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 347034                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               152695                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts            7850434                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            37055                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1548375                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts              895151                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            329794                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  4928                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               146829                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          4197                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         25483                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        92224                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              117707                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              6707770                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1507715                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           115685                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       342702                       # number of nop insts executed
system.cpu1.iew.exec_refs                     2339108                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                  982956                       # Number of branches executed
system.cpu1.iew.exec_stores                    831393                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.634799                       # Inst execution rate
system.cpu1.iew.wb_sent                       6597173                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      6561375                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  3197425                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  4464974                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.620945                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.716113                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts        1594434                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls          81118                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           100274                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples      9755465                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.627758                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.585985                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0      7484983     76.73%     76.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1079374     11.06%     87.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       367183      3.76%     91.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       234920      2.41%     93.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       168491      1.73%     95.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        74517      0.76%     96.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        76064      0.78%     97.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        56824      0.58%     97.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       213109      2.18%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total      9755465                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             6124073                       # Number of instructions committed
system.cpu1.commit.committedOps               6124073                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       1985876                       # Number of memory references committed
system.cpu1.commit.loads                      1213187                       # Number of loads committed
system.cpu1.commit.membars                      22586                       # Number of memory barriers committed
system.cpu1.commit.branches                    866488                       # Number of branches committed
system.cpu1.commit.fp_insts                     41227                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  5722327                       # Number of committed integer instructions.
system.cpu1.commit.function_calls               95129                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass       247554      4.04%      4.04% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu         3646853     59.55%     63.59% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          10597      0.17%     63.76% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     63.76% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd         10326      0.17%     63.93% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     63.93% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     63.93% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     63.93% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv          1986      0.03%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.97% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        1235773     20.18%     84.14% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite        772900     12.62%     96.77% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess       198084      3.23%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total          6124073                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               213109                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                    17170417                       # The number of ROB reads
system.cpu1.rob.rob_writes                   15719262                       # The number of ROB writes
system.cpu1.timesIdled                          71397                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         526394                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3804777442                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    5880491                       # Number of Instructions Simulated
system.cpu1.committedOps                      5880491                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.796919                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.796919                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.556508                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.556508                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                 8685381                       # number of integer regfile reads
system.cpu1.int_regfile_writes                4740732                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    27201                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   25643                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 310247                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                141917                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements            65099                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          463.722972                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            1848833                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs            65611                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.178705                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     1879972526500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   463.722972                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.905709                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.905709                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses          8556411                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses         8556411                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      1222356                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1222356                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       588321                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        588321                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        17437                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        17437                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        16296                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        16296                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      1810677                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1810677                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      1810677                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1810677                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       112363                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       112363                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       161965                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       161965                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1793                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1793                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          891                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          891                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       274328                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        274328                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       274328                       # number of overall misses
system.cpu1.dcache.overall_misses::total       274328                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1482127500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1482127500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   7331574147                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   7331574147                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     19537500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     19537500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6718500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      6718500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data        34500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total        34500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   8813701647                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   8813701647                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   8813701647                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   8813701647                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1334719                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1334719                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data       750286                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       750286                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        19230                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        19230                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        17187                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        17187                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      2085005                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      2085005                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      2085005                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      2085005                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.084185                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.084185                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.215871                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.215871                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.093240                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.093240                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.051842                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.051842                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.131572                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.131572                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.131572                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.131572                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13190.529801                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13190.529801                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 45266.410317                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 45266.410317                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10896.542108                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10896.542108                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7540.404040                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7540.404040                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32128.334137                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 32128.334137                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32128.334137                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 32128.334137                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       454264                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets          482                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs            15527                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets             10                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    29.256392                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    48.200000                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks        38456                       # number of writebacks
system.cpu1.dcache.writebacks::total            38456                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        66033                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        66033                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       137281                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       137281                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          379                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          379                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       203314                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       203314                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       203314                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       203314                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        46330                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        46330                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        24684                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        24684                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1414                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1414                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          891                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          891                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data        71014                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total        71014                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data        71014                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total        71014                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          162                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total          162                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2639                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2639                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         2801                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         2801                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    590183000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    590183000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1153615997                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1153615997                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     13566500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     13566500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5828500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5828500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data        33500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total        33500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1743798997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   1743798997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1743798997                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   1743798997                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     32350500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     32350500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     32350500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total     32350500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.034711                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.034711                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032899                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032899                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.073531                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.073531                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.051842                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.051842                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034059                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.034059                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034059                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.034059                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12738.679042                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12738.679042                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46735.375020                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46735.375020                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  9594.413013                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9594.413013                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  6541.526375                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  6541.526375                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24555.707283                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24555.707283                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24555.707283                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24555.707283                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199694.444444                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 199694.444444                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11549.625134                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11549.625134                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           129926                       # number of replacements
system.cpu1.icache.tags.tagsinuse          466.448190                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            1084325                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           130435                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             8.313144                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1880575078500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   466.448190                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.911032                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.911032                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          419                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          1352346                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         1352346                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst      1084325                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1084325                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1084325                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1084325                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1084325                       # number of overall hits
system.cpu1.icache.overall_hits::total        1084325                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       137526                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       137526                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       137526                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        137526                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       137526                       # number of overall misses
system.cpu1.icache.overall_misses::total       137526                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1969078999                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   1969078999                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   1969078999                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   1969078999                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   1969078999                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   1969078999                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1221851                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1221851                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1221851                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1221851                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1221851                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1221851                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.112555                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.112555                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.112555                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.112555                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.112555                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.112555                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14317.867160                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14317.867160                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14317.867160                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14317.867160                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14317.867160                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14317.867160                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          342                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               30                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.400000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       129926                       # number of writebacks
system.cpu1.icache.writebacks::total           129926                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7031                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         7031                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         7031                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         7031                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         7031                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         7031                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       130495                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       130495                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       130495                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       130495                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       130495                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       130495                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1753458499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   1753458499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1753458499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   1753458499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1753458499                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   1753458499                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.106801                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.106801                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.106801                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.106801                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.106801                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.106801                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13436.978421                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13436.978421                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13436.978421                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13436.978421                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13436.978421                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13436.978421                       # average overall mshr miss latency
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                 7367                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7367                       # Transaction distribution
system.iobus.trans_dist::WriteReq               53946                       # Transaction distribution
system.iobus.trans_dist::WriteResp              53946                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10580                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        39176                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  122626                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        42320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        68530                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2730138                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             10859000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               821000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              178000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            14076000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2828000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             6060001                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               90500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           216164058                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            26782000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                41693                       # number of replacements
system.iocache.tags.tagsinuse                0.508375                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41709                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1712300354000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.508375                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.031773                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.031773                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21862383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21862383                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858655675                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4858655675                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   4880518058                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4880518058                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   4880518058                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4880518058                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126372.156069                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126372.156069                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116929.526256                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 116929.526256                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 116968.677244                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 116968.677244                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 116968.677244                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 116968.677244                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13212383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13212383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778666661                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2778666661                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   2791879044                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2791879044                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   2791879044                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2791879044                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76372.156069                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76372.156069                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.031695                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.031695                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66911.421067                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 66911.421067                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66911.421067                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 66911.421067                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   344445                       # number of replacements
system.l2c.tags.tagsinuse                65257.633522                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4040340                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   409472                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     9.867195                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               7589084000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   53236.660660                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5305.017555                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6468.149046                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      210.708528                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       37.097733                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.812327                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.080948                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.098696                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003215                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000566                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995752                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65027                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         3644                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2937                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5880                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52328                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.992233                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 38778519                       # Number of tag accesses
system.l2c.tags.data_accesses                38778519                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       830376                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          830376                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks       866904                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total          866904                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data             177                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              78                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 255                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            93                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            26                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               119                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           167638                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            13954                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               181592                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       1001682                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        128599                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1130281                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       778846                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        41539                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           820385                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst             1001682                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              946484                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              128599                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               55493                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2132258                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst            1001682                       # number of overall hits
system.l2c.overall_hits::cpu0.data             946484                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             128599                       # number of overall hits
system.l2c.overall_hits::cpu1.data              55493                       # number of overall hits
system.l2c.overall_hits::total                2132258                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          2505                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           627                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3132                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           74                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          102                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             176                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         111923                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8380                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             120303                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        13465                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         1860                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           15325                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       273663                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          829                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         274492                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst             13465                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            385586                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1860                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9209                       # number of demand (read+write) misses
system.l2c.demand_misses::total                410120                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13465                       # number of overall misses
system.l2c.overall_misses::cpu0.data           385586                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1860                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9209                       # number of overall misses
system.l2c.overall_misses::total               410120                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      1461500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1509000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2970500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       588500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        59000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       647500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9993512000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    942928000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10936440000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1136019500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    157980000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1293999500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  20211623000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data     77550000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  20289173000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1136019500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  30205135000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    157980000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1020478000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     32519612500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1136019500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  30205135000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    157980000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1020478000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    32519612500                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       830376                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       830376                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks       866904                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total       866904                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2682                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          705                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3387                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          167                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          128                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           295                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       279561                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        22334                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           301895                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      1015147                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       130459                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1145606                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      1052509                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        42368                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1094877                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst         1015147                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1332070                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          130459                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           64702                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2542378                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        1015147                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1332070                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         130459                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          64702                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2542378                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.934004                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.889362                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.924712                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.443114                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.796875                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.596610                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.400353                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.375213                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.398493                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.013264                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.014257                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.013377                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.260010                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019567                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.250706                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.289464                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.014257                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.142329                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.161314                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.289464                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.014257                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.142329                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.161314                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   583.433134                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2406.698565                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   948.435504                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7952.702703                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   578.431373                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3678.977273                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89289.172020                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112521.241050                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 90907.458667                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84368.325288                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84935.483871                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 84437.161501                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73855.884793                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93546.441496                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 73915.352724                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 84368.325288                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 78335.663121                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84935.483871                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 110813.117602                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 79292.920365                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 84368.325288                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 78335.663121                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84935.483871                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 110813.117602                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 79292.920365                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               81059                       # number of writebacks
system.l2c.writebacks::total                    81059                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           17                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           17                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 17                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                17                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2505                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          627                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3132                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           74                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          102                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          176                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       111923                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8380                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        120303                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13465                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1843                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        15308                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       273663                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          829                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       274492                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13465                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       385586                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1843                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9209                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           410103                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13465                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       385586                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1843                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9209                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          410103                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7032                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data          162                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total         7194                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data         9755                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2639                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        12394                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        16787                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         2801                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        19588                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     50228500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     12653000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     62881500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1467500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2009000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      3476500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   8874280004                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    859128000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9733408004                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1001369001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    138309001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1139678002                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17481138002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     69259501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  17550397503                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1001369001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  26355418006                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    138309001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    928387501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  28423483509                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1001369001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  26355418006                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    138309001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    928387501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  28423483509                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1478504000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     30323500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1508827500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1478504000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data     30323500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   1508827500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.934004                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.889362                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.924712                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.443114                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.796875                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.596610                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.400353                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.375213                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.398493                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.013264                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014127                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013362                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.260010                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019567                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.250706                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013264                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.289464                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014127                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.142329                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.161307                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013264                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.289464                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014127                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.142329                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.161307                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20051.297405                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20180.223285                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20077.107280                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19831.081081                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19696.078431                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19752.840909                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79289.154186                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 102521.241050                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 80907.442075                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74368.288229                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75045.578405                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74449.830285                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63878.339425                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83545.839566                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63937.737723                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74368.288229                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68351.594731                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75045.578405                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 100813.063416                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69308.157973                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74368.288229                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68351.594731                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75045.578405                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 100813.063416                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69308.157973                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210253.697383                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187182.098765                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209734.153461                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 88074.343242                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10825.955016                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 77028.154993                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        844318                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       393480                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          433                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq                7194                       # Transaction distribution
system.membus.trans_dist::ReadResp             297120                       # Transaction distribution
system.membus.trans_dist::WriteReq              12394                       # Transaction distribution
system.membus.trans_dist::WriteResp             12394                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       122579                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262673                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             5556                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           1697                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            120271                       # Transaction distribution
system.membus.trans_dist::ReadExResp           120125                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        289973                       # Transaction distribution
system.membus.trans_dist::BadAddressError           47                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39176                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1170427                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           94                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1209697                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83433                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83433                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1293130                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        68530                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31401600                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31470130                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                34128370                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             4361                       # Total snoops (count)
system.membus.snoopTraffic                      28480                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            478637                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.001444                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.037968                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  477946     99.86%     99.86% # Request fanout histogram
system.membus.snoop_fanout::1                     691      0.14%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              478637                       # Request fanout histogram
system.membus.reqLayer0.occupancy            34935499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1350989532                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               59500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2172548749                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             925113                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      5110475                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2554732                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       342217                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           1055                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          987                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq               7194                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2261145                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             12394                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            12394                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       911435                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1144537                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          834683                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            5633                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          1816                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           7449                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp            1                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           302973                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          302973                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1145857                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1108145                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError           47                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq          240                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3045120                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4050284                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       390880                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       209583                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7695867                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    129904512                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    135990364                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     16664640                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side      6622614                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              289182130                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          363206                       # Total snoops (count)
system.toL2Bus.snoopTraffic                   6121792                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          2928698                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.120181                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.325532                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2577056     87.99%     87.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 351320     12.00%     99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    312      0.01%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                     10      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2928698                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4546181919                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           291385                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1524803969                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        2026499354                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         197300876                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         108970290                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6366                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    197565                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   70781     40.59%     40.59% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.08%     40.66% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1927      1.10%     41.77% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                     20      0.01%     41.78% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 101534     58.22%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              174393                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    69444     49.27%     49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1927      1.37%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                      20      0.01%     50.74% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   69424     49.26%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               140946                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1863377945500     97.69%     97.69% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               65817500      0.00%     97.70% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              580544500      0.03%     97.73% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               11361000      0.00%     97.73% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            43328343000      2.27%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1907364011500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981111                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.683751                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.808209                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.76%      3.76% # number of syscalls executed
system.cpu0.kern.syscall::3                        18      8.45%     12.21% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.88%     14.08% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     15.02%     29.11% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.47%     29.58% # number of syscalls executed
system.cpu0.kern.syscall::17                        8      3.76%     33.33% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.69%     38.03% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.82%     40.85% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.47%     41.31% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.41%     42.72% # number of syscalls executed
system.cpu0.kern.syscall::33                        6      2.82%     45.54% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.94%     46.48% # number of syscalls executed
system.cpu0.kern.syscall::45                       33     15.49%     61.97% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.41%     63.38% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.69%     68.08% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.69%     72.77% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.47%     73.24% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.82%     76.06% # number of syscalls executed
system.cpu0.kern.syscall::71                       21      9.86%     85.92% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.41%     87.32% # number of syscalls executed
system.cpu0.kern.syscall::74                        5      2.35%     89.67% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.47%     90.14% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.41%     91.55% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.23%     95.77% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.94%     96.71% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.94%     97.65% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.47%     98.12% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.94%     99.06% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.94%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   213                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  120      0.07%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3815      2.08%      2.15% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.18% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.18% # number of callpals executed
system.cpu0.kern.callpal::swpipl               167656     91.61%     93.80% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6177      3.38%     97.17% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     2      0.00%     97.17% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     97.18% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.18% # number of callpals executed
system.cpu0.kern.callpal::rti                    4658      2.55%     99.72% # number of callpals executed
system.cpu0.kern.callpal::callsys                 369      0.20%     99.93% # number of callpals executed
system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                183007                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7158                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1253                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1253                      
system.cpu0.kern.mode_good::user                 1253                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.175049                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.297943                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1905453819000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1901068000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3816                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2323                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     40320                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   10930     33.84%     33.84% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1925      5.96%     39.80% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    120      0.37%     40.18% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  19320     59.82%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               32295                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    10890     45.94%     45.94% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1925      8.12%     54.06% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     120      0.51%     54.57% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   10770     45.43%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                23705                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1876314481500     98.36%     98.36% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              564739500      0.03%     98.39% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               58247500      0.00%     98.39% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            30733817000      1.61%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1907671285500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.996340                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.557453                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.734015                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        12     10.62%     10.62% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      8.85%     19.47% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.88%     20.35% # number of syscalls executed
system.cpu1.kern.syscall::17                        7      6.19%     26.55% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.65%     29.20% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.65%     31.86% # number of syscalls executed
system.cpu1.kern.syscall::33                        5      4.42%     36.28% # number of syscalls executed
system.cpu1.kern.syscall::45                       21     18.58%     54.87% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.65%     57.52% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.88%     58.41% # number of syscalls executed
system.cpu1.kern.syscall::71                       33     29.20%     87.61% # number of syscalls executed
system.cpu1.kern.syscall::74                       11      9.73%     97.35% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.65%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   113                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                   20      0.06%      0.06% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  449      1.34%      1.41% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      1.42% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.44% # number of callpals executed
system.cpu1.kern.callpal::swpipl                27672     82.56%     84.00% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2585      7.71%     91.71% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.71% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     5      0.01%     91.73% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     91.74% # number of callpals executed
system.cpu1.kern.callpal::rti                    2577      7.69%     99.42% # number of callpals executed
system.cpu1.kern.callpal::callsys                 148      0.44%     99.87% # number of callpals executed
system.cpu1.kern.callpal::imb                      44      0.13%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 33518                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              911                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                493                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2088                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                538                      
system.cpu1.kern.mode_good::user                  493                      
system.cpu1.kern.mode_good::idle                   45                      
system.cpu1.kern.mode_switch_good::kernel     0.590560                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.021552                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.308133                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        2257888000      0.12%      0.12% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           790670500      0.04%      0.16% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1904622719000     99.84%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     450                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------