stats.txt revision 10726
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 1.904438 # Number of seconds simulated 410726Sandreas.hansson@arm.comsim_ticks 1904437574000 # Number of ticks simulated 510726Sandreas.hansson@arm.comfinal_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710726Sandreas.hansson@arm.comhost_inst_rate 150033 # Simulator instruction rate (inst/s) 810726Sandreas.hansson@arm.comhost_op_rate 150033 # Simulator op (including micro ops) rate (op/s) 910726Sandreas.hansson@arm.comhost_tick_rate 5049661741 # Simulator tick rate (ticks/s) 1010726Sandreas.hansson@arm.comhost_mem_usage 379720 # Number of bytes of host memory used 1110726Sandreas.hansson@arm.comhost_seconds 377.14 # Real time elapsed on the host 1210726Sandreas.hansson@arm.comsim_insts 56583768 # Number of instructions simulated 1310726Sandreas.hansson@arm.comsim_ops 56583768 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory 1710726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory 1810726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory 1910726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory 2010576Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2110726Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 26394240 # Number of bytes read from this memory 2210726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory 2310726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory 2410726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory 2510726Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory 2610726Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7983616 # Number of bytes written to this memory 2710726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory 2810726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory 2910726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory 3010726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory 3110576Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3210726Sandreas.hansson@arm.comsystem.physmem.num_reads::total 412410 # Number of read requests responded to by this memory 3310726Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory 3410726Sandreas.hansson@arm.comsystem.physmem.num_writes::total 124744 # Number of write requests responded to by this memory 3510726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s) 3610726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s) 3710726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) 3810726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s) 3910726Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) 4010726Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s) 4110726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s) 4210726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) 4310726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s) 4410726Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s) 4510726Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s) 4610726Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s) 4710726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s) 4810726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s) 4910726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) 5010726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s) 5110726Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) 5210726Sandreas.hansson@arm.comsystem.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s) 5310726Sandreas.hansson@arm.comsystem.physmem.readReqs 412410 # Number of read requests accepted 5410726Sandreas.hansson@arm.comsystem.physmem.writeReqs 166296 # Number of write requests accepted 5510726Sandreas.hansson@arm.comsystem.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue 5610726Sandreas.hansson@arm.comsystem.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue 5710726Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM 5810726Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue 5910726Sandreas.hansson@arm.comsystem.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM 6010726Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side 6110726Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side 6210726Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue 6310726Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one 6410726Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write 6510726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 25681 # Per bank write bursts 6610726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 26031 # Per bank write bursts 6710726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 26262 # Per bank write bursts 6810726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25929 # Per bank write bursts 6910726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25778 # Per bank write bursts 7010726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 25597 # Per bank write bursts 7110726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 26273 # Per bank write bursts 7210726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25295 # Per bank write bursts 7310726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 25970 # Per bank write bursts 7410726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 26150 # Per bank write bursts 7510726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25721 # Per bank write bursts 7610726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25208 # Per bank write bursts 7710726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 25640 # Per bank write bursts 7810726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25768 # Per bank write bursts 7910726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25547 # Per bank write bursts 8010726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25457 # Per bank write bursts 8110726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 9358 # Per bank write bursts 8210726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 9077 # Per bank write bursts 8310726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 9200 # Per bank write bursts 8410726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 8756 # Per bank write bursts 8510726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 8419 # Per bank write bursts 8610726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 8251 # Per bank write bursts 8710726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 9072 # Per bank write bursts 8810726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 8046 # Per bank write bursts 8910726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 8692 # Per bank write bursts 9010726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 8978 # Per bank write bursts 9110726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 8574 # Per bank write bursts 9210726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 8968 # Per bank write bursts 9310726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 8555 # Per bank write bursts 9410726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 9260 # Per bank write bursts 9510726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8896 # Per bank write bursts 9610726Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 8762 # Per bank write bursts 979978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9810726Sandreas.hansson@arm.comsystem.physmem.numWrRetry 50 # Number of times write queue was full causing retry 9910726Sandreas.hansson@arm.comsystem.physmem.totGap 1904433039500 # Total gap between requests 1009978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10610726Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 412410 # Read request sizes (log2) 1079978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1089978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1099978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1109978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1119978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1129978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11310726Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 166296 # Write request sizes (log2) 11410726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see 11510726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see 11610726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see 11710726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see 11810726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see 11910726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see 12010726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 12710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 12810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 12910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 13010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 13110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 13210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 13310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 13410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 13510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13610242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16110726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see 16210726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see 16310726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see 16410726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see 16510726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see 16610726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see 16710726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see 16810726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see 16910726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see 17010726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see 17110726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see 17210726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see 17310726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see 17410726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see 17510726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see 17610726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see 17710726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see 17810726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see 17910726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see 18010726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see 18110726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see 18210726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see 18310726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see 18410726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see 18510726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see 18610726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see 18710726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see 18810726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see 18910726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see 19010726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see 19110726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see 19210726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see 19310726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see 19410726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see 19510726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see 19610726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see 19710726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see 19810726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see 19910726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see 20010726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see 20110726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see 20210726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see 20310726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see 20410726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see 20510726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see 20610726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see 20710726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see 20810726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see 20910726Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see 21010726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation 21110726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation 21210726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation 21310726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation 21410726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation 21510726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation 21610726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation 21710726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation 21810726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation 21910726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation 22010726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation 22110726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation 22210726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation 22310726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation 22410726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes 22510726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes 22610726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes 22710726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes 22810726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 22910352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 23010352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 23110726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes 23210726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads 23310726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads 23410726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads 23510726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads 23610726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads 23710726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads 23810726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads 23910726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads 24010726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads 24110726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads 24210726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads 24310726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads 24410726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads 24510726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads 24610726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads 24710726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads 24810726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads 24910726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads 25010726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads 25110726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads 25210726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads 25310726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads 25410726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads 25510726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads 25610726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads 25710726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads 25810726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads 25910726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads 26010726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads 26110726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads 26210726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads 26310726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads 26410726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads 26510726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads 26610726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads 26710726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads 26810726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads 26910726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads 27010726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads 27110726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads 27210726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads 27310726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads 27410726Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads 27510726Sandreas.hansson@arm.comsystem.physmem.totQLat 4111304500 # Total ticks spent queuing 27610726Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM 27710726Sandreas.hansson@arm.comsystem.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers 27810726Sandreas.hansson@arm.comsystem.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst 2799978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 28010726Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst 28110726Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s 28210726Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s 28310726Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s 28410726Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s 2859978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28610585Sandreas.hansson@arm.comsystem.physmem.busUtil 0.15 # Data bus utilization in percentage 28710352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 28810585Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes 28910726Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing 29010726Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing 29110726Sandreas.hansson@arm.comsystem.physmem.readRowHits 371693 # Number of row buffer hits during reads 29210726Sandreas.hansson@arm.comsystem.physmem.writeRowHits 115102 # Number of row buffer hits during writes 29310726Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads 29410726Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes 29510726Sandreas.hansson@arm.comsystem.physmem.avgGap 3290847.23 # Average gap between requests 29610726Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined 29710726Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ) 29810726Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ) 29910726Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ) 30010726Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ) 30110726Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) 30210726Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ) 30310726Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ) 30410726Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ) 30510726Sandreas.hansson@arm.comsystem.physmem_0.averagePower 670.325620 # Core power per rank (mW) 30610726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states 30710726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states 30810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30910726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states 31010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 31110726Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ) 31210726Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ) 31310726Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ) 31410726Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ) 31510726Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) 31610726Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ) 31710726Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ) 31810726Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ) 31910726Sandreas.hansson@arm.comsystem.physmem_1.averagePower 670.317995 # Core power per rank (mW) 32010726Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states 32110726Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states 32210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 32310726Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states 32410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 32510726Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 16050181 # Number of BP lookups 32610726Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted 32710726Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect 32810726Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups 32910726Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits 3309481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33110726Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage 33210726Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target. 33310726Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions. 33410576Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3358464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 3368464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 3378464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 3388464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 33910726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9185685 # DTB read hits 34010726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 31794 # DTB read misses 34110726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_acv 464 # DTB read access violations 34210726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 674724 # DTB read accesses 34310726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5856177 # DTB write hits 34410726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 6642 # DTB write misses 34510726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 308 # DTB write access violations 34610726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 220970 # DTB write accesses 34710726Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15041862 # DTB hits 34810726Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 38436 # DTB misses 34910726Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 772 # DTB access violations 35010726Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 895694 # DTB accesses 35110726Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 1413849 # ITB hits 35210726Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 27924 # ITB misses 35310726Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_acv 522 # ITB acv 35410726Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 1441773 # ITB accesses 3558464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 3568464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 3578464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 3588464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 3598464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 3608464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 3618464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 3628464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 3638464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 3648464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 3658464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 3668464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 36710726Sandreas.hansson@arm.comsystem.cpu0.numCycles 115311619 # number of cpu cycles simulated 3688464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3698464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 37010726Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss 37110726Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed 37210726Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered 37310726Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken 37410726Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked 37510726Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing 37610726Sandreas.hansson@arm.comsystem.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb 37710726Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 37810726Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps 37910726Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions 38010726Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR 38110726Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched 38210726Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed 38310726Sandreas.hansson@arm.comsystem.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 38410726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total) 38510726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total) 38610726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total) 3878464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 38810726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total) 38910726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total) 39010726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total) 39110726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total) 39210726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total) 39310726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total) 39410726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total) 39510726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total) 39610726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total) 3978464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3988464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3998464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 40010726Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total) 40110726Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle 40210726Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle 40310726Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle 40410726Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked 40510726Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running 40610726Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking 40710726Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing 40810726Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch 40910726Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction 41010726Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode 41110726Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode 41210726Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing 41310726Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle 41410726Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking 41510726Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst 41610726Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running 41710726Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking 41810726Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename 41910726Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full 42010726Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full 42110726Sandreas.hansson@arm.comsystem.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full 42210726Sandreas.hansson@arm.comsystem.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full 42310726Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed 42410726Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made 42510726Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups 42610726Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups 42710726Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed 42810726Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing 42910726Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed 43010726Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed 43110726Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer 43210726Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit. 43310726Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit. 43410726Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads. 43510726Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores. 43610726Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec) 43710726Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ 43810726Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued 43910726Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued 44010726Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 6322079 # Number of squashed instructions iterated over during squash; mainly for profiling 44110726Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph 44210726Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed 44310726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle 44410726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle 44510726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle 4468464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 44710726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle 44810726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle 44910726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle 45010726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle 45110726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle 45210726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle 45310726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle 45410726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle 45510726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle 4568464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4578464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4588464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 45910726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle 4608464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 46110726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available 46210726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available 46310726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available 46410726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available 46510726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available 46610726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available 46710726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available 46810726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available 46910726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available 47010726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available 47110726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available 47210726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available 47310726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available 47410726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available 47510726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available 47610726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available 47710726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available 47810726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available 47910726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available 48010726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available 48110726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available 48210726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available 48310726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available 48410726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available 48510726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available 48610726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available 48710726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available 48810726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available 48910726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available 49010726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available 49110726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available 4928464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4938464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 49410726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued 49510726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued 49610726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued 49710726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued 49810726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued 49910726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued 50010726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued 50110726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued 50210726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued 50310726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued 50410726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued 50510726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued 50610726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued 50710726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued 50810726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued 50910726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued 51010726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued 51110726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued 51210726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued 51310726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued 51410726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued 51510726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued 51610726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued 51710726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued 51810726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued 51910726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued 52010726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued 52110726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued 52210726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued 52310726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued 52410726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued 52510726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued 52610726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued 5278464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 52810726Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued 52910726Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.453068 # Inst issue rate 53010726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested 53110726Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst) 53210726Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads 53310726Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 61059123 # Number of integer instruction queue writes 53410726Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses 53510726Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads 53610726Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 278076 # Number of floating instruction queue writes 53710726Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses 53810726Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses 53910726Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses 54010726Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores 5418464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 54210726Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed 54310726Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed 54410726Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations 54510726Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed 5468464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5478464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 54810726Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled 54910726Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked 5508464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 55110726Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing 55210726Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking 55310726Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking 55410726Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ 55510726Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch 55610726Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions 55710726Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions 55810726Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions 55910726Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall 56010726Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall 56110726Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations 56210726Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly 56310726Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly 56410726Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute 56510726Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions 56610726Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed 56710726Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute 5688464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 56910726Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 3391780 # number of nop insts executed 57010726Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed 57110726Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 8225133 # Number of branches executed 57210726Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 5876205 # Number of stores executed 57310726Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.448685 # Inst execution rate 57410726Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit 57510726Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back 57610726Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 26435135 # num instructions producing a value 57710726Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value 5788464SN/Asystem.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 57910726Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle 58010726Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back 5818464SN/Asystem.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 58210726Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit 58310726Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards 58410726Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted 58510726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle 58610726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle 58710726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle 5888241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 58910726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle 59010726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle 59110726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle 59210726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle 59310726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle 59410726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle 59510726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle 59610726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle 59710726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle 5988241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5998241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6008241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 60110726Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle 60210726Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 51332073 # Number of instructions committed 60310726Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed 6048241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 60510726Sandreas.hansson@arm.comsystem.cpu0.commit.refs 13832347 # Number of memory references committed 60610726Sandreas.hansson@arm.comsystem.cpu0.commit.loads 8208434 # Number of loads committed 60710726Sandreas.hansson@arm.comsystem.cpu0.commit.membars 200823 # Number of memory barriers committed 60810726Sandreas.hansson@arm.comsystem.cpu0.commit.branches 7767218 # Number of branches committed 60910726Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions. 61010726Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 47526784 # Number of committed integer instructions. 61110726Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 660195 # Number of function calls committed. 61210726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction 61310726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction 61410726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction 61510726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction 61610726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction 61710726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction 61810726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction 61910726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction 62010726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction 62110726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction 62210726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction 62310726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction 62410726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction 62510726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction 62610726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction 62710726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction 62810726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction 62910726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction 63010726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction 63110726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction 63210726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction 63310726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction 63410726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction 63510726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction 63610726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction 63710726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction 63810726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction 63910726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction 64010726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction 64110726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction 64210726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction 64310726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction 64410726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction 64510220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 64610726Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction 64710726Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached 6488464SN/Asystem.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 64910726Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 165216916 # The number of ROB reads 65010726Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 117798939 # The number of ROB writes 65110726Sandreas.hansson@arm.comsystem.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself 65210726Sandreas.hansson@arm.comsystem.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling 65310726Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 65410726Sandreas.hansson@arm.comsystem.cpu0.committedInsts 48375955 # Number of Instructions Simulated 65510726Sandreas.hansson@arm.comsystem.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated 65610726Sandreas.hansson@arm.comsystem.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction 65710726Sandreas.hansson@arm.comsystem.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads 65810726Sandreas.hansson@arm.comsystem.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle 65910726Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads 66010726Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 67964697 # number of integer regfile reads 66110726Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 37032803 # number of integer regfile writes 66210726Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 135608 # number of floating regfile reads 66310726Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 136877 # number of floating regfile writes 66410726Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads 66510726Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 821150 # number of misc regfile writes 66610726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1283357 # number of replacements 66710726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use 66810726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks. 66910726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks. 67010726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks. 67110726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. 67210726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor 67310726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy 67410726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy 67510726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id 67610726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id 67710726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id 67810726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses 67910726Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses 68010726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits 68110726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits 68210726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits 68310726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits 68410726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits 68510726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits 68610726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits 68710726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits 68810726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits 68910726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits 69010726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits 69110726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10231407 # number of overall hits 69210726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses 69310726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses 69410726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses 69510726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses 69610726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses 69710726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses 69810726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses 69910726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses 70010726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses 70110726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses 70210726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses 70310726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 3310446 # number of overall misses 70410726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles 70510726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles 70610726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles 70710726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles 70810726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles 70910726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles 71010726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles 71110726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles 71210726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles 71310726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles 71410726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles 71510726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles 71610726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses) 71710726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses) 71810726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses) 71910726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses) 72010726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses) 72110726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses) 72210726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses) 72310726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses) 72410726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses 72510726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses 72610726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses 72710726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses 72810726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses 72910726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses 73010726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses 73110726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses 73210726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses 73310726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses 73410726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses 73510726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses 73610726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses 73710726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses 73810726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses 73910726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses 74010726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency 74110726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency 74210726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency 74310726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency 74410726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency 74510726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency 74610726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency 74710726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency 74810726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency 74910726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency 75010726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency 75110726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency 75210726Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked 75310726Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked 75410726Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked 75510628Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked 75610726Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked 75710726Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked 7588464SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 7598464SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 76010726Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks 76110726Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 752753 # number of writebacks 76210726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits 76310726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits 76410726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits 76510726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits 76610726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits 76710726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits 76810726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits 76910726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits 77010726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits 77110726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits 77210726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses 77310726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses 77410726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses 77510726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses 77610726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses 77710726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses 77810726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses 77910726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses 78010726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses 78110726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses 78210726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses 78310726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses 78410726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles 78510726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles 78610726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles 78710726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles 78810726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles 78910726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles 79010726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles 79110726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles 79210726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 40869593877 # number of demand (read+write) MSHR miss cycles 79310726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 40869593877 # number of demand (read+write) MSHR miss cycles 79410726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 40869593877 # number of overall MSHR miss cycles 79510726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 40869593877 # number of overall MSHR miss cycles 79610726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1464167000 # number of ReadReq MSHR uncacheable cycles 79710726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1464167000 # number of ReadReq MSHR uncacheable cycles 79810726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129748498 # number of WriteReq MSHR uncacheable cycles 79910726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2129748498 # number of WriteReq MSHR uncacheable cycles 80010726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3593915498 # number of overall MSHR uncacheable cycles 80110726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 3593915498 # number of overall MSHR uncacheable cycles 80210726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125567 # mshr miss rate for ReadReq accesses 80310726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125567 # mshr miss rate for ReadReq accesses 80410726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048051 # mshr miss rate for WriteReq accesses 80510726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048051 # mshr miss rate for WriteReq accesses 80610726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086139 # mshr miss rate for LoadLockedReq accesses 80710726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086139 # mshr miss rate for LoadLockedReq accesses 80810726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012925 # mshr miss rate for StoreCondReq accesses 80910726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012925 # mshr miss rate for StoreCondReq accesses 81010726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for demand accesses 81110726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.094555 # mshr miss rate for demand accesses 81210726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for overall accesses 81310726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.094555 # mshr miss rate for overall accesses 81410726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747 # average ReadReq mshr miss latency 81510726Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747 # average ReadReq mshr miss latency 81610726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464 # average WriteReq mshr miss latency 81710726Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464 # average WriteReq mshr miss latency 81810726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency 81910726Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency 82010726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency 82110726Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency 82210726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency 82310726Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency 82410726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency 82510726Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency 8268835SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 8279055Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 8288835SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 8299055Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 8308835SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 8319055Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 8328464SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 83310726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 911417 # number of replacements 83410726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use 83510726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. 83610726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. 83710726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. 83810726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. 83910726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor 84010726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.994958 # Average percentage of cache occupancy 84110726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.994958 # Average percentage of cache occupancy 84210726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84310726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 84410726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 84510726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 9022750 # Number of tag accesses 84610726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 9022750 # Number of data accesses 84710726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 7153262 # number of ReadReq hits 84810726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 7153262 # number of ReadReq hits 84910726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 7153262 # number of demand (read+write) hits 85010726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 7153262 # number of demand (read+write) hits 85110726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 7153262 # number of overall hits 85210726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 7153262 # number of overall hits 85310726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 957376 # number of ReadReq misses 85410726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 957376 # number of ReadReq misses 85510726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 957376 # number of demand (read+write) misses 85610726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 957376 # number of demand (read+write) misses 85710726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 957376 # number of overall misses 85810726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 957376 # number of overall misses 85910726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13452406105 # number of ReadReq miss cycles 86010726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 13452406105 # number of ReadReq miss cycles 86110726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 13452406105 # number of demand (read+write) miss cycles 86210726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 13452406105 # number of demand (read+write) miss cycles 86310726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 13452406105 # number of overall miss cycles 86410726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 13452406105 # number of overall miss cycles 86510726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 8110638 # number of ReadReq accesses(hits+misses) 86610726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 8110638 # number of ReadReq accesses(hits+misses) 86710726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 8110638 # number of demand (read+write) accesses 86810726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 8110638 # number of demand (read+write) accesses 86910726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 8110638 # number of overall (read+write) accesses 87010726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 8110638 # number of overall (read+write) accesses 87110726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118040 # miss rate for ReadReq accesses 87210726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.118040 # miss rate for ReadReq accesses 87310726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.118040 # miss rate for demand accesses 87410726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.118040 # miss rate for demand accesses 87510726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses 87610726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses 87710726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency 87810726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency 87910726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency 88010726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency 88110726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency 88210726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency 88310726Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked 88410576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88510726Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked 88610576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 88710726Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 29.164103 # average number of cycles each access was blocked 88810576Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88910576Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 89010576Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 89110726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits 89210726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits 89310726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits 89410726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits 89510726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits 89610726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits 89710726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses 89810726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses 89910726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses 90010726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses 90110726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses 90210726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses 90310726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles 90410726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles 90510726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles 90610726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles 90710726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles 90810726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles 90910726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses 91010726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses 91110726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses 91210726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses 91310726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses 91410726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses 91510726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency 91610726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency 91710726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency 91810726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency 91910726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency 92010726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency 92110576Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 92210726Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 3445639 # Number of BP lookups 92310726Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted 92410726Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect 92510726Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups 92610726Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 836162 # Number of BTB hits 9279481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 92810726Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage 92910726Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target. 93010726Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions. 9318464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 9328464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 9338464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 9348464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 93510726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 1858276 # DTB read hits 93610726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 10905 # DTB read misses 93710726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_acv 64 # DTB read access violations 93810726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 300263 # DTB read accesses 93910726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 1193771 # DTB write hits 94010726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 2902 # DTB write misses 94110726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 104 # DTB write access violations 94210726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 125157 # DTB write accesses 94310726Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 3052047 # DTB hits 94410726Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 13807 # DTB misses 94510726Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 168 # DTB access violations 94610726Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 425420 # DTB accesses 94710726Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 529068 # ITB hits 94810726Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 7485 # ITB misses 94910726Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_acv 158 # ITB acv 95010726Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 536553 # ITB accesses 9518464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 9528464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 9538464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 9548464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 9558464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 9568464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 9578464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 9588464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 9598464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 9608464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 9618464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 9628464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 96310726Sandreas.hansson@arm.comsystem.cpu1.numCycles 14296923 # number of cpu cycles simulated 9648464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 9658464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 96610726Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss 96710726Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed 96810726Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered 96910726Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken 97010726Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked 97110726Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing 97210726Sandreas.hansson@arm.comsystem.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb 97310726Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 97410726Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps 97510726Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions 97610726Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 97710726Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched 97810726Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed 97910726Sandreas.hansson@arm.comsystem.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 98010726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total) 98110726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total) 98210726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total) 9838464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 98410726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total) 98510726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total) 98610726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total) 98710726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total) 98810726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total) 98910726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total) 99010726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total) 99110726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total) 99210726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total) 9938464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 9948464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 9958464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 99610726Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total) 99710726Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle 99810726Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle 99910726Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle 100010726Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked 100110726Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running 100210726Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking 100310726Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing 100410726Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch 100510726Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction 100610726Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode 100710726Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode 100810726Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing 100910726Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle 101010726Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking 101110726Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst 101210726Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running 101310726Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking 101410726Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename 101510726Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full 101610726Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full 101710726Sandreas.hansson@arm.comsystem.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full 101810726Sandreas.hansson@arm.comsystem.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full 101910726Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed 102010726Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made 102110726Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups 102210726Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups 102310726Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed 102410726Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing 102510726Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed 102610726Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed 102710726Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer 102810726Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit. 102910726Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit. 103010726Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads. 103110726Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores. 103210726Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec) 103310726Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ 103410726Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued 103510726Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued 103610726Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 1498950 # Number of squashed instructions iterated over during squash; mainly for profiling 103710726Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph 103810726Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed 103910726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle 104010726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle 104110726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle 10428464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 104310726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle 104410726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle 104510726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle 104610726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle 104710726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle 104810726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle 104910726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle 105010726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle 105110726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle 10528464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 10538464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 10548464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 105510726Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle 10568464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 105710726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available 105810726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available 105910726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available 106010726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available 106110726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available 106210726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available 106310726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available 106410726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available 106510726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available 106610726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available 106710726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available 106810726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available 106910726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available 107010726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available 107110726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available 107210726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available 107310726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available 107410726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available 107510726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available 107610726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available 107710726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available 107810726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available 107910726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available 108010726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available 108110726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available 108210726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available 108310726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available 108410726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available 108510726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available 108610726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available 108710726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available 10888464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 10898464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 109010726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued 109110726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued 109210726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued 109310726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued 109410726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued 109510726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued 109610726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued 109710726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued 109810726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued 109910726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued 110010726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued 110110726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued 110210726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued 110310726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued 110410726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued 110510726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued 110610726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued 110710726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued 110810726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued 110910726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued 111010726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued 111110726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued 111210726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued 111310726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued 111410726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued 111510726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued 111610726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued 111710726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued 111810726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued 111910726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued 112010726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued 112110726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued 112210726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued 11238464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 112410726Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued 112510726Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.633233 # Inst issue rate 112610726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested 112710726Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst) 112810726Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads 112910726Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 11194643 # Number of integer instruction queue writes 113010726Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses 113110726Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads 113210726Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 80450 # Number of floating instruction queue writes 113310726Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses 113410726Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses 113510726Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses 113610726Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores 11378464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 113810726Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed 113910726Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed 114010726Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations 114110726Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed 11428464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 11438464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 114410726Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled 114510726Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked 11468464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 114710726Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing 114810726Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking 114910726Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking 115010726Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ 115110726Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch 115210726Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions 115310726Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions 115410726Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions 115510726Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall 115610726Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall 115710726Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations 115810726Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly 115910726Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly 116010726Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute 116110726Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions 116210726Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed 116310726Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute 11648464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 116510726Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 503606 # number of nop insts executed 116610726Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed 116710726Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 1318456 # Number of branches executed 116810726Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 1202277 # Number of stores executed 116910726Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.624860 # Inst execution rate 117010726Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit 117110726Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back 117210726Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 4148200 # num instructions producing a value 117310726Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value 11748464SN/Asystem.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 117510726Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle 117610726Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back 11778464SN/Asystem.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 117810726Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit 117910726Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards 118010726Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted 118110726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle 118210726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle 118310726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle 11848464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 118510726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle 118610726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle 118710726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle 118810726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle 118910726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle 119010726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle 119110726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle 119210726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle 119310726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle 11948464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 11958464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 11968464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 119710726Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle 119810726Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 8615735 # Number of instructions committed 119910726Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed 12008464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 120110726Sandreas.hansson@arm.comsystem.cpu1.commit.refs 2763276 # Number of memory references committed 120210726Sandreas.hansson@arm.comsystem.cpu1.commit.loads 1626761 # Number of loads committed 120310726Sandreas.hansson@arm.comsystem.cpu1.commit.membars 39485 # Number of memory barriers committed 120410726Sandreas.hansson@arm.comsystem.cpu1.commit.branches 1225974 # Number of branches committed 120510726Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions. 120610726Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 7995429 # Number of committed integer instructions. 120710726Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 135018 # Number of function calls committed. 120810726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction 120910726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction 121010726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction 121110726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction 121210726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction 121310726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction 121410726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction 121510726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction 121610726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction 121710726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction 121810726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction 121910726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction 122010726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction 122110726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction 122210726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction 122310726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction 122410726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction 122510726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction 122610726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction 122710726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction 122810726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction 122910726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction 123010726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction 123110726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction 123210726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction 123310726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction 123410726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction 123510726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction 123610726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction 123710726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction 123810726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction 123910726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction 124010726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction 124110220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 124210726Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction 124310726Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached 12448464SN/Asystem.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 124510726Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 23176968 # The number of ROB reads 124610726Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 20704388 # The number of ROB writes 124710726Sandreas.hansson@arm.comsystem.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself 124810726Sandreas.hansson@arm.comsystem.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling 124910726Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 125010726Sandreas.hansson@arm.comsystem.cpu1.committedInsts 8207813 # Number of Instructions Simulated 125110726Sandreas.hansson@arm.comsystem.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated 125210726Sandreas.hansson@arm.comsystem.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction 125310726Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads 125410726Sandreas.hansson@arm.comsystem.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle 125510726Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads 125610726Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 11535994 # number of integer regfile reads 125710726Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 6250844 # number of integer regfile writes 125810726Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 43175 # number of floating regfile reads 125910726Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 42684 # number of floating regfile writes 126010726Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 891820 # number of misc regfile reads 126110726Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 203240 # number of misc regfile writes 126210726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 102439 # number of replacements 126310726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use 126410726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks. 126510726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks. 126610726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks. 126710726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit. 126810726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor 126910726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy 127010726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy 127110726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 127210726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id 127310726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 127410726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 127510726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 127610726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses 127710726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses 127810726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits 127910726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits 128010726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits 128110726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits 128210726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits 128310726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits 128410726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits 128510726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits 128610726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits 128710726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits 128810726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits 128910726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 2349874 # number of overall hits 129010726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses 129110726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses 129210726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses 129310726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses 129410726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses 129510726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses 129610726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses 129710726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses 129810726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses 129910726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses 130010726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses 130110726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 425658 # number of overall misses 130210726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles 130310726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles 130410726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles 130510726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles 130610726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles 130710726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles 130810726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles 130910726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles 131010726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles 131110726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles 131210726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles 131310726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles 131410726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses) 131510726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses) 131610726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses) 131710726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses) 131810726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses) 131910726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses) 132010726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses) 132110726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses) 132210726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses 132310726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses 132410726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses 132510726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses 132610726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses 132710726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses 132810726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses 132910726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses 133010726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses 133110726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses 133210726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses 133310726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses 133410726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses 133510726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses 133610726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses 133710726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses 133810726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency 133910726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency 134010726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency 134110726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency 134210726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency 134310726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency 134410726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency 134510726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency 134610726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency 134710726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency 134810726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency 134910726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency 135010726Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked 135110726Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked 135210726Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked 135310726Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked 135410726Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked 135510726Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked 13568464SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 13578464SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 135810726Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks 135910726Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 70134 # number of writebacks 136010726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits 136110726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits 136210726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits 136310726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits 136410726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits 136510726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits 136610726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits 136710726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits 136810726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits 136910726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits 137010726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses 137110726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses 137210726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses 137310726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses 137410726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses 137510726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses 137610726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses 137710726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses 137810726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses 137910726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses 138010726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses 138110726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses 138210726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles 138310726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles 138410726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles 138510726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles 138610726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles 138710726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles 138810726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles 138910726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles 139010726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles 139110726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles 139210726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles 139310726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles 139410726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles 139510726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles 139610726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles 139710726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles 139810726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles 139910726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles 140010726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses 140110726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses 140210726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses 140310726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses 140410726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses 140510726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses 140610726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses 140710726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses 140810726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses 140910726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses 141010726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses 141110726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses 141210726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency 141310726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency 141410726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency 141510726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency 141610726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency 141710726Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency 141810726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency 141910726Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency 142010726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency 142110726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency 142210726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency 142310726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency 14248835SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 14259055Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 14268835SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 14279055Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 14288835SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 14299055Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 14308464SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 143110726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 211356 # number of replacements 143210726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use 143310726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. 143410726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. 143510726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. 143610726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. 143710726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor 143810726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy 143910726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy 144010726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 144110726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id 144210726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 144310726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id 144410726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 144510726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 144610726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses 144710726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses 144810726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits 144910726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits 145010726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits 145110726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits 145210726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits 145310726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 1331062 # number of overall hits 145410726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses 145510726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses 145610726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses 145710726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses 145810726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses 145910726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 219986 # number of overall misses 146010726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles 146110726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles 146210726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles 146310726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles 146410726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles 146510726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles 146610726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses) 146710726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses) 146810726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses 146910726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses 147010726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses 147110726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses 147210726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses 147310726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses 147410726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses 147510726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses 147610726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses 147710726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses 147810726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency 147910726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency 148010726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency 148110726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency 148210726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency 148310726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency 148410726Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked 148510576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 148610726Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked 148710576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 148810726Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked 148910576Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 149010576Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 149110576Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 149210726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits 149310726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits 149410726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits 149510726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits 149610726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits 149710726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits 149810726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses 149910726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses 150010726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses 150110726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses 150210726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses 150310726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses 150410726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles 150510726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles 150610726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles 150710726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles 150810726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles 150910726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles 151010726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses 151110726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses 151210726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses 151310726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses 151410726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses 151510726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses 151610726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency 151710726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency 151810726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency 151910726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency 152010726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency 152110726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency 152210576Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 152310576Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 152410576Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 152510576Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 152610576Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 152710576Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 152810576Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 152910576Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 153010576Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 153110576Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 153210576Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 153310576Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 153410576Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 153510726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7375 # Transaction distribution 153610726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7375 # Transaction distribution 153710726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 54477 # Transaction distribution 153810726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 12925 # Transaction distribution 153910585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 154010726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes) 154110726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 154210576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 154310576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 154410726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes) 154510726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes) 154610576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 154710726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) 154810576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 154910576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 155010576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 155110576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 155210726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes) 155310726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) 155410726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) 155510726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes) 155610726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes) 155710726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 155810576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 155910576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 156010726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes) 156110726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes) 156210576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 156310726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) 156410576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 156510576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 156610576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 156710576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 156810726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes) 156910726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) 157010726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) 157110726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes) 157210726Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks) 157310576Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 157410726Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 157510576Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 157610576Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 157710576Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 157810576Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 157910576Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 158010726Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks) 158110576Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 158210726Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks) 158310576Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 158410576Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) 158510576Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 158610726Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) 158710576Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 158810576Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 158910576Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 159010576Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 159110576Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 159210576Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 159310576Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 159410726Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks) 159510576Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 159610576Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 159710576Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 159810726Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks) 159910576Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 160010726Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks) 160110576Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 160210726Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41698 # number of replacements 160310726Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use 160410576Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 160510726Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. 160610576Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 160710726Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit. 160810726Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor 160910726Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy 161010726Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy 161110576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 161210576Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 161310576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 161410726Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375570 # Number of tag accesses 161510726Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375570 # Number of data accesses 161610726Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 161710726Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 178 # number of ReadReq misses 161810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 161910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 162010726Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses 162110726Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 178 # number of demand (read+write) misses 162210726Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 178 # number of overall misses 162310726Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 178 # number of overall misses 162410726Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles 162510726Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles 162610726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles 162710726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles 162810726Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles 162910726Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles 163010726Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles 163110726Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles 163210726Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 163310726Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) 163410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 163510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 163610726Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses 163710726Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 178 # number of demand (read+write) accesses 163810726Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses 163910726Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 178 # number of overall (read+write) accesses 164010576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 164110576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 164210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 164310585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 164410576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 164510576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 164610576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 164710576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 164810726Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency 164910726Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency 165010726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency 165110726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency 165210726Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency 165310726Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency 165410726Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency 165510726Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency 165610726Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked 165710576Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 165810726Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked 165910576Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 166010726Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked 166110576Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 166210585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 166310576Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 166410585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 166510585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41520 # number of writebacks 166610726Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 166710726Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 166810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 166910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 167010726Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses 167110726Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses 167210726Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses 167310726Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses 167410726Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles 167510726Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles 167610726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles 167710726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles 167810726Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles 167910726Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles 168010726Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles 168110726Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles 168210576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 168310576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 168410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 168510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 168610576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 168710576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 168810576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 168910576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 169010726Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency 169110726Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency 169210726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency 169310726Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency 169410726Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency 169510726Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency 169610726Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency 169710726Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency 169810576Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 169910726Sandreas.hansson@arm.comsystem.l2c.tags.replacements 346915 # number of replacements 170010726Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65246.496404 # Cycle average of tags in use 170110726Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 2614060 # Total number of references to valid blocks. 170210726Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 412065 # Sample count of references to valid blocks. 170310726Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 6.343805 # Average number of references to valid blocks. 170410726Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 7589002750 # Cycle when the warmup percentage was hit. 170510726Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 53536.501359 # Average occupied blocks per requestor 170610726Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5301.488199 # Average occupied blocks per requestor 170710726Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6124.882413 # Average occupied blocks per requestor 170810726Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 215.988746 # Average occupied blocks per requestor 170910726Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 67.635688 # Average occupied blocks per requestor 171010726Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.816902 # Average percentage of cache occupancy 171110726Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.080894 # Average percentage of cache occupancy 171210726Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.093458 # Average percentage of cache occupancy 171310726Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.003296 # Average percentage of cache occupancy 171410726Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.001032 # Average percentage of cache occupancy 171510726Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.995583 # Average percentage of cache occupancy 171610726Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id 171710726Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id 171810726Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 2446 # Occupied blocks per task id 171910726Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id 172010726Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 7744 # Occupied blocks per task id 172110726Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 49345 # Occupied blocks per task id 172210726Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id 172310726Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 27379617 # Number of tag accesses 172410726Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 27379617 # Number of data accesses 172510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 898215 # number of ReadReq hits 172610726Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 742471 # number of ReadReq hits 172710726Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 210198 # number of ReadReq hits 172810726Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 63927 # number of ReadReq hits 172910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1914811 # number of ReadReq hits 173010726Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 822887 # number of Writeback hits 173110726Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 822887 # number of Writeback hits 173210726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits 173310726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 246 # number of UpgradeReq hits 173410726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 422 # number of UpgradeReq hits 173510726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 53 # number of SCUpgradeReq hits 173610726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits 173710726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits 173810726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 152332 # number of ReadExReq hits 173910726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 25116 # number of ReadExReq hits 174010726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 177448 # number of ReadExReq hits 174110726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 898215 # number of demand (read+write) hits 174210726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 894803 # number of demand (read+write) hits 174310726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 210198 # number of demand (read+write) hits 174410726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 89043 # number of demand (read+write) hits 174510726Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2092259 # number of demand (read+write) hits 174610726Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 898215 # number of overall hits 174710726Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 894803 # number of overall hits 174810726Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 210198 # number of overall hits 174910726Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 89043 # number of overall hits 175010726Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2092259 # number of overall hits 175110726Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 13731 # number of ReadReq misses 175210726Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 273058 # number of ReadReq misses 175310726Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1686 # number of ReadReq misses 175410726Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 819 # number of ReadReq misses 175510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 289294 # number of ReadReq misses 175610726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2683 # number of UpgradeReq misses 175710726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 1043 # number of UpgradeReq misses 175810726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 3726 # number of UpgradeReq misses 175910726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 349 # number of SCUpgradeReq misses 176010726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 386 # number of SCUpgradeReq misses 176110726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 735 # number of SCUpgradeReq misses 176210726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 112818 # number of ReadExReq misses 176310726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 10944 # number of ReadExReq misses 176410726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 123762 # number of ReadExReq misses 176510726Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 13731 # number of demand (read+write) misses 176610726Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 385876 # number of demand (read+write) misses 176710726Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1686 # number of demand (read+write) misses 176810726Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 11763 # number of demand (read+write) misses 176910726Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 413056 # number of demand (read+write) misses 177010726Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 13731 # number of overall misses 177110726Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 385876 # number of overall misses 177210726Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1686 # number of overall misses 177310726Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 11763 # number of overall misses 177410726Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 413056 # number of overall misses 177510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.inst 1146699750 # number of ReadReq miss cycles 177610726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.data 19948507750 # number of ReadReq miss cycles 177710726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.inst 143666750 # number of ReadReq miss cycles 177810726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.data 75193250 # number of ReadReq miss cycles 177910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::total 21314067500 # number of ReadReq miss cycles 178010726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 1596458 # number of UpgradeReq miss cycles 178110726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 5835814 # number of UpgradeReq miss cycles 178210726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 7432272 # number of UpgradeReq miss cycles 178310726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 1194963 # number of SCUpgradeReq miss cycles 178410726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 187494 # number of SCUpgradeReq miss cycles 178510726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 1382457 # number of SCUpgradeReq miss cycles 178610726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 9983790515 # number of ReadExReq miss cycles 178710726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 1229173205 # number of ReadExReq miss cycles 178810726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 11212963720 # number of ReadExReq miss cycles 178910726Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 1146699750 # number of demand (read+write) miss cycles 179010726Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 29932298265 # number of demand (read+write) miss cycles 179110726Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 143666750 # number of demand (read+write) miss cycles 179210726Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 1304366455 # number of demand (read+write) miss cycles 179310726Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 32527031220 # number of demand (read+write) miss cycles 179410726Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 1146699750 # number of overall miss cycles 179510726Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 29932298265 # number of overall miss cycles 179610726Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 143666750 # number of overall miss cycles 179710726Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 1304366455 # number of overall miss cycles 179810726Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 32527031220 # number of overall miss cycles 179910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 911946 # number of ReadReq accesses(hits+misses) 180010726Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1015529 # number of ReadReq accesses(hits+misses) 180110726Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 211884 # number of ReadReq accesses(hits+misses) 180210726Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 64746 # number of ReadReq accesses(hits+misses) 180310726Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2204105 # number of ReadReq accesses(hits+misses) 180410726Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 822887 # number of Writeback accesses(hits+misses) 180510726Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 822887 # number of Writeback accesses(hits+misses) 180610726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2859 # number of UpgradeReq accesses(hits+misses) 180710726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 1289 # number of UpgradeReq accesses(hits+misses) 180810726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 4148 # number of UpgradeReq accesses(hits+misses) 180910726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 402 # number of SCUpgradeReq accesses(hits+misses) 181010726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 416 # number of SCUpgradeReq accesses(hits+misses) 181110726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 818 # number of SCUpgradeReq accesses(hits+misses) 181210726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 265150 # number of ReadExReq accesses(hits+misses) 181310726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 36060 # number of ReadExReq accesses(hits+misses) 181410726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 301210 # number of ReadExReq accesses(hits+misses) 181510726Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 911946 # number of demand (read+write) accesses 181610726Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1280679 # number of demand (read+write) accesses 181710726Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 211884 # number of demand (read+write) accesses 181810726Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 100806 # number of demand (read+write) accesses 181910726Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2505315 # number of demand (read+write) accesses 182010726Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 911946 # number of overall (read+write) accesses 182110726Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1280679 # number of overall (read+write) accesses 182210726Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 211884 # number of overall (read+write) accesses 182310726Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 100806 # number of overall (read+write) accesses 182410726Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2505315 # number of overall (read+write) accesses 182510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.015057 # miss rate for ReadReq accesses 182610726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.268883 # miss rate for ReadReq accesses 182710726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.007957 # miss rate for ReadReq accesses 182810726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.012649 # miss rate for ReadReq accesses 182910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.131252 # miss rate for ReadReq accesses 183010726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.938440 # miss rate for UpgradeReq accesses 183110726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.809154 # miss rate for UpgradeReq accesses 183210726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.898264 # miss rate for UpgradeReq accesses 183310726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.868159 # miss rate for SCUpgradeReq accesses 183410726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.927885 # miss rate for SCUpgradeReq accesses 183510726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.898533 # miss rate for SCUpgradeReq accesses 183610726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.425487 # miss rate for ReadExReq accesses 183710726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.303494 # miss rate for ReadExReq accesses 183810726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.410883 # miss rate for ReadExReq accesses 183910726Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.015057 # miss rate for demand accesses 184010726Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.301306 # miss rate for demand accesses 184110726Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.007957 # miss rate for demand accesses 184210726Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.116689 # miss rate for demand accesses 184310726Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.164872 # miss rate for demand accesses 184410726Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.015057 # miss rate for overall accesses 184510726Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.301306 # miss rate for overall accesses 184610726Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.007957 # miss rate for overall accesses 184710726Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.116689 # miss rate for overall accesses 184810726Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.164872 # miss rate for overall accesses 184910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 83511.743500 # average ReadReq miss latency 185010726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.data 73055.935918 # average ReadReq miss latency 185110726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 85211.595492 # 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average overall miss latency 186910726Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency 187010726Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency 187110726Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency 187210726Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 78747.267247 # average overall miss latency 187310576Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 187410576Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 187510576Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 187610576Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 187710576Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 187810576Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 187910576Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 188010576Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 188110726Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 83224 # number of writebacks 188210726Sandreas.hansson@arm.comsystem.l2c.writebacks::total 83224 # number of writebacks 188310726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits 188410726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits 188510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 188610726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits 188710726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 188810726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits 188910726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 189010726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits 189110726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 189210726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits 189310726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 189410726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits 189510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.inst 13722 # number of ReadReq MSHR misses 189610726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.data 273058 # number of ReadReq MSHR misses 189710726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.inst 1677 # number of ReadReq MSHR misses 189810726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.data 818 # number of ReadReq MSHR misses 189910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::total 289275 # number of ReadReq MSHR misses 190010726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 2683 # number of UpgradeReq MSHR misses 190110726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 1043 # number of UpgradeReq MSHR misses 190210726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 3726 # number of UpgradeReq MSHR misses 190310726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 349 # number of SCUpgradeReq MSHR misses 190410726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 386 # number of SCUpgradeReq MSHR misses 190510726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 735 # number of SCUpgradeReq MSHR misses 190610726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 112818 # number of ReadExReq MSHR misses 190710726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 10944 # number of ReadExReq MSHR misses 190810726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 123762 # number of ReadExReq MSHR misses 190910726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 13722 # number of demand (read+write) MSHR misses 191010726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 385876 # number of demand (read+write) MSHR misses 191110726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 1677 # number of demand (read+write) MSHR misses 191210726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 11762 # number of demand (read+write) MSHR misses 191310726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 413037 # number of demand (read+write) MSHR misses 191410726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 13722 # number of overall MSHR misses 191510726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 385876 # number of overall MSHR misses 191610726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses 191710726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses 191810726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses 191910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles 192010726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles 192110726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles 192210726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.data 65122250 # number of ReadReq MSHR miss cycles 192310726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::total 17706943750 # number of ReadReq MSHR miss cycles 192410726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47889169 # number of UpgradeReq MSHR miss cycles 192510726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18491538 # number of UpgradeReq MSHR miss cycles 192610726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 66380707 # number of UpgradeReq MSHR miss cycles 192710726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6218348 # number of SCUpgradeReq MSHR miss cycles 192810726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6847885 # number of SCUpgradeReq MSHR miss cycles 192910726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 13066233 # number of SCUpgradeReq MSHR miss cycles 193010726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8604034485 # number of ReadExReq MSHR miss cycles 193110726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1094197795 # number of ReadExReq MSHR miss cycles 193210726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 9698232280 # number of ReadExReq MSHR miss cycles 193310726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 974652500 # number of demand (read+write) MSHR miss cycles 193410726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 25149140735 # number of demand (read+write) MSHR miss cycles 193510726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 122062750 # number of demand (read+write) MSHR miss cycles 193610726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 1159320045 # number of demand (read+write) MSHR miss cycles 193710726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 27405176030 # number of demand (read+write) MSHR miss cycles 193810726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 974652500 # number of overall MSHR miss cycles 193910726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 25149140735 # number of overall MSHR miss cycles 194010726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 122062750 # number of overall MSHR miss cycles 194110726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 1159320045 # number of overall MSHR miss cycles 194210726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 27405176030 # number of overall MSHR miss cycles 194310726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1365620000 # number of ReadReq MSHR uncacheable cycles 194410726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27118000 # number of ReadReq MSHR uncacheable cycles 194510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1392738000 # number of ReadReq MSHR uncacheable cycles 194610726Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1999167500 # number of WriteReq MSHR uncacheable cycles 194710726Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 591543000 # number of WriteReq MSHR uncacheable cycles 194810726Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 2590710500 # number of WriteReq MSHR uncacheable cycles 194910726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 3364787500 # number of overall MSHR uncacheable cycles 195010726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 618661000 # number of overall MSHR uncacheable cycles 195110726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 3983448500 # number of overall MSHR uncacheable cycles 195210726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for ReadReq accesses 195310726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268883 # mshr miss rate for ReadReq accesses 195410726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for ReadReq accesses 195510726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012634 # mshr miss rate for ReadReq accesses 195610726Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.131244 # mshr miss rate for ReadReq accesses 195710726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938440 # mshr miss rate for UpgradeReq accesses 195810726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809154 # mshr miss rate for UpgradeReq accesses 195910726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.898264 # mshr miss rate for UpgradeReq accesses 196010726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.868159 # mshr miss rate for SCUpgradeReq accesses 196110726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.927885 # mshr miss rate for SCUpgradeReq accesses 196210726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.898533 # mshr miss rate for SCUpgradeReq accesses 196310726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425487 # mshr miss rate for ReadExReq accesses 196410726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303494 # mshr miss rate for ReadExReq accesses 196510726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.410883 # mshr miss rate for ReadExReq accesses 196610726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for demand accesses 196710726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for demand accesses 196810726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for demand accesses 196910726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for demand accesses 197010726Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.164864 # mshr miss rate for demand accesses 197110726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for overall accesses 197210726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for overall accesses 197310726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for overall accesses 197410726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for overall accesses 197510726Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.164864 # mshr miss rate for overall accesses 197610726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average ReadReq mshr miss latency 197710726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60591.911792 # average ReadReq mshr miss latency 197810726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average ReadReq mshr miss latency 197910726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79611.552567 # average ReadReq mshr miss latency 198010726Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 61211.455363 # average ReadReq mshr miss latency 198110726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.112561 # average UpgradeReq mshr miss latency 198210726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17729.183126 # average UpgradeReq mshr miss latency 198310726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 17815.541331 # average UpgradeReq mshr miss latency 198410726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.616046 # average SCUpgradeReq mshr miss latency 198510726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17740.634715 # average SCUpgradeReq mshr miss latency 198610726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17777.187755 # average SCUpgradeReq mshr miss latency 198710726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76264.731559 # average ReadExReq mshr miss latency 198810726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99981.523666 # average ReadExReq mshr miss latency 198910726Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 78361.955043 # average ReadExReq mshr miss latency 199010726Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency 199110726Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency 199210726Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency 199310726Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency 199410726Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency 199510726Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency 199610726Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency 199710726Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency 199810726Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency 199910726Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency 200010576Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 200110576Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 200210576Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 200310576Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 200410576Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 200510576Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 200610576Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 200710576Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 200810576Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 200910576Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 201010726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 296650 # Transaction distribution 201110726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 296572 # Transaction distribution 201210726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 12925 # Transaction distribution 201310726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 12925 # Transaction distribution 201410726Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 124744 # Transaction distribution 201510576Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 201610576Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 201710726Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 9402 # Transaction distribution 201810726Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution 201910726Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 4742 # Transaction distribution 202010726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 123808 # Transaction distribution 202110726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 123481 # Transaction distribution 202210726Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 78 # Transaction distribution 202310726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes) 202410726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes) 202510726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) 202610726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes) 202710726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 202810726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) 202910726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) 203010726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) 203110726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) 203210726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) 203310585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 203410585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) 203510726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) 203610726Sandreas.hansson@arm.comsystem.membus.snoops 10437 # Total snoops (count) 203710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 594010 # Request fanout histogram 203810576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 203910576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 204010576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 204110576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 204210726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram 204310576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 204410576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 204510576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 204610576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 204710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 594010 # Request fanout histogram 204810726Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) 204910576Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 205010726Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) 205110576Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 205210628Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) 205310576Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 205410726Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) 205510726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 205610726Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks) 205710576Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 205810726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution 205910726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution 206010726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution 206110726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution 206210726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution 206310726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution 206410726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution 206510726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution 206610726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution 206710726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution 206810726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution 206910726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution 207010726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes) 207110726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes) 207210726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes) 207310726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) 207410726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) 207510726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) 207610726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) 207710726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) 207810726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) 207910726Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) 208010726Sandreas.hansson@arm.comsystem.toL2Bus.snoops 72565 # Total snoops (count) 208110726Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram 208210726Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram 208310726Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram 208410576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 208510576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 208610576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 208710576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 208810726Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram 208910726Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram 209010576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 209110576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 209210576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 209310726Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram 209410726Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) 209510726Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 209610726Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) 209710576Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 209810726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) 209910726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 210010726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) 210110726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 210210726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks) 210310628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 210410726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks) 210510576Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 210610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 210710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 210810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 210910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 211010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 211110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 211210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 211310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 211410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 211510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 211610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 211710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 211810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 211910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 212010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 212110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 212210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 212310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 212410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 212510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 212610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 212710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 212810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 212910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 213010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 213110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 213210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 213310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 213410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 213510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 213610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 21378464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 213810726Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed 213910726Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed 214010726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl 214110726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl 214210726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl 214310726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl 214410726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl 214510726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl 214610726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl 214710726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl 214810726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl 214910726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl 215010726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl 215110726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl 215210726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl 215310726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl 215410726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl 215510726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl 215610726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl 215710726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl 215810726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl 21598464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 21608464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 21618464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 216210726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl 216310726Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl 216410726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed 216510726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed 216610726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed 216710726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed 216810726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed 216910726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed 217010726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed 217110726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed 217210726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed 217310726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed 217410726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed 217510726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed 217610726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed 217710726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed 217810726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed 217910726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed 218010726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed 218110726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed 218210726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed 218310726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed 218410726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed 218510726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed 218610726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed 218710726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed 218810726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed 218910726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed 219010726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed 219110726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed 219210726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed 219310726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed 219410726Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::total 215 # number of syscalls executed 21958464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 219610726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed 219710726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed 219810726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed 219910726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed 220010726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed 220110726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed 220210726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed 220310726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed 220410726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed 220510726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed 220610726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed 220710726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed 220810726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed 220910726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed 221010726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed 221110726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed 221210726Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 170714 # number of callpals executed 221310726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches 221410726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1181 # number of protection mode switches 22158464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 221610726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1181 221710726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1181 22188464SN/Asystem.cpu0.kern.mode_good::idle 0 221910726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches 22208464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 22218983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 222210726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches 222310726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode 222410726Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode 22258464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 222610726Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3503 # number of times the context was actually changed 22278464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 222810726Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed 222910726Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed 223010726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl 223110726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl 223210726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl 223310726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl 223410726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl 223510726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl 223610726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl 223710726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl 223810726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl 223910726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl 224010726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl 224110726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl 224210726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl 224310726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl 224410726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl 224510726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl 22468464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 22478464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 224810726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl 224910726Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl 225010726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed 225110726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed 225210726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed 225310726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed 225410726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed 225510726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed 225610726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed 225710726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed 225810726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed 225910726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed 226010726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed 226110726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed 226210726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed 226310726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed 226410726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed 226510726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed 226610726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed 226710726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed 226810726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed 226910726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed 227010726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed 227110726Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::total 111 # number of syscalls executed 22728464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 227310726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed 227410726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed 227510726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed 227610726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed 227710726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed 227810726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed 227910726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed 228010726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed 228110726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed 228210726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed 228310726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed 228410726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed 228510726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed 228610726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed 228710726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed 22888464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 228910726Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 46904 # number of callpals executed 229010726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches 229110726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 554 # number of protection mode switches 229210726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches 229310726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 733 229410726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 554 229510726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 179 229610726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches 22978464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 229810726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches 229910726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches 230010726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode 230110726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode 230210726Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode 230310726Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 1024 # number of times the context was actually changed 23045703SN/A 23055703SN/A---------- End Simulation Statistics ---------- 2306