stats.txt revision 10220
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 310220Sandreas.hansson@arm.comsim_seconds 1.905651 # Number of seconds simulated 410220Sandreas.hansson@arm.comsim_ticks 1905651402000 # Number of ticks simulated 510220Sandreas.hansson@arm.comfinal_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 124387 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 124387 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 4179760275 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 352908 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 455.92 # Real time elapsed on the host 1210220Sandreas.hansson@arm.comsim_insts 56710998 # Number of instructions simulated 1310220Sandreas.hansson@arm.comsim_ops 56710998 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory 1710220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory 1810220Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 1910220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory 2010220Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory 2110220Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28857792 # Number of bytes read from this memory 2210220Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory 2310220Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory 2410220Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory 2510220Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory 2610220Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7816896 # Number of bytes written to this memory 2710220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory 2810220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory 2910220Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 3010220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory 3110220Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory 3210220Sandreas.hansson@arm.comsystem.physmem.num_reads::total 450903 # Number of read requests responded to by this memory 3310220Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory 3410220Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122139 # Number of write requests responded to by this memory 3510220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s) 3610220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s) 3710220Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s) 3810220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s) 3910220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s) 4010220Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s) 4110220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s) 4210220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s) 4310220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s) 4410220Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s) 4510220Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s) 4610220Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s) 4710220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s) 4810220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s) 4910220Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s) 5010220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s) 5110220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s) 5210220Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s) 5310220Sandreas.hansson@arm.comsystem.physmem.readReqs 450903 # Number of read requests accepted 5410220Sandreas.hansson@arm.comsystem.physmem.writeReqs 122139 # Number of write requests accepted 5510220Sandreas.hansson@arm.comsystem.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue 5610220Sandreas.hansson@arm.comsystem.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue 5710220Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM 5810220Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue 5910220Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM 6010220Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side 6110220Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side 6210220Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue 639978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 6410220Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write 6510220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 28020 # Per bank write bursts 6610220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 28240 # Per bank write bursts 6710220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 28746 # Per bank write bursts 6810220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 28309 # Per bank write bursts 6910220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 27973 # Per bank write bursts 7010220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 28180 # Per bank write bursts 7110220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 28116 # Per bank write bursts 7210220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 27456 # Per bank write bursts 7310220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 27700 # Per bank write bursts 7410220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 28070 # Per bank write bursts 7510220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 27744 # Per bank write bursts 7610220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 28151 # Per bank write bursts 7710220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 28476 # Per bank write bursts 7810220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 28764 # Per bank write bursts 7910220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 28477 # Per bank write bursts 8010220Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 28339 # Per bank write bursts 8110220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7807 # Per bank write bursts 8210220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7750 # Per bank write bursts 8310220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 8222 # Per bank write bursts 8410220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7743 # Per bank write bursts 8510220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7390 # Per bank write bursts 8610220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 7636 # Per bank write bursts 8710220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 7609 # Per bank write bursts 8810220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6913 # Per bank write bursts 8910220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 6944 # Per bank write bursts 9010220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 7275 # Per bank write bursts 9110220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7157 # Per bank write bursts 9210220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 7547 # Per bank write bursts 9310220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7916 # Per bank write bursts 9410220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 8234 # Per bank write bursts 9510220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8082 # Per bank write bursts 9610220Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7890 # Per bank write bursts 979978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9810220Sandreas.hansson@arm.comsystem.physmem.numWrRetry 8 # Number of times write queue was full causing retry 9910220Sandreas.hansson@arm.comsystem.physmem.totGap 1905651381000 # Total gap between requests 1009978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10610220Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 450903 # Read request sizes (log2) 1079978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1089978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1099978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1109978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1119978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1129978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11310220Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 122139 # Write request sizes (log2) 11410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see 11510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see 11610220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see 11710220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see 11810220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see 11910220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see 12010220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see 12110220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see 12210220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see 12310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see 12410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see 12510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see 12610220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see 12710220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see 12810220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see 12910220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see 13010220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see 13110220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see 13210220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see 13310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see 13410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see 13510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see 13610220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see 16210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see 16310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see 16410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see 16510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see 16610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see 16710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see 16810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see 16910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see 17010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see 17110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see 17210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see 17310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see 17410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see 17510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see 17610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see 17710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see 17810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see 17910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see 19010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see 19110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see 19210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see 19310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see 19410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see 19510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see 19610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see 19710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see 19810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see 19910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see 20010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see 20110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see 20210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see 20310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see 20410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see 20510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see 20610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see 20710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see 20810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 20910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see 21010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation 21110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation 21210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation 21310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation 21410220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation 21510220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation 21610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation 21710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation 21810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation 21910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation 22010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation 22110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation 22210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation 22310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation 22410220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes 22510220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes 22610220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes 22710220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes 22810148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 22910148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 23010148Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 23110220Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes 23210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads 23310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads 23410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads 23510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads 23610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads 23710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads 23810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads 23910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads 24010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads 24110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads 24210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads 24310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads 24410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads 24510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads 24610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads 24710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads 24810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads 24910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads 25010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads 25110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads 25210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads 25310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads 25410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads 25510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads 25610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads 25710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads 25810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads 25910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads 26010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads 26110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads 26210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads 26310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads 26410220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads 26510220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads 26610220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads 26710220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads 26810220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads 26910220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads 27010220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads 27110220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads 27210220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads 27310220Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads 27410220Sandreas.hansson@arm.comsystem.physmem.totQLat 8930594750 # Total ticks spent queuing 27510220Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM 27610220Sandreas.hansson@arm.comsystem.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers 27710220Sandreas.hansson@arm.comsystem.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst 2789978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27910220Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst 28010220Sandreas.hansson@arm.comsystem.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s 28110220Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s 28210220Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s 28310220Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s 2849978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 2859490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.15 # Data bus utilization in percentage 2869978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 2879978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28810220Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing 28910220Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing 29010220Sandreas.hansson@arm.comsystem.physmem.readRowHits 407659 # Number of row buffer hits during reads 29110220Sandreas.hansson@arm.comsystem.physmem.writeRowHits 98604 # Number of row buffer hits during writes 29210220Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads 29310220Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes 29410220Sandreas.hansson@arm.comsystem.physmem.avgGap 3325500.37 # Average gap between requests 29510220Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined 29610220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states 29710220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 63633700000 # Time in different power states 29810220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 29910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 37488657000 # Time in different power states 30010220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 30110220Sandreas.hansson@arm.comsystem.membus.throughput 19303809 # Throughput (bytes/s) 30210220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 296468 # Transaction distribution 30310220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 296393 # Transaction distribution 30410220Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 13039 # Transaction distribution 30510220Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 13039 # Transaction distribution 30610220Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 122139 # Transaction distribution 30710220Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 9699 # Transaction distribution 30810220Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution 30910220Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 4861 # Transaction distribution 31010220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 162690 # Transaction distribution 31110220Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 162297 # Transaction distribution 31210220Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 75 # Transaction distribution 31310220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes) 31410220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes) 31510220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) 31610220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes) 31710220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) 31810220Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) 31910220Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes) 32010220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes) 32110220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes) 32210220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes) 32310220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) 32410220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) 32510220Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes) 32610220Sandreas.hansson@arm.comsystem.membus.data_through_bus 36748378 # Total data (bytes) 32710220Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) 32810220Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks) 3299729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 33010220Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks) 3319729Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 33210220Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks) 3339729Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 33410220Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks) 3359729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 33610220Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks) 3379729Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 33810036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 33910220Sandreas.hansson@arm.comsystem.l2c.tags.replacements 343977 # number of replacements 34010220Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use 34110220Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 2582565 # Total number of references to valid blocks. 34210220Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks. 34310220Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks. 34410220Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit. 34510220Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor 34610220Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor 34710220Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor 34810220Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor 34910220Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor 35010220Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy 35110220Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy 35210220Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy 35310220Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy 35410220Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy 35510220Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy 35610220Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id 35710220Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id 35810220Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id 35910220Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id 36010220Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id 36110220Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id 36210220Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id 36310220Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 27108862 # Number of tag accesses 36410220Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 27108862 # Number of data accesses 36510220Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits 36610220Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits 36710220Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits 36810220Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits 36910220Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits 37010220Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits 37110220Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 822208 # number of Writeback hits 37210220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits 37310220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits 37410220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits 37510220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits 37610220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 37710220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits 37810220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits 37910220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits 38010220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits 38110220Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits 38210220Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits 38310220Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits 38410220Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits 38510220Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2062288 # number of demand (read+write) hits 38610220Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 867616 # number of overall hits 38710220Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 891053 # number of overall hits 38810220Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 210128 # number of overall hits 38910220Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 93491 # number of overall hits 39010220Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2062288 # number of overall hits 39110220Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses 39210220Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses 39310220Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses 39410220Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses 39510220Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 289117 # number of ReadReq misses 39610220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses 39710220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses 39810220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 3729 # number of UpgradeReq misses 39910220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 406 # 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number of ReadExReq miss cycles 42910220Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 1067454245 # number of demand (read+write) miss cycles 43010220Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 27275567970 # number of demand (read+write) miss cycles 43110220Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 96862500 # number of demand (read+write) miss cycles 43210220Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 674854213 # number of demand (read+write) miss cycles 43310220Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 29114738928 # number of demand (read+write) miss cycles 43410220Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 1067454245 # number of overall miss cycles 43510220Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 27275567970 # number of overall miss cycles 43610220Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles 43710220Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles 43810220Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles 43910220Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses) 44010220Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses) 44110220Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses) 44210220Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses) 44310220Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses) 44410220Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses) 44510220Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses) 44610220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses) 44710220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses) 44810220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses) 44910220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 455 # number of SCUpgradeReq accesses(hits+misses) 45010148Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 458 # number of SCUpgradeReq accesses(hits+misses) 45110220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 913 # number of SCUpgradeReq accesses(hits+misses) 45210220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 269131 # number of ReadExReq accesses(hits+misses) 45310220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 31923 # number of ReadExReq accesses(hits+misses) 45410220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 301054 # number of ReadExReq accesses(hits+misses) 45510220Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 881651 # 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miss rate for SCUpgradeReq accesses 47410220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947598 # miss rate for SCUpgradeReq accesses 47510220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.920044 # miss rate for SCUpgradeReq accesses 47610220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.426168 # miss rate for ReadExReq accesses 47710220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.198666 # miss rate for ReadExReq accesses 47810220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.402044 # miss rate for ReadExReq accesses 47910220Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.015919 # miss rate for demand accesses 48010220Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.303397 # miss rate for demand accesses 48110220Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.005857 # miss rate for demand accesses 48210220Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.067747 # 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average overall miss latency 50910220Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency 51010220Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency 51110220Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency 51210220Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 70984.895742 # average overall miss latency 5138464SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5148464SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 5158464SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 5168464SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 5178983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5188983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # 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number of UpgradeReq MSHR miss cycles 56710220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4153902 # number of SCUpgradeReq MSHR miss cycles 56810220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4341434 # number of SCUpgradeReq MSHR miss cycles 56910220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 8495336 # number of SCUpgradeReq MSHR miss cycles 57010220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7989750261 # number of ReadExReq MSHR miss cycles 57110220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 560973786 # number of ReadExReq MSHR miss cycles 57210220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 8550724047 # number of ReadExReq MSHR miss cycles 57310220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 890067005 # number of demand (read+write) MSHR miss cycles 57410220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 22463368024 # number of demand (read+write) MSHR miss cycles 57510220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 80840000 # number of demand (read+write) MSHR miss cycles 57610220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 590686287 # number of demand (read+write) MSHR miss cycles 57710220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 24024961316 # number of demand (read+write) MSHR miss cycles 57810220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 890067005 # number of overall MSHR miss cycles 57910220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 22463368024 # number of overall MSHR miss cycles 58010220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 80840000 # number of overall MSHR miss cycles 58110220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 590686287 # number of overall MSHR miss cycles 58210220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 24024961316 # number of overall MSHR miss cycles 58310220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367392500 # number of ReadReq MSHR uncacheable cycles 58410220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22035500 # number of ReadReq MSHR uncacheable cycles 58510220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1389428000 # number of ReadReq MSHR uncacheable cycles 58610220Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2022747000 # number of WriteReq MSHR uncacheable cycles 58710220Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 583651500 # number of WriteReq MSHR uncacheable cycles 58810220Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 2606398500 # number of WriteReq MSHR uncacheable cycles 58910220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 3390139500 # number of overall MSHR uncacheable cycles 59010220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 605687000 # number of overall MSHR uncacheable cycles 59110220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 3995826500 # number of overall MSHR uncacheable cycles 59210220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for ReadReq accesses 59310220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270683 # mshr miss rate for ReadReq accesses 59410220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for ReadReq accesses 59510220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006597 # mshr miss rate for ReadReq accesses 59610220Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.133140 # mshr miss rate for ReadReq accesses 59710220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940535 # mshr miss rate for UpgradeReq accesses 59810220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801822 # mshr miss rate for UpgradeReq accesses 59910220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.896610 # mshr miss rate for UpgradeReq accesses 60010220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.892308 # mshr miss rate for SCUpgradeReq accesses 60110220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947598 # mshr miss rate for SCUpgradeReq accesses 60210220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.920044 # mshr miss rate for SCUpgradeReq accesses 60310220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.426168 # mshr miss rate for ReadExReq accesses 60410220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198666 # mshr miss rate for ReadExReq accesses 60510220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.402044 # mshr miss rate for ReadExReq accesses 60610220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for demand accesses 60710220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for demand accesses 60810220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for demand accesses 60910220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for demand accesses 61010220Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.165883 # mshr miss rate for demand accesses 61110220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for overall accesses 61210220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for overall accesses 61310220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for overall accesses 61410220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for overall accesses 61510220Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.165883 # mshr miss rate for overall accesses 61610220Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average ReadReq mshr miss latency 61710220Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52940.897184 # average ReadReq mshr miss latency 61810220Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average ReadReq mshr miss latency 61910220Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65881.376940 # average ReadReq mshr miss latency 62010220Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 53525.737789 # average ReadReq mshr miss latency 62110220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.352787 # average UpgradeReq mshr miss latency 62210220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.566288 # average UpgradeReq mshr miss latency 62310220Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.457495 # average UpgradeReq mshr miss latency 62410220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10231.285714 # average SCUpgradeReq mshr miss latency 62510220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.304147 # average SCUpgradeReq mshr miss latency 62610220Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10113.495238 # average SCUpgradeReq mshr miss latency 62710220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69660.841894 # average ReadExReq mshr miss latency 62810220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 88453.766320 # average ReadExReq mshr miss latency 62910220Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 70645.538530 # average ReadExReq mshr miss latency 63010220Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency 63110220Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency 63210220Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency 63310220Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency 63410220Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency 63510220Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency 63610220Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency 63710220Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency 63810220Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency 63910220Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency 6408835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 6418835SAli.Saidi@ARM.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 6429055Ssaidi@eecs.umich.edusystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 6438835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 6448835SAli.Saidi@ARM.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 6459055Ssaidi@eecs.umich.edusystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 6468835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 6478835SAli.Saidi@ARM.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 6489055Ssaidi@eecs.umich.edusystem.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 6498464SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 65010220Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41695 # number of replacements 65110220Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.491978 # Cycle average of tags in use 6529838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 65310220Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 6549838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 65510220Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1712295759000 # Cycle when the warmup percentage was hit. 65610220Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.491978 # Average occupied blocks per requestor 65710220Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.030749 # Average percentage of cache occupancy 65810220Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.030749 # Average percentage of cache occupancy 65910036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 66010036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 66110036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 66210036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 375543 # Number of tag accesses 66310036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 375543 # Number of data accesses 6649988Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 6659988Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::total 175 # number of ReadReq misses 6668835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 6678464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 6689988Snilay@cs.wisc.edusystem.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 6699988Snilay@cs.wisc.edusystem.iocache.demand_misses::total 41727 # number of demand (read+write) misses 6709988Snilay@cs.wisc.edusystem.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 6719988Snilay@cs.wisc.edusystem.iocache.overall_misses::total 41727 # number of overall misses 67210220Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # number of ReadReq miss cycles 67310220Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21492883 # number of ReadReq miss cycles 67410220Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 12499299192 # number of WriteReq miss cycles 67510220Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 12499299192 # number of WriteReq miss cycles 67610220Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 12520792075 # number of demand (read+write) miss cycles 67710220Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 12520792075 # number of demand (read+write) miss cycles 67810220Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 12520792075 # number of overall miss cycles 67910220Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 12520792075 # number of overall miss cycles 6809988Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 6819988Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 6828835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 6838464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 6849988Snilay@cs.wisc.edusystem.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 6859988Snilay@cs.wisc.edusystem.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 6869988Snilay@cs.wisc.edusystem.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 6879988Snilay@cs.wisc.edusystem.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 6888835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 6899055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 6908835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 6919055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 6928835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 6939055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 6948835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 6959055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 69610220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286 # average ReadReq miss latency 69710220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 122816.474286 # average ReadReq miss latency 69810220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514 # average WriteReq miss latency 69910220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 300811.012514 # average WriteReq miss latency 70010220Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency 70110220Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency 70210220Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency 70310220Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency 70410220Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked 7058464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 70610220Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked 7078464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 70810220Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked 7098983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7108464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 7118464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 71210220Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 71310220Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41520 # number of writebacks 7149988Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 7159988Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 7168835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 7178835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 7189988Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses 7199988Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses 7209988Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses 7219988Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses 72210220Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles 72310220Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles 72410220Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles 72510220Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles 72610220Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles 72710220Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles 72810220Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles 72910220Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles 7308835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 7319055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 7328835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 7339055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 7348835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 7359055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 7368835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 7379055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 73810220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency 73910220Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency 74010220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency 74110220Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency 74210220Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency 74310220Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency 74410220Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency 74510220Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency 7468464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 7478464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 7488464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 7498464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 7508464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 7518464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 7528464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 7538464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 7548464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 7558464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 7568464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 7578464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 7588464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 75910220Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 12477942 # Number of BP lookups 76010220Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted 76110220Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect 76210220Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups 76310220Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits 7649481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 76510220Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage 76610220Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target. 76710220Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions. 7688464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 7698464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 7708464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 7718464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 77210220Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 8879185 # DTB read hits 77310220Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 30734 # DTB read misses 77410220Sandreas.hansson@arm.comsystem.cpu0.dtb.read_acv 556 # DTB read access violations 77510220Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 627584 # DTB read accesses 77610220Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5815647 # DTB write hits 77710220Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 8173 # DTB write misses 77810220Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 357 # DTB write access violations 77910220Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 210225 # DTB write accesses 78010220Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 14694832 # DTB hits 78110220Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 38907 # DTB misses 78210220Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 913 # DTB access violations 78310220Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 837809 # DTB accesses 78410220Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 998260 # ITB hits 78510220Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 27519 # ITB misses 78610220Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_acv 894 # ITB acv 78710220Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 1025779 # ITB accesses 7888464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 7898464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 7908464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 7918464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 7928464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 7938464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 7948464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 7958464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 7968464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 7978464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 7988464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 7998464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 80010220Sandreas.hansson@arm.comsystem.cpu0.numCycles 116074371 # number of cpu cycles simulated 8018464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 8028464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 80310220Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss 80410220Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed 80510220Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered 80610220Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken 80710220Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked 80810220Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing 80910220Sandreas.hansson@arm.comsystem.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked 81010220Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 81110220Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps 81210220Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions 81310220Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR 81410220Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched 81510220Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed 81610220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total) 81710220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total) 81810220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total) 8198464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 82010220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total) 82110220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total) 82210220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total) 82310220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total) 82410220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total) 82510220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total) 82610220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total) 82710220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total) 82810220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total) 8298464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 8308464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 8318464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 83210220Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total) 83310220Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle 83410220Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle 83510220Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle 83610220Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked 83710220Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running 83810220Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking 83910220Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing 84010220Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch 84110220Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction 84210220Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode 84310220Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode 84410220Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing 84510220Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle 84610220Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking 84710220Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst 84810220Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running 84910220Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking 85010220Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename 85110220Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full 85210220Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full 85310220Sandreas.hansson@arm.comsystem.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full 85410220Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed 85510220Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made 85610220Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups 85710220Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups 85810220Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed 85910220Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing 86010220Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed 86110220Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed 86210220Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer 86310220Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit. 86410220Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit. 86510220Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads. 86610220Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores. 86710220Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec) 86810220Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ 86910220Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued 87010220Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued 87110220Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling 87210220Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph 87310220Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed 87410220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle 87510220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle 87610220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle 8778464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 87810220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle 87910220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle 88010220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle 88110220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle 88210220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle 88310220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle 88410220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle 88510220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle 88610220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle 8878464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 8888464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 8898464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 89010220Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle 8918464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 89210220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available 89310220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available 89410220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available 89510220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available 89610220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available 89710220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available 89810220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available 89910220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available 90010220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available 90110220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available 90210220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available 90310220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available 90410220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available 90510220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available 90610220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available 90710220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available 90810220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available 90910220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available 91010220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available 91110220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available 91210220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available 91310220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available 91410220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available 91510220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available 91610220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available 91710220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available 91810220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available 91910220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available 92010220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available 92110220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available 92210220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available 9238464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 9248464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 92510220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued 92610220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued 92710220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued 92810220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued 92910220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued 93010220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued 93110220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued 93210220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued 93310220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued 93410220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued 93510220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued 93610220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued 93710220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued 93810220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued 93910220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued 94010220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued 94110220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued 94210220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued 94310220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued 94410220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued 94510220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued 94610220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued 94710220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued 94810220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued 94910220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued 95010220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued 95110220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued 95210220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued 95310220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued 95410220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued 95510220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued 95610220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued 95710220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued 9588464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 95910220Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued 96010220Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.443500 # Inst issue rate 96110220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested 96210220Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst) 96310220Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads 96410220Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes 96510220Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses 96610220Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads 96710220Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes 96810220Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses 96910220Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses 97010220Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses 97110220Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores 9728464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 97310220Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed 97410220Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed 97510220Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations 97610220Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed 9778464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 9788464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 97910220Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled 98010220Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked 9818464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 98210220Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing 98310220Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking 98410220Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking 98510220Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ 98610220Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch 98710220Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions 98810220Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions 98910220Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions 99010220Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall 99110220Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall 99210220Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations 99310220Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly 99410220Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly 99510220Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute 99610220Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions 99710220Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed 99810220Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute 9998464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 100010220Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 3229636 # number of nop insts executed 100110220Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed 100210220Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 8136394 # Number of branches executed 100310220Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 5837466 # Number of stores executed 100410220Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.440174 # Inst execution rate 100510220Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit 100610220Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back 100710220Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 25278333 # num instructions producing a value 100810220Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value 10098464SN/Asystem.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 101010220Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle 101110220Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back 10128464SN/Asystem.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 101310220Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit 101410220Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards 101510220Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted 101610220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle 101710220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle 101810220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle 10198241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 102010220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle 102110220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle 102210220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle 102310220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle 102410220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle 102510220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle 102610220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle 102710220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle 102810220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle 10298241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 10308241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 10318241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 103210220Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle 103310220Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 51248256 # Number of instructions committed 103410220Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed 10358241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 103610220Sandreas.hansson@arm.comsystem.cpu0.commit.refs 13810671 # Number of memory references committed 103710220Sandreas.hansson@arm.comsystem.cpu0.commit.loads 8171492 # Number of loads committed 103810220Sandreas.hansson@arm.comsystem.cpu0.commit.membars 199624 # Number of memory barriers committed 103910220Sandreas.hansson@arm.comsystem.cpu0.commit.branches 7741114 # Number of branches committed 104010220Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions. 104110220Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 47457125 # Number of committed integer instructions. 104210220Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 657479 # Number of function calls committed. 104310220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction 104410220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction 104510220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction 104610220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction 104710220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction 104810220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction 104910220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction 105010220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction 105110220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction 105210220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction 105310220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction 105410220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction 105510220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction 105610220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction 105710220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction 105810220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction 105910220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction 106010220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction 106110220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction 106210220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction 106310220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction 106410220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction 106510220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction 106610220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction 106710220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction 106810220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction 106910220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction 107010220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction 107110220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction 107210220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction 107310220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction 107410220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction 107510220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction 107610220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 107710220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction 107810220Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached 10798464SN/Asystem.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 108010220Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 130790454 # The number of ROB reads 108110220Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 116222813 # The number of ROB writes 108210220Sandreas.hansson@arm.comsystem.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself 108310220Sandreas.hansson@arm.comsystem.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling 108410220Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 108510220Sandreas.hansson@arm.comsystem.cpu0.committedInsts 48300626 # Number of Instructions Simulated 108610220Sandreas.hansson@arm.comsystem.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated 108710220Sandreas.hansson@arm.comsystem.cpu0.committedInsts_total 48300626 # Number of Instructions Simulated 108810220Sandreas.hansson@arm.comsystem.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction 108910220Sandreas.hansson@arm.comsystem.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads 109010220Sandreas.hansson@arm.comsystem.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle 109110220Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads 109210220Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 67219449 # number of integer regfile reads 109310220Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 36695614 # number of integer regfile writes 109410220Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 128632 # number of floating regfile reads 109510220Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 130173 # number of floating regfile writes 109610220Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads 109710220Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 820377 # number of misc regfile writes 10985703SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 10995703SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 11005703SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 11015703SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 11028464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 11038983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 11048464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 11058464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 11068983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 11078464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 11088464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 11098983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 11108464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 11118464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 11128983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 11138464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 11148464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 11158983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 11168464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 11178464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 11188983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 11198464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 11208464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 11218983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 11228464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 11238464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 11248983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 11258464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 11268983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 11278464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 11285703SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 112910220Sandreas.hansson@arm.comsystem.toL2Bus.throughput 111416521 # Throughput (bytes/s) 113010220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution 113110220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution 113210220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution 113310220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution 113410220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution 113510220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution 113610220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution 113710220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution 113810220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution 113910220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution 114010220Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution 114110220Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes) 114210220Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes) 114310220Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes) 114410220Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes) 114510220Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes) 114610220Sandreas.hansson@arm.comsystem.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes) 114710220Sandreas.hansson@arm.comsystem.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes) 114810220Sandreas.hansson@arm.comsystem.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes) 114910220Sandreas.hansson@arm.comsystem.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes) 115010220Sandreas.hansson@arm.comsystem.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes) 115110220Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 210926490 # Total data (bytes) 115210220Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes) 115310220Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks) 11549729Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 115510220Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) 11569729Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 115710220Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks) 11589729Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 115910220Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks) 11609729Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 116110220Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks) 116210148Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 116310220Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks) 116410220Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 116510220Sandreas.hansson@arm.comsystem.iobus.throughput 1435370 # Throughput (bytes/s) 116610220Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7369 # Transaction distribution 116710220Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7369 # Transaction distribution 116810220Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 54591 # Transaction distribution 116910220Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 54591 # Transaction distribution 117010220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes) 117110220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 11729729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 11739729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 11749729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 11759729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 11769729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 117710220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 11789729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 11799729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 11809729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 11819729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 118210220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes) 11839988Snilay@cs.wisc.edusystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 11849988Snilay@cs.wisc.edusystem.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 118510220Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes) 118610220Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes) 118710220Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 11889729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 11899729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 11909729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 11919729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 11929729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 119310220Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 11949729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 11959729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 11969729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 11979729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 119810220Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes) 11999988Snilay@cs.wisc.edusystem.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 12009988Snilay@cs.wisc.edusystem.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 120110220Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes) 120210220Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2735314 # Total data (bytes) 120310220Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks) 12049729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 120510220Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 12069729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 12079729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 12089729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 12099729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 12109729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 12119729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 12129729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 12139729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 12149729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 12159729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) 12169729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 121710220Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 12189729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 12199729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 12209729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 12219729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 12229729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 12239729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 12249729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 122510220Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks) 12269729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 12279729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 12289729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 122910220Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks) 12309729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 123110220Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks) 12329729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 123310220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 881127 # number of replacements 123410220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use 123510220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks. 123610220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks. 123710220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks. 123810220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit. 123910220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor 124010220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy 124110220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy 124210220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 124310220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 124410220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id 124510220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id 124610220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 124710220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 124810220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses 124910220Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses 125010220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits 125110220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits 125210220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits 125310220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits 125410220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits 125510220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 6795719 # number of overall hits 125610220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses 125710220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses 125810220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses 125910220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses 126010220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses 126110220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 926821 # number of overall misses 126210220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles 126310220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles 126410220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles 126510220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles 126610220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles 126710220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles 126810220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses) 126910220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses) 127010220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses 127110220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses 127210220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses 127310220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses 127410220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses 127510220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses 127610220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses 127710220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses 127810220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses 127910220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses 128010220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency 128110220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency 128210220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency 128310220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency 128410220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency 128510220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency 128610220Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked 128710220Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked 128810220Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked 128910148Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked 129010220Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked 129110220Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked 12928464SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 12938464SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 129410220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits 129510220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits 129610220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits 129710220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits 129810220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits 129910220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits 130010220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses 130110220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses 130210220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses 130310220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses 130410220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses 130510220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses 130610220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles 130710220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles 130810220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles 130910220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles 131010220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles 131110220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles 131210220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses 131310220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses 131410220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses 131510220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses 131610220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses 131710220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses 131810220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency 131910220Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency 132010220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency 132110220Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency 132210220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency 132310220Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency 13248464SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 132510220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1281204 # number of replacements 132610220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use 132710220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks. 132810220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks. 132910220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks. 133010220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit. 133110220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor 133210220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy 133310220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy 133410036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 133510220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 133610220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 133710220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 133810036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 133910220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses 134010220Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses 134110220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits 134210220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits 134310220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits 134410220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits 134510220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits 134610220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits 134710220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits 134810220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits 134910220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits 135010220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits 135110220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits 135210220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10126574 # number of overall hits 135310220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses 135410220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses 135510220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses 135610220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses 135710220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses 135810220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses 135910220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses 136010220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses 136110220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses 136210220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses 136310220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses 136410220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 3345621 # number of overall misses 136510220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles 136610220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles 136710220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles 136810220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles 136910220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles 137010220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles 137110220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles 137210220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles 137310220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles 137410220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles 137510220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles 137610220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles 137710220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses) 137810220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses) 137910220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses) 138010220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses) 138110220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses) 138210220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses) 138310220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses) 138410220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses) 138510220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses 138610220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses 138710220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses 138810220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses 138910220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses 139010220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses 139110220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses 139210220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses 139310220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses 139410220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses 139510220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses 139610220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses 139710220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses 139810220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses 139910220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses 140010220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses 140110220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency 140210220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency 140310220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency 140410220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency 140510220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency 140610220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency 140710220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency 140810220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency 140910220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency 141010220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency 141110220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency 141210220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency 141310220Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked 141410220Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked 141510220Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked 14169988Snilay@cs.wisc.edusystem.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 141710220Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked 141810220Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked 14198464SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 14208464SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 142110220Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks 142210220Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 754427 # number of writebacks 142310220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits 142410220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits 142510220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits 142610220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits 142710220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits 142810220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits 142910220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits 143010220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits 143110220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits 143210220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits 143310220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses 143410220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses 143510220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses 143610220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses 143710220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses 143810220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses 143910220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses 144010220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses 144110220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses 144210220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses 144310220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses 144410220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses 144510220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles 144610220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles 144710220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles 144810220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles 144910220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles 145010220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles 145110220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles 145210220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles 145310220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles 145410220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles 145510220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles 145610220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles 145710220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles 145810220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles 145910220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles 146010220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles 146110220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles 146210220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles 146310220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses 146410220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses 146510220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses 146610220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses 146710220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses 146810220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses 146910220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses 147010220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses 147110220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses 147210220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses 147310220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses 147410220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses 147510220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency 147610220Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency 147710220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency 147810220Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency 147910220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency 148010220Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency 148110220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency 148210220Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency 148310220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency 148410220Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency 148510220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency 148610220Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency 14878835SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 14889055Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 14898835SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 14909055Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 14918835SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 14929055Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 14938464SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 149410220Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 2485884 # Number of BP lookups 149510220Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted 149610220Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect 149710220Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups 149810220Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 831190 # Number of BTB hits 14999481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 150010220Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage 150110220Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target. 150210220Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions. 15038464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 15048464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 15058464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 15068464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 150710220Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 1846757 # DTB read hits 150810220Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 10485 # DTB read misses 150910220Sandreas.hansson@arm.comsystem.cpu1.dtb.read_acv 25 # DTB read access violations 151010220Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 320297 # DTB read accesses 151110220Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 1188866 # DTB write hits 151210220Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 1998 # DTB write misses 151310220Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 67 # DTB write access violations 151410220Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 130212 # DTB write accesses 151510220Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 3035623 # DTB hits 151610220Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 12483 # DTB misses 151710220Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 92 # DTB access violations 151810220Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 450509 # DTB accesses 151910220Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 420713 # ITB hits 152010220Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 6600 # ITB misses 152110220Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_acv 223 # ITB acv 152210220Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 427313 # ITB accesses 15238464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 15248464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 15258464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 15268464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 15278464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 15288464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 15298464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 15308464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 15318464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 15328464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 15338464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 15348464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 153510220Sandreas.hansson@arm.comsystem.cpu1.numCycles 14964653 # number of cpu cycles simulated 15368464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 15378464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 153810220Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss 153910220Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed 154010220Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered 154110220Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken 154210220Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked 154310220Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing 154410220Sandreas.hansson@arm.comsystem.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked 154510220Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 154610220Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps 154710220Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions 154810220Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 154910220Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched 155010220Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed 155110220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total) 155210220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total) 155310220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total) 15548464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 155510220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total) 155610220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total) 155710220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total) 155810220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total) 155910220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total) 156010220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total) 156110220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total) 156210220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total) 156310220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total) 15648464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 15658464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 15668464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 156710220Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total) 156810220Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle 156910220Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle 157010220Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle 157110220Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked 157210220Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running 157310220Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking 157410220Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing 157510220Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch 157610220Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction 157710220Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode 157810220Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode 157910220Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing 158010220Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle 158110220Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking 158210220Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst 158310220Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running 158410220Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking 158510220Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename 158610220Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full 158710220Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full 158810220Sandreas.hansson@arm.comsystem.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full 158910220Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed 159010220Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made 159110220Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups 159210220Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups 159310220Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed 159410220Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing 159510220Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed 159610220Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed 159710220Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer 159810220Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit. 159910220Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit. 160010220Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads. 160110220Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores. 160210220Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec) 160310220Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ 160410220Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued 160510220Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued 160610220Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling 160710220Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph 160810220Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed 160910220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle 161010220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle 161110220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle 16128464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 161310220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle 161410220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle 161510220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle 161610220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle 161710220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle 161810220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle 161910220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle 162010220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle 162110220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle 16228464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 16238464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 16248464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 162510220Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle 16268464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 162710220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available 162810220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available 162910220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available 163010220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available 163110220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available 163210220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available 163310220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available 163410220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available 163510220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available 163610220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available 163710220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available 163810220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available 163910220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available 164010220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available 164110220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available 164210220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available 164310220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available 164410220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available 164510220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available 164610220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available 164710220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available 164810220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available 164910220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available 165010220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available 165110220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available 165210220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available 165310220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available 165410220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available 165510220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available 165610220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available 165710220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available 16588464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 16598464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 166010220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued 166110220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued 166210220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued 166310220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued 166410220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued 166510220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued 166610220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued 166710220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued 166810220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued 166910220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued 167010220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued 167110220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued 167210220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued 167310220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued 167410220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued 167510220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued 167610220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued 167710220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued 167810220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued 167910220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued 168010220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued 168110220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued 168210220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued 168310220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued 168410220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued 168510220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued 168610220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued 168710220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued 168810220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued 168910220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued 169010220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued 169110220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued 169210220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued 16938464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 169410220Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued 169510220Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.609525 # Inst issue rate 169610220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested 169710220Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst) 169810220Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads 169910220Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes 170010220Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses 170110220Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads 170210220Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes 170310220Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses 170410220Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses 170510220Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses 170610220Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores 17078464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 170810220Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed 170910220Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed 171010220Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations 171110220Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed 17128464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 17138464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 171410220Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled 171510220Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked 17168464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 171710220Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing 171810220Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking 171910220Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking 172010220Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ 172110220Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch 172210220Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions 172310220Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions 172410220Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions 172510220Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall 172610220Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall 172710220Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations 172810220Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly 172910220Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly 173010220Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute 173110220Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions 173210220Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed 173310220Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute 17348464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 173510220Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 483081 # number of nop insts executed 173610220Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed 173710220Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 1345265 # Number of branches executed 173810220Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 1196645 # Number of stores executed 173910220Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.603549 # Inst execution rate 174010220Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit 174110220Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back 174210220Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 4203498 # num instructions producing a value 174310220Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value 17448464SN/Asystem.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 174510220Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle 174610220Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back 17478464SN/Asystem.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 174810220Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit 174910220Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards 175010220Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted 175110220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle 175210220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle 175310220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle 17548464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 175510220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle 175610220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle 175710220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle 175810220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle 175910220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle 176010220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle 176110220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle 176210220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle 176310220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle 17648464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 17658464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 17668464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 176710220Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle 176810220Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 8834118 # Number of instructions committed 176910220Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed 17708464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 177110220Sandreas.hansson@arm.comsystem.cpu1.commit.refs 2811640 # Number of memory references committed 177210220Sandreas.hansson@arm.comsystem.cpu1.commit.loads 1676136 # Number of loads committed 177310220Sandreas.hansson@arm.comsystem.cpu1.commit.membars 41495 # Number of memory barriers committed 177410220Sandreas.hansson@arm.comsystem.cpu1.commit.branches 1262292 # Number of branches committed 177510220Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions. 177610220Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 8189363 # Number of committed integer instructions. 177710220Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 139415 # Number of function calls committed. 177810220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction 177910220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction 178010220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction 178110220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction 178210220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction 178310220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction 178410220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction 178510220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction 178610220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction 178710220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction 178810220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction 178910220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction 179010220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction 179110220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction 179210220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction 179310220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction 179410220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction 179510220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction 179610220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction 179710220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction 179810220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction 179910220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction 180010220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction 180110220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction 180210220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction 180310220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction 180410220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction 180510220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction 180610220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction 180710220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction 180810220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction 180910220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction 181010220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction 181110220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 181210220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction 181310220Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached 18148464SN/Asystem.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 181510220Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 23736453 # The number of ROB reads 181610220Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 20710450 # The number of ROB writes 181710220Sandreas.hansson@arm.comsystem.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself 181810220Sandreas.hansson@arm.comsystem.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling 181910220Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 182010220Sandreas.hansson@arm.comsystem.cpu1.committedInsts 8410372 # Number of Instructions Simulated 182110220Sandreas.hansson@arm.comsystem.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated 182210220Sandreas.hansson@arm.comsystem.cpu1.committedInsts_total 8410372 # Number of Instructions Simulated 182310220Sandreas.hansson@arm.comsystem.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction 182410220Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads 182510220Sandreas.hansson@arm.comsystem.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle 182610220Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads 182710220Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 11653751 # number of integer regfile reads 182810220Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 6367365 # number of integer regfile writes 182910220Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 51509 # number of floating regfile reads 183010220Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 51143 # number of floating regfile writes 183110220Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 926936 # number of misc regfile reads 183210220Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 206554 # number of misc regfile writes 183310220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 210820 # number of replacements 183410220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use 183510220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks. 183610220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks. 183710220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks. 183810220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit. 183910220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor 184010220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy 184110220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy 184210036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 184310220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 184410036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 184510220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses 184610220Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses 184710220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits 184810220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits 184910220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits 185010220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits 185110220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits 185210220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 1201520 # number of overall hits 185310220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses 185410220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses 185510220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses 185610220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses 185710220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses 185810220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 219211 # number of overall misses 185910220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles 186010220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles 186110220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles 186210220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles 186310220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles 186410220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles 186510220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses) 186610220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses) 186710220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses 186810220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses 186910220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses 187010220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses 187110220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses 187210220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses 187310220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses 187410220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses 187510220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses 187610220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses 187710220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency 187810220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency 187910220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency 188010220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency 188110220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency 188210220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency 188310220Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked 18849568Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188510220Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked 18869568Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 188710220Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked 18889568Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 18898464SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 18908464SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 189110220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits 189210220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits 189310220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits 189410220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits 189510220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits 189610220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits 189710220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses 189810220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses 189910220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses 190010220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses 190110220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses 190210220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses 190310220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles 190410220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles 190510220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles 190610220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles 190710220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles 190810220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles 190910220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses 191010220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses 191110220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses 191210220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses 191310220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses 191410220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses 191510220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency 191610220Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency 191710220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency 191810220Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency 191910220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency 192010220Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency 19218464SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 192210220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 102235 # number of replacements 192310220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use 192410220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks. 192510220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks. 192610220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks. 192710220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit. 192810220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor 192910220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy 193010220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy 193110220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id 193210220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id 193310220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id 193410220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses 193510220Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses 193610220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits 193710220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits 193810220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits 193910220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits 194010220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits 194110220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits 194210220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits 194310220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits 194410220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits 194510220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits 194610220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits 194710220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 2412285 # number of overall hits 194810220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses 194910220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses 195010220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses 195110220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses 195210220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses 195310220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses 195410220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses 195510220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses 195610220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses 195710220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses 195810220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses 195910220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 403088 # number of overall misses 196010220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles 196110220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles 196210220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles 196310220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles 196410220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles 196510220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles 196610220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles 196710220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles 196810220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles 196910220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles 197010220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles 197110220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles 197210220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses) 197310220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses) 197410220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses) 197510220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses) 197610220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses) 197710220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses) 197810220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses) 197910220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses) 198010220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses 198110220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses 198210220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses 198310220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses 198410220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses 198510220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses 198610220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses 198710220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses 198810220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses 198910220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses 199010220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses 199110220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses 199210220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses 199310220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses 199410220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses 199510220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses 199610220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency 199710220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency 199810220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency 199910220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency 200010220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency 200110220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency 200210220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency 200310220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency 200410220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency 200510220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency 200610220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency 200710220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency 200810220Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked 20099459Ssaidi@eecs.umich.edusystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 201010220Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked 20119459Ssaidi@eecs.umich.edusystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 201210220Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked 20139459Ssaidi@eecs.umich.edusystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 20148464SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 20158464SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 201610220Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks 201710220Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 67781 # number of writebacks 201810220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits 201910220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits 202010220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits 202110220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits 202210220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits 202310220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits 202410220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits 202510220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits 202610220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits 202710220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits 202810220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses 202910220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses 203010220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses 203110220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses 203210220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses 203310220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses 203410220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses 203510220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses 203610220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses 203710220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses 203810220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses 203910220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses 204010220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles 204110220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles 204210220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles 204310220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles 204410220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles 204510220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles 204610220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles 204710220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles 204810220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles 204910220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles 205010220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles 205110220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles 205210220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles 205310220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles 205410220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles 205510220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles 205610220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles 205710220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles 205810220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses 205910220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses 206010220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses 206110220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses 206210220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses 206310220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses 206410220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses 206510220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses 206610220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses 206710220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses 206810220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses 206910220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses 207010220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency 207110220Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency 207210220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency 207310220Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency 207410220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency 207510220Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency 207610220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency 207710220Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency 207810220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency 207910220Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency 208010220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency 208110220Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency 20828835SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 20839055Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 20848835SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 20859055Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 20868835SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 20879055Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 20888464SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 20898464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 209010220Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed 209110220Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed 209210220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl 209310220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl 209410220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl 209510220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl 209610220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl 209710220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl 209810220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl 209910220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl 210010220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl 210110220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl 210210220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl 210310220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl 210410220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl 210510220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl 210610220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl 210710220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl 210810220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl 210910220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl 211010220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl 21118464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 21128464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 21138464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 211410220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl 211510220Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl 211610220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed 211710220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed 211810220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed 211910220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed 212010220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed 212110220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed 212210220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed 212310220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed 212410220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed 212510220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed 212610220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed 212710220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed 212810220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed 212910220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed 213010220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed 213110220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed 213210220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed 213310220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed 213410220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed 213510220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed 213610220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed 213710220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed 213810220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed 213910220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed 214010220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed 214110220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed 214210220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed 214310220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed 214410220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed 214510220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::total 211 # number of syscalls executed 21468464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 214710220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed 214810148Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed 214910148Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed 215010220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed 215110220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed 215210220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed 215310220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed 215410220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed 215510220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed 215610220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed 215710220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed 215810220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed 215910220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed 216010220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed 216110220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed 216210220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed 216310220Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 169959 # number of callpals executed 216410220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches 216510220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1287 # number of protection mode switches 21668464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 216710220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1286 216810220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1287 21698464SN/Asystem.cpu0.kern.mode_good::idle 0 217010220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches 21718464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 21728983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 217310220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches 217410220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode 217510220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode 21768464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 217710220Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3530 # number of times the context was actually changed 21788464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 217910220Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed 218010220Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed 218110220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl 218210220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl 218310220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl 218410220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl 218510220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl 218610220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl 218710220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl 218810220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl 218910220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl 219010220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl 219110220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl 219210220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl 219310220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl 219410220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl 219510220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl 219610220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl 21978464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 21988464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 219910220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl 220010220Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl 220110220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed 220210220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed 220310220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed 220410220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed 220510220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed 220610220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed 220710220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed 220810220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed 220910220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed 221010220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed 221110220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed 221210220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed 221310220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed 221410220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed 221510220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed 221610220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed 221710220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed 221810220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed 221910220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed 222010220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed 222110220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed 222210220Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::total 115 # number of syscalls executed 22238464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 222410220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed 222510220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed 222610220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed 222710220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed 222810220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed 222910220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed 223010220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed 223110220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed 223210220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed 223310220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed 223410220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed 223510220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed 223610220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed 223710220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed 223810220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed 22398464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 224010220Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 48076 # number of callpals executed 224110220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches 224210220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 460 # number of protection mode switches 224310220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches 224410220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 662 224510220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 460 224610220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 202 224710220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches 22488464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 224910220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches 225010220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches 225110220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode 225210220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode 225310220Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode 225410220Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 1068 # number of times the context was actually changed 22555703SN/A 22565703SN/A---------- End Simulation Statistics ---------- 2257