15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 1.910457 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 1910457097500 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 1910457097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 237868 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 237868 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 8017235800 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 340828 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 238.29 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 56682446 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 56682446 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 856512 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 24438912 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 120704 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 888384 # Number of bytes read from this memory 2110576Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 26305472 # Number of bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 856512 # Number of instructions bytes read from this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 120704 # Number of instructions bytes read from this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 977216 # Number of instructions bytes read from this memory 2611860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7909632 # Number of bytes written to this memory 2711860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7909632 # Number of bytes written to this memory 2811860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 13383 # Number of read requests responded to by this memory 2911860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 381858 # Number of read requests responded to by this memory 3011860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1886 # Number of read requests responded to by this memory 3111860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 13881 # Number of read requests responded to by this memory 3210576Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3311860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 411023 # Number of read requests responded to by this memory 3411860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 123588 # Number of write requests responded to by this memory 3511860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 123588 # Number of write requests responded to by this memory 3611860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 448328 # Total read bandwidth from this memory (bytes/s) 3711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 12792180 # Total read bandwidth from this memory (bytes/s) 3811860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 63181 # Total read bandwidth from this memory (bytes/s) 3911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 465011 # Total read bandwidth from this memory (bytes/s) 4011860Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 502 # Total read bandwidth from this memory (bytes/s) 4111860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13769203 # Total read bandwidth from this memory (bytes/s) 4211860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 448328 # Instruction read bandwidth from this memory (bytes/s) 4311860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 63181 # Instruction read bandwidth from this memory (bytes/s) 4411860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 511509 # Instruction read bandwidth from this memory (bytes/s) 4511860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4140178 # Write bandwidth from this memory (bytes/s) 4611860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4140178 # Write bandwidth from this memory (bytes/s) 4711860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4140178 # Total bandwidth to/from this memory (bytes/s) 4811860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 448328 # Total bandwidth to/from this memory (bytes/s) 4911860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 12792180 # Total bandwidth to/from this memory (bytes/s) 5011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 63181 # Total bandwidth to/from this memory (bytes/s) 5111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 465011 # Total bandwidth to/from this memory (bytes/s) 5211860Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 502 # Total bandwidth to/from this memory (bytes/s) 5311860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17909381 # Total bandwidth to/from this memory (bytes/s) 5411860Sandreas.hansson@arm.comsystem.physmem.readReqs 411023 # Number of read requests accepted 5511860Sandreas.hansson@arm.comsystem.physmem.writeReqs 123588 # Number of write requests accepted 5611860Sandreas.hansson@arm.comsystem.physmem.readBursts 411023 # Number of DRAM read bursts, including those serviced by the write queue 5711860Sandreas.hansson@arm.comsystem.physmem.writeBursts 123588 # Number of DRAM write bursts, including those merged in the write queue 5811860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 26298624 # Total number of bytes read from DRAM 5911860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue 6011860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7907712 # Total number of bytes written to DRAM 6111860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 26305472 # Total read bytes from the system interface side 6211860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7909632 # Total written bytes from the system interface side 6311860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue 6410892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 6511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 26243 # Per bank write bursts 6711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25982 # Per bank write bursts 6811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25968 # Per bank write bursts 6911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25688 # Per bank write bursts 7011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25576 # Per bank write bursts 7111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 25569 # Per bank write bursts 7211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 25629 # Per bank write bursts 7311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25342 # Per bank write bursts 7411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 25591 # Per bank write bursts 7511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25697 # Per bank write bursts 7611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25920 # Per bank write bursts 7711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25515 # Per bank write bursts 7811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 26076 # Per bank write bursts 7911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25417 # Per bank write bursts 8011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25094 # Per bank write bursts 8111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25609 # Per bank write bursts 8211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 8586 # Per bank write bursts 8311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 8089 # Per bank write bursts 8411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7939 # Per bank write bursts 8511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7426 # Per bank write bursts 8611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7272 # Per bank write bursts 8711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 7413 # Per bank write bursts 8811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 7547 # Per bank write bursts 8911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 7156 # Per bank write bursts 9011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7533 # Per bank write bursts 9111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 7641 # Per bank write bursts 9211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7810 # Per bank write bursts 9311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 7729 # Per bank write bursts 9411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 8256 # Per bank write bursts 9511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7847 # Per bank write bursts 9611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 7516 # Per bank write bursts 9711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7798 # Per bank write bursts 989978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911860Sandreas.hansson@arm.comsystem.physmem.numWrRetry 69 # Number of times write queue was full causing retry 10011860Sandreas.hansson@arm.comsystem.physmem.totGap 1910452747500 # Total gap between requests 1019978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 1069978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 411023 # Read request sizes (log2) 1089978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1099978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1109978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1119978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1129978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1139978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 123588 # Write request sizes (log2) 11511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 316637 # What read queue length does an incoming req see 11611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 38767 # What read queue length does an incoming req see 11711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 30209 # What read queue length does an incoming req see 11811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 25132 # What read queue length does an incoming req see 11911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 134 # What read queue length does an incoming req see 12011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see 12111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see 12211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 6 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 12710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 12810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 12910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 13010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 13110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 13210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 13310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 13410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 13510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 13610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13710242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1518 # What write queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2732 # What write queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 3319 # What write queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4343 # What write queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5637 # What write queue length does an incoming req see 16711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see 16811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see 16911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see 17011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see 17111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 7604 # What write queue length does an incoming req see 17211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8137 # What write queue length does an incoming req see 17311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 7914 # What write queue length does an incoming req see 17411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 7224 # What write queue length does an incoming req see 17511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7343 # What write queue length does an incoming req see 17611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 7491 # What write queue length does an incoming req see 17711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7730 # What write queue length does an incoming req see 17811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6507 # What write queue length does an incoming req see 17911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 6752 # What write queue length does an incoming req see 18011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 904 # What write queue length does an incoming req see 18111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 514 # What write queue length does an incoming req see 18211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 331 # What write queue length does an incoming req see 18311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 263 # What write queue length does an incoming req see 18411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 295 # What write queue length does an incoming req see 18511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 286 # What write queue length does an incoming req see 18611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see 18711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 315 # What write queue length does an incoming req see 18811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 288 # What write queue length does an incoming req see 18911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 326 # What write queue length does an incoming req see 19011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see 19111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 381 # What write queue length does an incoming req see 19211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 369 # What write queue length does an incoming req see 19311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 277 # What write queue length does an incoming req see 19411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 290 # What write queue length does an incoming req see 19511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 318 # What write queue length does an incoming req see 19611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 343 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see 19811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 203 # What write queue length does an incoming req see 19911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 249 # What write queue length does an incoming req see 20011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see 20111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 240 # What write queue length does an incoming req see 20211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see 20311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 310 # What write queue length does an incoming req see 20411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see 20511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 241 # What write queue length does an incoming req see 20611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 381 # What write queue length does an incoming req see 20711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 395 # What write queue length does an incoming req see 20811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 248 # What write queue length does an incoming req see 20911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 148 # What write queue length does an incoming req see 21011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see 21111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 64267 # Bytes accessed per row activation 21211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 532.249522 # Bytes accessed per row activation 21311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 325.147595 # Bytes accessed per row activation 21411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 415.887517 # Bytes accessed per row activation 21511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 14293 22.24% 22.24% # Bytes accessed per row activation 21611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 11517 17.92% 40.16% # Bytes accessed per row activation 21711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 5102 7.94% 48.10% # Bytes accessed per row activation 21811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2862 4.45% 52.55% # Bytes accessed per row activation 21911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2222 3.46% 56.01% # Bytes accessed per row activation 22011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1875 2.92% 58.93% # Bytes accessed per row activation 22111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1935 3.01% 61.94% # Bytes accessed per row activation 22211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1643 2.56% 64.49% # Bytes accessed per row activation 22311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 22818 35.51% 100.00% # Bytes accessed per row activation 22411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 64267 # Bytes accessed per row activation 22511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5506 # Reads before turning the bus around for writes 22611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 74.626952 # Reads before turning the bus around for writes 22711860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2826.578445 # Reads before turning the bus around for writes 22811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5503 99.95% 99.95% # Reads before turning the bus around for writes 22910726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 23010352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 23110352Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 23211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5506 # Reads before turning the bus around for writes 23311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5506 # Writes before turning the bus around for reads 23411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.440610 # Writes before turning the bus around for reads 23511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.769678 # Writes before turning the bus around for reads 23611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 24.128904 # Writes before turning the bus around for reads 23711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 4988 90.59% 90.59% # Writes before turning the bus around for reads 23811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 40 0.73% 91.32% # Writes before turning the bus around for reads 23911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 160 2.91% 94.22% # Writes before turning the bus around for reads 24011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 10 0.18% 94.41% # Writes before turning the bus around for reads 24111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 4 0.07% 94.48% # Writes before turning the bus around for reads 24211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 18 0.33% 94.81% # Writes before turning the bus around for reads 24311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 5 0.09% 94.90% # Writes before turning the bus around for reads 24411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 6 0.11% 95.01% # Writes before turning the bus around for reads 24511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 35 0.64% 95.64% # Writes before turning the bus around for reads 24611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 4 0.07% 95.71% # Writes before turning the bus around for reads 24711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 137 2.49% 98.20% # Writes before turning the bus around for reads 24811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 15 0.27% 98.47% # Writes before turning the bus around for reads 24911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 13 0.24% 98.71% # Writes before turning the bus around for reads 25011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads 25111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 8 0.15% 98.91% # Writes before turning the bus around for reads 25211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 3 0.05% 98.96% # Writes before turning the bus around for reads 25311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 5 0.09% 99.06% # Writes before turning the bus around for reads 25411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 3 0.05% 99.11% # Writes before turning the bus around for reads 25511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads 25611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads 25711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 9 0.16% 99.38% # Writes before turning the bus around for reads 25811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 10 0.18% 99.56% # Writes before turning the bus around for reads 25911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 9 0.16% 99.73% # Writes before turning the bus around for reads 26011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads 26111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 8 0.15% 99.89% # Writes before turning the bus around for reads 26211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 3 0.05% 99.95% # Writes before turning the bus around for reads 26311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads 26411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads 26511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5506 # Writes before turning the bus around for reads 26611860Sandreas.hansson@arm.comsystem.physmem.totQLat 8133947000 # Total ticks spent queuing 26711860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 15838622000 # Total ticks spent from burst creation until serviced by the DRAM 26811860Sandreas.hansson@arm.comsystem.physmem.totBusLat 2054580000 # Total ticks spent in databus transfers 26911860Sandreas.hansson@arm.comsystem.physmem.avgQLat 19794.67 # Average queueing delay per DRAM burst 2709978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27111860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 38544.67 # Average memory access latency per DRAM burst 27211754Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 27311754Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s 27411860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s 27511754Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s 2769978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27710892Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 27810352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 27910892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28011860Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 2.17 # Average read queue length when enqueuing 28111860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 27.12 # Average write queue length when enqueuing 28211860Sandreas.hansson@arm.comsystem.physmem.readRowHits 370641 # Number of row buffer hits during reads 28311860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 99565 # Number of row buffer hits during writes 28411860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads 28511860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 80.56 # Row buffer hit rate for writes 28611860Sandreas.hansson@arm.comsystem.physmem.avgGap 3573538.04 # Average gap between requests 28711860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 87.97 # Row buffer hit rate, read and write combined 28811860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 228629940 # Energy for activate commands per rank (pJ) 28911860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 121519695 # Energy for precharge commands per rank (pJ) 29011860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) 29111860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 320654160 # Energy for write commands per rank (pJ) 29211860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3862397760.000001 # Energy for refresh commands per rank (pJ) 29311860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 4332596790 # Energy for active background per rank (pJ) 29411860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 252811200 # Energy for precharge background per rank (pJ) 29511860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 8421848610 # Energy for active power-down per rank (pJ) 29611860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 4670504160 # Energy for precharge power-down per rank (pJ) 29711860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 449339904270 # Energy for self refresh per rank (pJ) 29811860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 473022982485 # Total energy per rank (pJ) 29911860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 247.596757 # Core power per rank (mW) 30011860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 1900281265750 # Total Idle time Per DRAM Rank 30111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 402747000 # Time in different power states 30211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1640746000 # Time in different power states 30311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 1869662817000 # Time in different power states 30411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 12162830000 # Time in different power states 30511860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 8118960750 # Time in different power states 30611860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 18468996750 # Time in different power states 30711860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 230243580 # Energy for activate commands per rank (pJ) 30811860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 122373570 # Energy for precharge commands per rank (pJ) 30911860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1463121660 # Energy for read commands per rank (pJ) 31011860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 324318600 # Energy for write commands per rank (pJ) 31111860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3740699040.000001 # Energy for refresh commands per rank (pJ) 31211860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 4231975260 # Energy for active background per rank (pJ) 31311860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 230624160 # Energy for precharge background per rank (pJ) 31411860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 8237523150 # Energy for active power-down per rank (pJ) 31511860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 4445714880 # Energy for precharge power-down per rank (pJ) 31611860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 449624008125 # Energy for self refresh per rank (pJ) 31711860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 472652324325 # Total energy per rank (pJ) 31811860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 247.402742 # Core power per rank (mW) 31911860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 1900567958250 # Total Idle time Per DRAM Rank 32011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 356565750 # Time in different power states 32111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1589032000 # Time in different power states 32211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 1870929942000 # Time in different power states 32311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 11577456000 # Time in different power states 32411860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 7939162500 # Time in different power states 32511860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 18064939250 # Time in different power states 32611860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 32711860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 32811860Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 16804357 # Number of BP lookups 32911860Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 14368910 # Number of conditional branches predicted 33011860Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 476654 # Number of conditional branches incorrect 33111860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 10787243 # Number of BTB lookups 33211860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 4777357 # Number of BTB hits 3339481Snilay@cs.wisc.edusystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33411860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 44.287099 # BTB Hit Percentage 33511860Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 929095 # Number of times the RAS was used to get a target. 33611860Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 33008 # Number of incorrect RAS predictions. 33711860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectLookups 5112942 # Number of indirect predictor lookups. 33811860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectHits 499455 # Number of indirect target hits. 33911860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectMisses 4613487 # Number of indirect misses. 34011860Sandreas.hansson@arm.comsystem.cpu0.branchPredindirectMispredicted 206250 # Number of mispredicted indirect branches. 34110576Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3428464SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 3438464SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 3448464SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 3458464SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 34611860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9429395 # DTB read hits 34711860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 34826 # DTB read misses 34811860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_acv 601 # DTB read access violations 34911860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 567385 # DTB read accesses 35011860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5710239 # DTB write hits 35111860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 8500 # DTB write misses 35211860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 413 # DTB write access violations 35311860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 185113 # DTB write accesses 35411860Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15139634 # DTB hits 35511860Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 43326 # DTB misses 35611860Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 1014 # DTB access violations 35711860Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 752498 # DTB accesses 35811860Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 1313411 # ITB hits 35911860Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 6916 # ITB misses 36011860Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_acv 613 # ITB acv 36111860Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 1320327 # ITB accesses 3628464SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 3638464SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 3648464SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 3658464SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 3668464SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 3678464SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 3688464SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 3698464SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 3708464SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 3718464SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 3728464SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 3738464SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 37411860Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 12957 # Number of power state transitions 37511860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 6479 # Distribution of time spent in the clock gated state 37611860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 285646442.815249 # Distribution of time spent in the clock gated state 37711860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 440880288.422179 # Distribution of time spent in the clock gated state 37811860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 6479 100.00% 100.00% # Distribution of time spent in the clock gated state 37911860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 39000 # Distribution of time spent in the clock gated state 38011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 38111860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 6479 # Distribution of time spent in the clock gated state 38211860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 59753794500 # Cumulative time (in ticks) in various power states 38311860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 1850703303000 # Cumulative time (in ticks) in various power states 38411860Sandreas.hansson@arm.comsystem.cpu0.numCycles 119514068 # number of cpu cycles simulated 3858464SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3868464SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 38711860Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 25767559 # Number of cycles fetch is stalled on an Icache miss 38811860Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 73719684 # Number of instructions fetch has processed 38911860Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 16804357 # Number of branches that fetch encountered 39011860Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 6205907 # Number of branches that fetch has predicted taken 39111860Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 86932839 # Number of cycles fetch has run and was not squashing or blocked 39211860Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 1362768 # Number of cycles fetch has spent squashing 39311860Sandreas.hansson@arm.comsystem.cpu0.fetch.TlbCycles 60 # Number of cycles fetch has spent waiting for tlb 39411860Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39511860Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 137457 # Number of stall cycles due to pending traps 39611860Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 417781 # Number of stall cycles due to pending quiesce instructions 39711860Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR 39811860Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 8508507 # Number of cache lines fetched 39911860Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 323806 # Number of outstanding Icache misses that were squashed 40011860Sandreas.hansson@arm.comsystem.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 40111860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 113967656 # Number of instructions fetched each cycle (Total) 40211860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 0.646847 # Number of instructions fetched each cycle (Total) 40311860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 1.957898 # Number of instructions fetched each cycle (Total) 4048464SN/Asystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40511860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 100279992 87.99% 87.99% # Number of instructions fetched each cycle (Total) 40611860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 883136 0.77% 88.76% # Number of instructions fetched each cycle (Total) 40711860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 1879288 1.65% 90.41% # Number of instructions fetched each cycle (Total) 40811860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 773699 0.68% 91.09% # Number of instructions fetched each cycle (Total) 40911860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::4 2621733 2.30% 93.39% # Number of instructions fetched each cycle (Total) 41011860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::5 582123 0.51% 93.90% # Number of instructions fetched each cycle (Total) 41111860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::6 690580 0.61% 94.51% # Number of instructions fetched each cycle (Total) 41211860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::7 840992 0.74% 95.25% # Number of instructions fetched each cycle (Total) 41311860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::8 5416113 4.75% 100.00% # Number of instructions fetched each cycle (Total) 4148464SN/Asystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4158464SN/Asystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 4168464SN/Asystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 41711860Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 113967656 # Number of instructions fetched each cycle (Total) 41811860Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.140606 # Number of branch fetches per cycle 41911860Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.616829 # Number of inst fetches per cycle 42011860Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 20688539 # Number of cycles decode is idle 42111860Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 82043348 # Number of cycles decode is blocked 42211860Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 8777506 # Number of cycles decode is running 42311860Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 1804992 # Number of cycles decode is unblocking 42411860Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 653270 # Number of cycles decode is squashing 42511860Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 4633985 # Number of times decode resolved a branch 42611860Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 29119 # Number of times decode detected a branch misprediction 42711860Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 64001211 # Number of instructions handled by decode 42811860Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 84558 # Number of squashed instructions handled by decode 42911860Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 653270 # Number of cycles rename is squashing 43011860Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 21557209 # Number of cycles rename is idle 43111860Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 55702323 # Number of cycles rename is blocking 43211860Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 17600356 # count of cycles rename stalled for serializing inst 43311860Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 9645124 # Number of cycles rename is running 43411860Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 8809372 # Number of cycles rename is unblocking 43511860Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 61498566 # Number of instructions processed by rename 43611860Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 199219 # Number of times rename has blocked due to ROB full 43711860Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 2004403 # Number of times rename has blocked due to IQ full 43811860Sandreas.hansson@arm.comsystem.cpu0.rename.LQFullEvents 243805 # Number of times rename has blocked due to LQ full 43911860Sandreas.hansson@arm.comsystem.cpu0.rename.SQFullEvents 4929982 # Number of times rename has blocked due to SQ full 44011860Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 41484246 # Number of destination operands rename has renamed 44111860Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 74256527 # Number of register rename lookups that rename has made 44211860Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 74125426 # Number of integer rename lookups 44311860Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 122370 # Number of floating rename lookups 44411860Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 33821902 # Number of HB maps that are committed 44511860Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 7662344 # Number of HB maps that are undone due to squashing 44611860Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 1423361 # count of serializing insts renamed 44711860Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 232902 # count of temporary serializing insts renamed 44811860Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 12334048 # count of insts added to the skid buffer 44911860Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 9834851 # Number of loads inserted to the mem dependence unit. 45011860Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 6076556 # Number of stores inserted to the mem dependence unit. 45111860Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 1449838 # Number of conflicting loads. 45211860Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 941199 # Number of conflicting stores. 45311860Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 54338035 # Number of instructions added to the IQ (excludes non-spec) 45411860Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1857223 # Number of non-speculative instructions added to the IQ 45511860Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 52670686 # Number of instructions issued 45611860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 76725 # Number of squashed instructions issued 45711860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 9465955 # Number of squashed instructions iterated over during squash; mainly for profiling 45811860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 4150833 # Number of squashed operands that are examined and possibly removed from graph 45911860Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 1293033 # Number of squashed non-spec instructions that were removed 46011860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 113967656 # Number of insts issued each cycle 46111860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.462155 # Number of insts issued each cycle 46211860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.203590 # Number of insts issued each cycle 4638464SN/Asystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 46411860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 92547755 81.21% 81.21% # Number of insts issued each cycle 46511860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 9157312 8.04% 89.24% # Number of insts issued each cycle 46611860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 3826452 3.36% 92.60% # Number of insts issued each cycle 46711860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 2741793 2.41% 95.00% # Number of insts issued each cycle 46811860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 2858470 2.51% 97.51% # Number of insts issued each cycle 46911860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 1410754 1.24% 98.75% # Number of insts issued each cycle 47011860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 945179 0.83% 99.58% # Number of insts issued each cycle 47111860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 363161 0.32% 99.90% # Number of insts issued each cycle 47211860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 116780 0.10% 100.00% # Number of insts issued each cycle 4738464SN/Asystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4748464SN/Asystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4758464SN/Asystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 47611860Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 113967656 # Number of insts issued each cycle 4778464SN/Asystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 167135 16.69% 16.69% # attempts to use FU when none available 47911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available 48011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available 48111860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available 48211860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available 48311860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available 48411860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available 48511860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available 48611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available 48711860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.69% # attempts to use FU when none available 48811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available 48911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available 49011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available 49111860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available 49211860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available 49311860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available 49411860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available 49511860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available 49611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available 49711860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available 49811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available 49911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available 50011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available 50111860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available 50211860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available 50311860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available 50411860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available 50511860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available 50611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available 50711860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available 50811860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available 50911860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 489044 48.84% 65.53% # attempts to use FU when none available 51011860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 297041 29.67% 95.20% # attempts to use FU when none available 51111860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMemRead 26511 2.65% 97.85% # attempts to use FU when none available 51211860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMemWrite 21568 2.15% 100.00% # attempts to use FU when none available 5138464SN/Asystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5148464SN/Asystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 51511860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 2539 0.00% 0.00% # Type of FU issued 51611860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 36140522 68.62% 68.62% # Type of FU issued 51711860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 55958 0.11% 68.73% # Type of FU issued 51811754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued 51911860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 25396 0.05% 68.78% # Type of FU issued 52011754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued 52111754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued 52211754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued 52311754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued 52411754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued 52511754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued 52611754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued 52711754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued 52811754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued 52911754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued 53011754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued 53111754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued 53211754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued 53311754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued 53411754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued 53511754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued 53611754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued 53711754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued 53811754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued 53911754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued 54011754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued 54111754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued 54211754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued 54311754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued 54411754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued 54511754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued 54611754Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued 54711860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 9743290 18.50% 87.28% # Type of FU issued 54811860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 5689891 10.80% 98.08% # Type of FU issued 54911860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMemRead 122252 0.23% 98.31% # Type of FU issued 55011860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMemWrite 110721 0.21% 98.52% # Type of FU issued 55111860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 778850 1.48% 100.00% # Type of FU issued 5528464SN/Asystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 55311860Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 52670686 # Type of FU issued 55411860Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.440707 # Inst issue rate 55511860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 1001299 # FU busy when requested 55611860Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.019011 # FU busy rate (busy events/executed inst) 55711860Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 219818324 # Number of integer instruction queue reads 55811860Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 65405263 # Number of integer instruction queue writes 55911860Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 50914307 # Number of integer instruction queue wakeup accesses 56011860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 568728 # Number of floating instruction queue reads 56111860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 273845 # Number of floating instruction queue writes 56211860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 257541 # Number of floating instruction queue wakeup accesses 56311860Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 53361731 # Number of integer alu accesses 56411860Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 307715 # Number of floating point alu accesses 56511860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 607759 # Number of loads that had data forwarded from stores 5668464SN/Asystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 56711860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 1969497 # Number of loads squashed 56811860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 4520 # Number of memory responses ignored because the instruction is squashed 56911860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 18416 # Number of memory ordering violations 57011860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 673256 # Number of stores squashed 5718464SN/Asystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5728464SN/Asystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 57311860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 18394 # Number of loads that were rescheduled 57411860Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 367969 # Number of times an access to memory failed due to the cache being blocked 5758464SN/Asystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 57611860Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 653270 # Number of cycles IEW is squashing 57711860Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 52238307 # Number of cycles IEW is blocking 57811860Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 1038475 # Number of cycles IEW is unblocking 57911860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 59749161 # Number of instructions dispatched to IQ 58011860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 168806 # Number of squashed instructions skipped by dispatch 58111860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 9834851 # Number of dispatched load instructions 58211860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 6076556 # Number of dispatched store instructions 58311860Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 1644704 # Number of dispatched non-speculative instructions 58411860Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 40383 # Number of times the IQ has become full, causing a stall 58511860Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 797635 # Number of times the LSQ has become full, causing a stall 58611860Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 18416 # Number of memory order violations 58711860Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 191736 # Number of branches that were predicted taken incorrectly 58811860Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 507842 # Number of branches that were predicted not taken incorrectly 58911860Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 699578 # Number of branch mispredicts detected at execute 59011860Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 51971663 # Number of executed instructions 59111860Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 9489993 # Number of load instructions executed 59211860Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 699023 # Number of squashed instructions skipped in execute 5938464SN/Asystem.cpu0.iew.exec_swp 0 # number of swp insts executed 59411860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 3553903 # number of nop insts executed 59511860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 15226009 # number of memory reference insts executed 59611860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 8258878 # Number of branches executed 59711860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 5736016 # Number of stores executed 59811860Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.434858 # Inst execution rate 59911860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 51356635 # cumulative count of insts sent to commit 60011860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 51171848 # cumulative count of insts written-back 60111860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 26241416 # num instructions producing a value 60211860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 36276103 # num instructions consuming a value 60311860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.428166 # insts written-back per cycle 60411860Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.723380 # average fanout of values written-back 60511860Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 9976632 # The number of squashed insts skipped by commit 60611860Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 564190 # The number of times commit has been forced to stall to communicate backwards 60711860Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 625296 # The number of times a branch was mispredicted 60811860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 112216183 # Number of insts commited each cycle 60911860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.442120 # Number of insts commited each cycle 61011860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.363987 # Number of insts commited each cycle 6118241SN/Asystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 61211860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 94653327 84.35% 84.35% # Number of insts commited each cycle 61311860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 6985358 6.22% 90.57% # Number of insts commited each cycle 61411860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 3782709 3.37% 93.94% # Number of insts commited each cycle 61511860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 2004229 1.79% 95.73% # Number of insts commited each cycle 61611860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 1568389 1.40% 97.13% # Number of insts commited each cycle 61711860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 570810 0.51% 97.64% # Number of insts commited each cycle 61811860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 418508 0.37% 98.01% # Number of insts commited each cycle 61911860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 451920 0.40% 98.41% # Number of insts commited each cycle 62011860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 1780933 1.59% 100.00% # Number of insts commited each cycle 6218241SN/Asystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6228241SN/Asystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6238241SN/Asystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 62411860Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 112216183 # Number of insts commited each cycle 62511860Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 49613021 # Number of instructions committed 62611860Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 49613021 # Number of ops (including micro ops) committed 6278241SN/Asystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 62811860Sandreas.hansson@arm.comsystem.cpu0.commit.refs 13268654 # Number of memory references committed 62911860Sandreas.hansson@arm.comsystem.cpu0.commit.loads 7865354 # Number of loads committed 63011860Sandreas.hansson@arm.comsystem.cpu0.commit.membars 192328 # Number of memory barriers committed 63111860Sandreas.hansson@arm.comsystem.cpu0.commit.branches 7511599 # Number of branches committed 63211860Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. 63311860Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 45921534 # Number of committed integer instructions. 63411860Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 632359 # Number of function calls committed. 63511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 2886254 5.82% 5.82% # Class of committed instruction 63611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntAlu 32400169 65.31% 71.12% # Class of committed instruction 63711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntMult 54625 0.11% 71.23% # Class of committed instruction 63811680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction 63911860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction 64011680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction 64111680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction 64211680SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction 64311687Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction 64411860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.29% # Class of committed instruction 64511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.29% # Class of committed instruction 64611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.29% # Class of committed instruction 64711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.29% # Class of committed instruction 64811860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.29% # Class of committed instruction 64911860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.29% # Class of committed instruction 65011860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.29% # Class of committed instruction 65111860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.29% # Class of committed instruction 65211860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.29% # Class of committed instruction 65311860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.29% # Class of committed instruction 65411860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.29% # Class of committed instruction 65511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.29% # Class of committed instruction 65611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.29% # Class of committed instruction 65711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.29% # Class of committed instruction 65811860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.29% # Class of committed instruction 65911860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.29% # Class of committed instruction 66011860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.29% # Class of committed instruction 66111860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.29% # Class of committed instruction 66211860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.29% # Class of committed instruction 66311860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.29% # Class of committed instruction 66411860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.29% # Class of committed instruction 66511860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.29% # Class of committed instruction 66611860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.29% # Class of committed instruction 66711860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemRead 7944499 16.01% 87.30% # Class of committed instruction 66811860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemWrite 5299897 10.68% 97.98% # Class of committed instruction 66911860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction 67011860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction 67111860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IprAccess 778850 1.57% 100.00% # Class of committed instruction 67210220Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 67311860Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::total 49613021 # Class of committed instruction 67411860Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 1780933 # number cycles where commit BW limit reached 67511860Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 169850432 # The number of ROB reads 67611860Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 120933247 # The number of ROB writes 67711860Sandreas.hansson@arm.comsystem.cpu0.timesIdled 478916 # Number of times that the entire CPU went into an idle state and unscheduled itself 67811860Sandreas.hansson@arm.comsystem.cpu0.idleCycles 5546412 # Total number of cycles that the CPU has spent unscheduled due to idling 67911860Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 3700805346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 68011860Sandreas.hansson@arm.comsystem.cpu0.committedInsts 46729302 # Number of Instructions Simulated 68111860Sandreas.hansson@arm.comsystem.cpu0.committedOps 46729302 # Number of Ops (including micro ops) Simulated 68211860Sandreas.hansson@arm.comsystem.cpu0.cpi 2.557583 # CPI: Cycles Per Instruction 68311860Sandreas.hansson@arm.comsystem.cpu0.cpi_total 2.557583 # CPI: Total CPI of All Threads 68411860Sandreas.hansson@arm.comsystem.cpu0.ipc 0.390994 # IPC: Instructions Per Cycle 68511860Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.390994 # IPC: Total IPC of All Threads 68611860Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 68048969 # number of integer regfile reads 68711860Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 37279666 # number of integer regfile writes 68811860Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 121382 # number of floating regfile reads 68911860Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 130068 # number of floating regfile writes 69011860Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1658488 # number of misc regfile reads 69111860Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 782262 # number of misc regfile writes 69211860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 69311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1253915 # number of replacements 69411860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.032819 # Cycle average of tags in use 69511860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 10656048 # Total number of references to valid blocks. 69611860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1254345 # Sample count of references to valid blocks. 69711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 8.495309 # Average number of references to valid blocks. 69811860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. 69911860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.032819 # Average occupied blocks per requestor 70011860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988345 # Average percentage of cache occupancy 70111860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988345 # Average percentage of cache occupancy 70211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id 70311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id 70411860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 70511754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id 70611860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 56914873 # Number of tag accesses 70711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 56914873 # Number of data accesses 70811860Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 70911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6773563 # number of ReadReq hits 71011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6773563 # number of ReadReq hits 71111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 3523907 # number of WriteReq hits 71211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 3523907 # number of WriteReq hits 71311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174492 # number of LoadLockedReq hits 71411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 174492 # number of LoadLockedReq hits 71511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 179921 # number of StoreCondReq hits 71611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 179921 # number of StoreCondReq hits 71711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10297470 # number of demand (read+write) hits 71811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10297470 # number of demand (read+write) hits 71911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10297470 # number of overall hits 72011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10297470 # number of overall hits 72111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1555944 # number of ReadReq misses 72211860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1555944 # number of ReadReq misses 72311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1682220 # number of WriteReq misses 72411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1682220 # number of WriteReq misses 72511860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19936 # number of LoadLockedReq misses 72611860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 19936 # number of LoadLockedReq misses 72711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 3029 # number of StoreCondReq misses 72811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 3029 # number of StoreCondReq misses 72911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 3238164 # number of demand (read+write) misses 73011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 3238164 # number of demand (read+write) misses 73111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 3238164 # number of overall misses 73211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 3238164 # number of overall misses 73311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41483749500 # number of ReadReq miss cycles 73411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 41483749500 # number of ReadReq miss cycles 73511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85008982052 # number of WriteReq miss cycles 73611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 85008982052 # number of WriteReq miss cycles 73711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 398193000 # number of LoadLockedReq miss cycles 73811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 398193000 # number of LoadLockedReq miss cycles 73911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17043500 # number of StoreCondReq miss cycles 74011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 17043500 # number of StoreCondReq miss cycles 74111860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 126492731552 # number of demand (read+write) miss cycles 74211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 126492731552 # number of demand (read+write) miss cycles 74311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 126492731552 # number of overall miss cycles 74411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 126492731552 # number of overall miss cycles 74511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8329507 # number of ReadReq accesses(hits+misses) 74611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8329507 # number of ReadReq accesses(hits+misses) 74711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5206127 # number of WriteReq accesses(hits+misses) 74811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5206127 # number of WriteReq accesses(hits+misses) 74911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194428 # number of LoadLockedReq accesses(hits+misses) 75011860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 194428 # number of LoadLockedReq accesses(hits+misses) 75111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182950 # number of StoreCondReq accesses(hits+misses) 75211860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 182950 # number of StoreCondReq accesses(hits+misses) 75311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 13535634 # number of demand (read+write) accesses 75411860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 13535634 # number of demand (read+write) accesses 75511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 13535634 # number of overall (read+write) accesses 75611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 13535634 # number of overall (read+write) accesses 75711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186799 # miss rate for ReadReq accesses 75811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.186799 # miss rate for ReadReq accesses 75911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323123 # miss rate for WriteReq accesses 76011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.323123 # miss rate for WriteReq accesses 76111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102537 # miss rate for LoadLockedReq accesses 76211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102537 # miss rate for LoadLockedReq accesses 76311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016556 # miss rate for StoreCondReq accesses 76411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.016556 # miss rate for StoreCondReq accesses 76511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.239233 # miss rate for demand accesses 76611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.239233 # miss rate for demand accesses 76711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.239233 # miss rate for overall accesses 76811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.239233 # miss rate for overall accesses 76911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26661.466929 # average ReadReq miss latency 77011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 26661.466929 # average ReadReq miss latency 77111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50533.807737 # average WriteReq miss latency 77211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 50533.807737 # average WriteReq miss latency 77311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19973.565409 # average LoadLockedReq miss latency 77411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19973.565409 # average LoadLockedReq miss latency 77511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.774513 # average StoreCondReq miss latency 77611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.774513 # average StoreCondReq miss latency 77711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency 77811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 39063.102286 # average overall miss latency 77911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency 78011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 39063.102286 # average overall miss latency 78111860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 4473141 # number of cycles access was blocked 78211860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 2637 # number of cycles access was blocked 78311860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 108649 # number of cycles access was blocked 78411860Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 100 # number of cycles access was blocked 78511860Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.170568 # average number of cycles each access was blocked 78611860Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 26.370000 # average number of cycles each access was blocked 78711860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 737996 # number of writebacks 78811860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 737996 # number of writebacks 78911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 553324 # number of ReadReq MSHR hits 79011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 553324 # number of ReadReq MSHR hits 79111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1430604 # number of WriteReq MSHR hits 79211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1430604 # number of WriteReq MSHR hits 79311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5325 # number of LoadLockedReq MSHR hits 79411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 5325 # number of LoadLockedReq MSHR hits 79511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1983928 # number of demand (read+write) MSHR hits 79611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1983928 # number of demand (read+write) MSHR hits 79711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1983928 # number of overall MSHR hits 79811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1983928 # number of overall MSHR hits 79911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002620 # number of ReadReq MSHR misses 80011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 1002620 # number of ReadReq MSHR misses 80111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251616 # number of WriteReq MSHR misses 80211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 251616 # number of WriteReq MSHR misses 80311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14611 # number of LoadLockedReq MSHR misses 80411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 14611 # number of LoadLockedReq MSHR misses 80511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3029 # number of StoreCondReq MSHR misses 80611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 3029 # number of StoreCondReq MSHR misses 80711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1254236 # number of demand (read+write) MSHR misses 80811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1254236 # number of demand (read+write) MSHR misses 80911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1254236 # number of overall MSHR misses 81011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1254236 # number of overall MSHR misses 81111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable 81211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable 81311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable 81411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 9909 # number of WriteReq MSHR uncacheable 81511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses 81611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 16886 # number of overall MSHR uncacheable misses 81711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31595131000 # number of ReadReq MSHR miss cycles 81811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 31595131000 # number of ReadReq MSHR miss cycles 81911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13207477923 # number of WriteReq MSHR miss cycles 82011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 13207477923 # number of WriteReq MSHR miss cycles 82111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 169739500 # number of LoadLockedReq MSHR miss cycles 82211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 169739500 # number of LoadLockedReq MSHR miss cycles 82311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14014500 # number of StoreCondReq MSHR miss cycles 82411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14014500 # number of StoreCondReq MSHR miss cycles 82511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44802608923 # number of demand (read+write) MSHR miss cycles 82611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 44802608923 # number of demand (read+write) MSHR miss cycles 82711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44802608923 # number of overall MSHR miss cycles 82811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 44802608923 # number of overall MSHR miss cycles 82911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557264500 # number of ReadReq MSHR uncacheable cycles 83011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557264500 # number of ReadReq MSHR uncacheable cycles 83111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557264500 # number of overall MSHR uncacheable cycles 83211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557264500 # number of overall MSHR uncacheable cycles 83311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120370 # mshr miss rate for ReadReq accesses 83411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses 83511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048331 # mshr miss rate for WriteReq accesses 83611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048331 # mshr miss rate for WriteReq accesses 83711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075149 # mshr miss rate for LoadLockedReq accesses 83811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075149 # mshr miss rate for LoadLockedReq accesses 83911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016556 # mshr miss rate for StoreCondReq accesses 84011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016556 # mshr miss rate for StoreCondReq accesses 84111860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for demand accesses 84211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.092662 # mshr miss rate for demand accesses 84311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for overall accesses 84411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.092662 # mshr miss rate for overall accesses 84511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31512.568072 # average ReadReq mshr miss latency 84611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31512.568072 # average ReadReq mshr miss latency 84711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52490.612374 # average WriteReq mshr miss latency 84811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52490.612374 # average WriteReq mshr miss latency 84911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11617.240435 # average LoadLockedReq mshr miss latency 85011860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11617.240435 # average LoadLockedReq mshr miss latency 85111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.774513 # average StoreCondReq mshr miss latency 85211860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.774513 # average StoreCondReq mshr miss latency 85311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency 85411860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency 85511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency 85611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency 85711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223199.727677 # average ReadReq mshr uncacheable latency 85811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223199.727677 # average ReadReq mshr uncacheable latency 85911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92222.225512 # average overall mshr uncacheable latency 86011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92222.225512 # average overall mshr uncacheable latency 86111860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 86211860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 891919 # number of replacements 86311860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 509.368701 # Cycle average of tags in use 86411860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 7561136 # Total number of references to valid blocks. 86511860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 892430 # Sample count of references to valid blocks. 86611860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 8.472526 # Average number of references to valid blocks. 86711860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 30335024500 # Cycle when the warmup percentage was hit. 86811860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 509.368701 # Average occupied blocks per requestor 86911860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.994861 # Average percentage of cache occupancy 87011860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.994861 # Average percentage of cache occupancy 87111606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 87211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id 87311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 87411606Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 87511860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 9401165 # Number of tag accesses 87611860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 9401165 # Number of data accesses 87711860Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 87811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 7561136 # number of ReadReq hits 87911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 7561136 # number of ReadReq hits 88011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 7561136 # number of demand (read+write) hits 88111860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 7561136 # number of demand (read+write) hits 88211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 7561136 # number of overall hits 88311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 7561136 # number of overall hits 88411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 947367 # number of ReadReq misses 88511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 947367 # number of ReadReq misses 88611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 947367 # number of demand (read+write) misses 88711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 947367 # number of demand (read+write) misses 88811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 947367 # number of overall misses 88911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 947367 # number of overall misses 89011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858743493 # number of ReadReq miss cycles 89111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 13858743493 # number of ReadReq miss cycles 89211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 13858743493 # number of demand (read+write) miss cycles 89311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 13858743493 # number of demand (read+write) miss cycles 89411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 13858743493 # number of overall miss cycles 89511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 13858743493 # number of overall miss cycles 89611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 8508503 # number of ReadReq accesses(hits+misses) 89711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 8508503 # number of ReadReq accesses(hits+misses) 89811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 8508503 # number of demand (read+write) accesses 89911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 8508503 # number of demand (read+write) accesses 90011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 8508503 # number of overall (read+write) accesses 90111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 8508503 # number of overall (read+write) accesses 90211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111344 # miss rate for ReadReq accesses 90311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.111344 # miss rate for ReadReq accesses 90411860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.111344 # miss rate for demand accesses 90511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.111344 # miss rate for demand accesses 90611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.111344 # miss rate for overall accesses 90711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.111344 # miss rate for overall accesses 90811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14628.695630 # average ReadReq miss latency 90911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 14628.695630 # average ReadReq miss latency 91011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency 91111860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 14628.695630 # average overall miss latency 91211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency 91311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 14628.695630 # average overall miss latency 91411860Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 7760 # number of cycles access was blocked 91510576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91611860Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 263 # number of cycles access was blocked 91710576Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 91811860Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 29.505703 # average number of cycles each access was blocked 91910576Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92011860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 891919 # number of writebacks 92111860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 891919 # number of writebacks 92211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54705 # number of ReadReq MSHR hits 92311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 54705 # number of ReadReq MSHR hits 92411860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 54705 # number of demand (read+write) MSHR hits 92511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 54705 # number of demand (read+write) MSHR hits 92611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 54705 # number of overall MSHR hits 92711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 54705 # number of overall MSHR hits 92811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 892662 # number of ReadReq MSHR misses 92911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 892662 # number of ReadReq MSHR misses 93011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 892662 # number of demand (read+write) MSHR misses 93111860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 892662 # number of demand (read+write) MSHR misses 93211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 892662 # number of overall MSHR misses 93311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 892662 # number of overall MSHR misses 93411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12247880494 # number of ReadReq MSHR miss cycles 93511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 12247880494 # number of ReadReq MSHR miss cycles 93611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12247880494 # number of demand (read+write) MSHR miss cycles 93711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 12247880494 # number of demand (read+write) MSHR miss cycles 93811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12247880494 # number of overall MSHR miss cycles 93911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 12247880494 # number of overall MSHR miss cycles 94011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for ReadReq accesses 94111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104914 # mshr miss rate for ReadReq accesses 94211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for demand accesses 94311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.104914 # mshr miss rate for demand accesses 94411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for overall accesses 94511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.104914 # mshr miss rate for overall accesses 94611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average ReadReq mshr miss latency 94711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13720.624933 # average ReadReq mshr miss latency 94811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency 94911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency 95011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency 95111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency 95211860Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 4440494 # Number of BP lookups 95311860Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 3820633 # Number of conditional branches predicted 95411860Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 114977 # Number of conditional branches incorrect 95511860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 2284731 # Number of BTB lookups 95611860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 882766 # Number of BTB hits 9579481Snilay@cs.wisc.edusystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 95811860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 38.637634 # BTB Hit Percentage 95911860Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 229523 # Number of times the RAS was used to get a target. 96011860Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 8540 # Number of incorrect RAS predictions. 96111860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectLookups 1232926 # Number of indirect predictor lookups. 96211860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectHits 164040 # Number of indirect target hits. 96311860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectMisses 1068886 # Number of indirect misses. 96411860Sandreas.hansson@arm.comsystem.cpu1.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. 9658464SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 9668464SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 9678464SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 9688464SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 96911860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2425125 # DTB read hits 97011860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 16040 # DTB read misses 97111860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_acv 82 # DTB read access violations 97211860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 432289 # DTB read accesses 97311860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 1438640 # DTB write hits 97411860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 3531 # DTB write misses 97511860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 65 # DTB write access violations 97611860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 162605 # DTB write accesses 97711860Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 3863765 # DTB hits 97811860Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 19571 # DTB misses 97911754Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 147 # DTB access violations 98011860Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 594894 # DTB accesses 98111860Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 679335 # ITB hits 98211860Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 3486 # ITB misses 98311860Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_acv 144 # ITB acv 98411860Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 682821 # ITB accesses 9858464SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 9868464SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 9878464SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 9888464SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 9898464SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 9908464SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 9918464SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 9928464SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 9938464SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 9948464SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 9958464SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 9968464SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 99711860Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 5088 # Number of power state transitions 99811860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2544 # Distribution of time spent in the clock gated state 99911860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 747516916.077044 # Distribution of time spent in the clock gated state 100011860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 396242813.132808 # Distribution of time spent in the clock gated state 100111860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 2544 100.00% 100.00% # Distribution of time spent in the clock gated state 100211860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state 100311860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 975504000 # Distribution of time spent in the clock gated state 100411860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 2544 # Distribution of time spent in the clock gated state 100511860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 8774063000 # Cumulative time (in ticks) in various power states 100611860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 1901683034500 # Cumulative time (in ticks) in various power states 100711860Sandreas.hansson@arm.comsystem.cpu1.numCycles 17550671 # number of cpu cycles simulated 10088464SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 10098464SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 101011860Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 7093737 # Number of cycles fetch is stalled on an Icache miss 101111860Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 17628277 # Number of instructions fetch has processed 101211860Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 4440494 # Number of branches that fetch encountered 101311860Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 1276329 # Number of branches that fetch has predicted taken 101411860Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 9234250 # Number of cycles fetch has run and was not squashing or blocked 101511860Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 381282 # Number of cycles fetch has spent squashing 101611860Sandreas.hansson@arm.comsystem.cpu1.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb 101711860Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 26389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 101811860Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 68063 # Number of stall cycles due to pending traps 101911860Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 51076 # Number of stall cycles due to pending quiesce instructions 102011860Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR 102111860Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 1982953 # Number of cache lines fetched 102211860Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 84304 # Number of outstanding Icache misses that were squashed 102311860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 16664213 # Number of instructions fetched each cycle (Total) 102411860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 1.057852 # Number of instructions fetched each cycle (Total) 102511860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 2.464693 # Number of instructions fetched each cycle (Total) 10268464SN/Asystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 102711860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 13566532 81.41% 81.41% # Number of instructions fetched each cycle (Total) 102811860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 196080 1.18% 82.59% # Number of instructions fetched each cycle (Total) 102911860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 329765 1.98% 84.57% # Number of instructions fetched each cycle (Total) 103011860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 235529 1.41% 85.98% # Number of instructions fetched each cycle (Total) 103111860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::4 402874 2.42% 88.40% # Number of instructions fetched each cycle (Total) 103211860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::5 150126 0.90% 89.30% # Number of instructions fetched each cycle (Total) 103311860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::6 175137 1.05% 90.35% # Number of instructions fetched each cycle (Total) 103411860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::7 212228 1.27% 91.62% # Number of instructions fetched each cycle (Total) 103511860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::8 1395942 8.38% 100.00% # Number of instructions fetched each cycle (Total) 10368464SN/Asystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 10378464SN/Asystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 10388464SN/Asystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 103911860Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 16664213 # Number of instructions fetched each cycle (Total) 104011860Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.253010 # Number of branch fetches per cycle 104111860Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 1.004422 # Number of inst fetches per cycle 104211860Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 5803889 # Number of cycles decode is idle 104311860Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 8198941 # Number of cycles decode is blocked 104411860Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 2195429 # Number of cycles decode is running 104511860Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 282754 # Number of cycles decode is unblocking 104611860Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 183199 # Number of cycles decode is squashing 104711860Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 845965 # Number of times decode resolved a branch 104811860Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 7619 # Number of times decode detected a branch misprediction 104911860Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 14397519 # Number of instructions handled by decode 105011860Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 23764 # Number of squashed instructions handled by decode 105111860Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 183199 # Number of cycles rename is squashing 105211860Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 5993501 # Number of cycles rename is idle 105311860Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 917111 # Number of cycles rename is blocking 105411860Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 6016357 # count of cycles rename stalled for serializing inst 105511860Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 2289218 # Number of cycles rename is running 105611860Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 1264825 # Number of cycles rename is unblocking 105711860Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 13624374 # Number of instructions processed by rename 105811860Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 3775 # Number of times rename has blocked due to ROB full 105911860Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 108540 # Number of times rename has blocked due to IQ full 106011860Sandreas.hansson@arm.comsystem.cpu1.rename.LQFullEvents 34178 # Number of times rename has blocked due to LQ full 106111860Sandreas.hansson@arm.comsystem.cpu1.rename.SQFullEvents 643759 # Number of times rename has blocked due to SQ full 106211860Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 9046149 # Number of destination operands rename has renamed 106311860Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 16244839 # Number of register rename lookups that rename has made 106411860Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 16178929 # Number of integer rename lookups 106511860Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 59321 # Number of floating rename lookups 106611860Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 7078981 # Number of HB maps that are committed 106711860Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 1967160 # Number of HB maps that are undone due to squashing 106811860Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 511491 # count of serializing insts renamed 106911860Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 53621 # count of temporary serializing insts renamed 107011860Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 2283119 # count of insts added to the skid buffer 107111860Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 2539964 # Number of loads inserted to the mem dependence unit. 107211860Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 1543921 # Number of stores inserted to the mem dependence unit. 107311860Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 323106 # Number of conflicting loads. 107411860Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 168966 # Number of conflicting stores. 107511860Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 11939663 # Number of instructions added to the IQ (excludes non-spec) 107611860Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 585885 # Number of non-speculative instructions added to the IQ 107711860Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 11455956 # Number of instructions issued 107811860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 28942 # Number of squashed instructions issued 107911860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 2572399 # Number of squashed instructions iterated over during squash; mainly for profiling 108011860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 1228155 # Number of squashed operands that are examined and possibly removed from graph 108111860Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 432246 # Number of squashed non-spec instructions that were removed 108211860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 16664213 # Number of insts issued each cycle 108311860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.687459 # Number of insts issued each cycle 108411860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.414504 # Number of insts issued each cycle 10858464SN/Asystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 108611860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 11970475 71.83% 71.83% # Number of insts issued each cycle 108711860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 2021121 12.13% 83.96% # Number of insts issued each cycle 108811860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 863574 5.18% 89.14% # Number of insts issued each cycle 108911860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 618225 3.71% 92.85% # Number of insts issued each cycle 109011860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 572472 3.44% 96.29% # Number of insts issued each cycle 109111860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 300775 1.80% 98.09% # Number of insts issued each cycle 109211860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 197233 1.18% 99.28% # Number of insts issued each cycle 109311860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 86853 0.52% 99.80% # Number of insts issued each cycle 109411860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 33485 0.20% 100.00% # Number of insts issued each cycle 10958464SN/Asystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 10968464SN/Asystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 10978464SN/Asystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 109811860Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 16664213 # Number of insts issued each cycle 10998464SN/Asystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 110011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 33486 10.24% 10.24% # attempts to use FU when none available 110111860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available 110211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available 110311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available 110411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available 110511860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available 110611860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available 110711860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available 110811860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available 110911860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.24% # attempts to use FU when none available 111011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available 111111860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.24% # attempts to use FU when none available 111211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.24% # attempts to use FU when none available 111311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.24% # attempts to use FU when none available 111411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.24% # attempts to use FU when none available 111511860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.24% # attempts to use FU when none available 111611860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.24% # attempts to use FU when none available 111711860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 10.24% # attempts to use FU when none available 111811860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.24% # attempts to use FU when none available 111911860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 10.24% # attempts to use FU when none available 112011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.24% # attempts to use FU when none available 112111860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.24% # attempts to use FU when none available 112211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.24% # attempts to use FU when none available 112311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.24% # attempts to use FU when none available 112411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.24% # attempts to use FU when none available 112511860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.24% # attempts to use FU when none available 112611860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.24% # attempts to use FU when none available 112711860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.24% # attempts to use FU when none available 112811860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.24% # attempts to use FU when none available 112911860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available 113011860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.24% # attempts to use FU when none available 113111860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 173880 53.16% 63.40% # attempts to use FU when none available 113211860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 104341 31.90% 95.30% # attempts to use FU when none available 113311860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMemRead 7997 2.44% 97.75% # attempts to use FU when none available 113411860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMemWrite 7375 2.25% 100.00% # attempts to use FU when none available 11358464SN/Asystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 11368464SN/Asystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 113711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 4756 0.04% 0.04% # Type of FU issued 113811860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 7097834 61.96% 62.00% # Type of FU issued 113911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 17086 0.15% 62.15% # Type of FU issued 114011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued 114111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.27% # Type of FU issued 114211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued 114311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued 114411860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued 114511860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.27% # Type of FU issued 114611860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.29% # Type of FU issued 114711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.29% # Type of FU issued 114811860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.29% # Type of FU issued 114911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.29% # Type of FU issued 115011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.29% # Type of FU issued 115111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.29% # Type of FU issued 115211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.29% # Type of FU issued 115311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.29% # Type of FU issued 115411860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.29% # Type of FU issued 115511860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.29% # Type of FU issued 115611860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.29% # Type of FU issued 115711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.29% # Type of FU issued 115811860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.29% # Type of FU issued 115911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.29% # Type of FU issued 116011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.29% # Type of FU issued 116111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.29% # Type of FU issued 116211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.29% # Type of FU issued 116311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.29% # Type of FU issued 116411860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.29% # Type of FU issued 116511860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.29% # Type of FU issued 116611860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.29% # Type of FU issued 116711860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.29% # Type of FU issued 116811860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.29% # Type of FU issued 116911860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 2506692 21.88% 84.17% # Type of FU issued 117011860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 1424790 12.44% 96.61% # Type of FU issued 117111860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMemRead 45041 0.39% 97.00% # Type of FU issued 117211860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMemWrite 43535 0.38% 97.38% # Type of FU issued 117311860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 299845 2.62% 100.00% # Type of FU issued 11748464SN/Asystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 117511860Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 11455956 # Type of FU issued 117611860Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.652736 # Inst issue rate 117711860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 327079 # FU busy when requested 117811860Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.028551 # FU busy rate (busy events/executed inst) 117911860Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 39706848 # Number of integer instruction queue reads 118011860Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 14995495 # Number of integer instruction queue writes 118111860Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 10932885 # Number of integer instruction queue wakeup accesses 118211860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 225297 # Number of floating instruction queue reads 118311860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 107483 # Number of floating instruction queue writes 118411860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 104737 # Number of floating instruction queue wakeup accesses 118511860Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 11657954 # Number of integer alu accesses 118611860Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 120325 # Number of floating point alu accesses 118711860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 118525 # Number of loads that had data forwarded from stores 11888464SN/Asystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 118911860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 552207 # Number of loads squashed 119011860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 1214 # Number of memory responses ignored because the instruction is squashed 119111860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 5210 # Number of memory ordering violations 119211860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 179004 # Number of stores squashed 11938464SN/Asystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 11948464SN/Asystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 119511860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 539 # Number of loads that were rescheduled 119611860Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 99906 # Number of times an access to memory failed due to the cache being blocked 11978464SN/Asystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 119811860Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 183199 # Number of cycles IEW is squashing 119911860Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 564470 # Number of cycles IEW is blocking 120011860Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 284501 # Number of cycles IEW is unblocking 120111860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 13175740 # Number of instructions dispatched to IQ 120211860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 58730 # Number of squashed instructions skipped by dispatch 120311860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 2539964 # Number of dispatched load instructions 120411860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 1543921 # Number of dispatched store instructions 120511860Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 532175 # Number of dispatched non-speculative instructions 120611860Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 7107 # Number of times the IQ has become full, causing a stall 120711860Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 276039 # Number of times the LSQ has become full, causing a stall 120811860Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 5210 # Number of memory order violations 120911860Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 46730 # Number of branches that were predicted taken incorrectly 121011860Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 149015 # Number of branches that were predicted not taken incorrectly 121111860Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 195745 # Number of branch mispredicts detected at execute 121211860Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 11262138 # Number of executed instructions 121311860Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 2450359 # Number of load instructions executed 121411860Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 193817 # Number of squashed instructions skipped in execute 12158464SN/Asystem.cpu1.iew.exec_swp 0 # number of swp insts executed 121611860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 650192 # number of nop insts executed 121711860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 3899095 # number of memory reference insts executed 121811860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 1684701 # Number of branches executed 121911860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 1448736 # Number of stores executed 122011860Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.641693 # Inst execution rate 122111860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 11092333 # cumulative count of insts sent to commit 122211860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 11037622 # cumulative count of insts written-back 122311860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 5277529 # num instructions producing a value 122411860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 7434192 # num instructions consuming a value 122511860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.628900 # insts written-back per cycle 122611860Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.709899 # average fanout of values written-back 122711860Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 2589103 # The number of squashed insts skipped by commit 122811860Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 153639 # The number of times commit has been forced to stall to communicate backwards 122911860Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 170452 # The number of times a branch was mispredicted 123011860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 16200161 # Number of insts commited each cycle 123111860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.644352 # Number of insts commited each cycle 123211860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.619659 # Number of insts commited each cycle 12338464SN/Asystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 123411860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 12420478 76.67% 76.67% # Number of insts commited each cycle 123511860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 1746852 10.78% 87.45% # Number of insts commited each cycle 123611860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 623239 3.85% 91.30% # Number of insts commited each cycle 123711860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 386399 2.39% 93.68% # Number of insts commited each cycle 123811860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 294857 1.82% 95.50% # Number of insts commited each cycle 123911860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 125210 0.77% 96.28% # Number of insts commited each cycle 124011860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 112311 0.69% 96.97% # Number of insts commited each cycle 124111860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 119786 0.74% 97.71% # Number of insts commited each cycle 124211860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 371029 2.29% 100.00% # Number of insts commited each cycle 12438464SN/Asystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 12448464SN/Asystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 12458464SN/Asystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 124611860Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 16200161 # Number of insts commited each cycle 124711860Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 10438605 # Number of instructions committed 124811860Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 10438605 # Number of ops (including micro ops) committed 12498464SN/Asystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 125011860Sandreas.hansson@arm.comsystem.cpu1.commit.refs 3352674 # Number of memory references committed 125111860Sandreas.hansson@arm.comsystem.cpu1.commit.loads 1987757 # Number of loads committed 125211860Sandreas.hansson@arm.comsystem.cpu1.commit.membars 48909 # Number of memory barriers committed 125311860Sandreas.hansson@arm.comsystem.cpu1.commit.branches 1497531 # Number of branches committed 125411860Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. 125511860Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 9696003 # Number of committed integer instructions. 125611860Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 163829 # Number of function calls committed. 125711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 490211 4.70% 4.70% # Class of committed instruction 125811860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntAlu 6213226 59.52% 64.22% # Class of committed instruction 125911860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntMult 16788 0.16% 64.38% # Class of committed instruction 126011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction 126111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.51% # Class of committed instruction 126211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction 126311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction 126411860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction 126511860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.51% # Class of committed instruction 126611860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.54% # Class of committed instruction 126711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.54% # Class of committed instruction 126811860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.54% # Class of committed instruction 126911860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.54% # Class of committed instruction 127011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.54% # Class of committed instruction 127111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.54% # Class of committed instruction 127211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.54% # Class of committed instruction 127311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.54% # Class of committed instruction 127411860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.54% # Class of committed instruction 127511860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.54% # Class of committed instruction 127611860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.54% # Class of committed instruction 127711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.54% # Class of committed instruction 127811860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.54% # Class of committed instruction 127911860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.54% # Class of committed instruction 128011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.54% # Class of committed instruction 128111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.54% # Class of committed instruction 128211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.54% # Class of committed instruction 128311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.54% # Class of committed instruction 128411860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.54% # Class of committed instruction 128511860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.54% # Class of committed instruction 128611860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.54% # Class of committed instruction 128711860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.54% # Class of committed instruction 128811860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.54% # Class of committed instruction 128911860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemRead 1991924 19.08% 83.62% # Class of committed instruction 129011860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemWrite 1323832 12.68% 96.30% # Class of committed instruction 129111860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction 129211860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction 129311860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IprAccess 299845 2.87% 100.00% # Class of committed instruction 129410220Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 129511860Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::total 10438605 # Class of committed instruction 129611860Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 371029 # number cycles where commit BW limit reached 129711860Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 28746473 # The number of ROB reads 129811860Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 26517839 # The number of ROB writes 129911860Sandreas.hansson@arm.comsystem.cpu1.timesIdled 134718 # Number of times that the entire CPU went into an idle state and unscheduled itself 130011860Sandreas.hansson@arm.comsystem.cpu1.idleCycles 886458 # Total number of cycles that the CPU has spent unscheduled due to idling 130111860Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 3803363525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 130211860Sandreas.hansson@arm.comsystem.cpu1.committedInsts 9953144 # Number of Instructions Simulated 130311860Sandreas.hansson@arm.comsystem.cpu1.committedOps 9953144 # Number of Ops (including micro ops) Simulated 130411860Sandreas.hansson@arm.comsystem.cpu1.cpi 1.763329 # CPI: Cycles Per Instruction 130511860Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.763329 # CPI: Total CPI of All Threads 130611860Sandreas.hansson@arm.comsystem.cpu1.ipc 0.567109 # IPC: Instructions Per Cycle 130711860Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.567109 # IPC: Total IPC of All Threads 130811860Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 14490611 # number of integer regfile reads 130911860Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 7893529 # number of integer regfile writes 131011860Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 58631 # number of floating regfile reads 131111860Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 57835 # number of floating regfile writes 131211860Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 573327 # number of misc regfile reads 131311860Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 245000 # number of misc regfile writes 131411860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 131511860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 130880 # number of replacements 131611860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 488.755319 # Cycle average of tags in use 131711860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 3056587 # Total number of references to valid blocks. 131811860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 131392 # Sample count of references to valid blocks. 131911860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 23.263113 # Average number of references to valid blocks. 132011860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 49534102500 # Cycle when the warmup percentage was hit. 132111860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 488.755319 # Average occupied blocks per requestor 132211860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.954600 # Average percentage of cache occupancy 132311860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.954600 # Average percentage of cache occupancy 132411336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 132511860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id 132611860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id 132711860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 132811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 132911860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 14487576 # Number of tag accesses 133011860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 14487576 # Number of data accesses 133111860Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 133211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1941589 # number of ReadReq hits 133311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1941589 # number of ReadReq hits 133411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1026269 # number of WriteReq hits 133511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1026269 # number of WriteReq hits 133611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40594 # number of LoadLockedReq hits 133711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 40594 # number of LoadLockedReq hits 133811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 37239 # number of StoreCondReq hits 133911860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 37239 # number of StoreCondReq hits 134011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 2967858 # number of demand (read+write) hits 134111860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 2967858 # number of demand (read+write) hits 134211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 2967858 # number of overall hits 134311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 2967858 # number of overall hits 134411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 240679 # number of ReadReq misses 134511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 240679 # number of ReadReq misses 134611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 291916 # number of WriteReq misses 134711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 291916 # number of WriteReq misses 134811860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5260 # number of LoadLockedReq misses 134911860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5260 # number of LoadLockedReq misses 135011860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 3088 # number of StoreCondReq misses 135111860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 3088 # number of StoreCondReq misses 135211860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 532595 # number of demand (read+write) misses 135311860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 532595 # number of demand (read+write) misses 135411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 532595 # number of overall misses 135511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 532595 # number of overall misses 135611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3354943500 # number of ReadReq miss cycles 135711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 3354943500 # number of ReadReq miss cycles 135811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12208160588 # number of WriteReq miss cycles 135911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 12208160588 # number of WriteReq miss cycles 136011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 53604000 # number of LoadLockedReq miss cycles 136111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 53604000 # number of LoadLockedReq miss cycles 136211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17137500 # number of StoreCondReq miss cycles 136311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 17137500 # number of StoreCondReq miss cycles 136411860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 15563104088 # number of demand (read+write) miss cycles 136511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 15563104088 # number of demand (read+write) miss cycles 136611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 15563104088 # number of overall miss cycles 136711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 15563104088 # number of overall miss cycles 136811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2182268 # number of ReadReq accesses(hits+misses) 136911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2182268 # number of ReadReq accesses(hits+misses) 137011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1318185 # number of WriteReq accesses(hits+misses) 137111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 1318185 # number of WriteReq accesses(hits+misses) 137211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45854 # number of LoadLockedReq accesses(hits+misses) 137311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 45854 # number of LoadLockedReq accesses(hits+misses) 137411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40327 # number of StoreCondReq accesses(hits+misses) 137511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 40327 # number of StoreCondReq accesses(hits+misses) 137611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 3500453 # number of demand (read+write) accesses 137711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 3500453 # number of demand (read+write) accesses 137811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 3500453 # number of overall (read+write) accesses 137911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 3500453 # number of overall (read+write) accesses 138011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110288 # miss rate for ReadReq accesses 138111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.110288 # miss rate for ReadReq accesses 138211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221453 # miss rate for WriteReq accesses 138311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.221453 # miss rate for WriteReq accesses 138411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.114712 # miss rate for LoadLockedReq accesses 138511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.114712 # miss rate for LoadLockedReq accesses 138611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076574 # miss rate for StoreCondReq accesses 138711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.076574 # miss rate for StoreCondReq accesses 138811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.152150 # miss rate for demand accesses 138911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.152150 # miss rate for demand accesses 139011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.152150 # miss rate for overall accesses 139111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.152150 # miss rate for overall accesses 139211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13939.494098 # average ReadReq miss latency 139311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 13939.494098 # average ReadReq miss latency 139411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41820.799778 # average WriteReq miss latency 139511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 41820.799778 # average WriteReq miss latency 139611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10190.874525 # average LoadLockedReq miss latency 139711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10190.874525 # average LoadLockedReq miss latency 139811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5549.708549 # average StoreCondReq miss latency 139911860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5549.708549 # average StoreCondReq miss latency 140011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency 140111860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 29221.273365 # average overall miss latency 140211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency 140311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 29221.273365 # average overall miss latency 140411860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 720106 # number of cycles access was blocked 140511860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 464 # number of cycles access was blocked 140611860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 24866 # number of cycles access was blocked 140711860Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 14 # number of cycles access was blocked 140811860Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.959463 # average number of cycles each access was blocked 140911860Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets 33.142857 # average number of cycles each access was blocked 141011860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 84401 # number of writebacks 141111860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 84401 # number of writebacks 141211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147677 # number of ReadReq MSHR hits 141311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 147677 # number of ReadReq MSHR hits 141411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243516 # number of WriteReq MSHR hits 141511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 243516 # number of WriteReq MSHR hits 141611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 792 # number of LoadLockedReq MSHR hits 141711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 792 # number of LoadLockedReq MSHR hits 141811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 391193 # number of demand (read+write) MSHR hits 141911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 391193 # number of demand (read+write) MSHR hits 142011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 391193 # number of overall MSHR hits 142111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 391193 # number of overall MSHR hits 142211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93002 # number of ReadReq MSHR misses 142311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 93002 # number of ReadReq MSHR misses 142411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48400 # number of WriteReq MSHR misses 142511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 48400 # number of WriteReq MSHR misses 142611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4468 # number of LoadLockedReq MSHR misses 142711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 4468 # number of LoadLockedReq MSHR misses 142811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3088 # number of StoreCondReq MSHR misses 142911860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 3088 # number of StoreCondReq MSHR misses 143011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 141402 # number of demand (read+write) MSHR misses 143111860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 141402 # number of demand (read+write) MSHR misses 143211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 141402 # number of overall MSHR misses 143311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 141402 # number of overall MSHR misses 143411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable 143511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable 143611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable 143711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 3156 # number of WriteReq MSHR uncacheable 143811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses 143911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 3374 # number of overall MSHR uncacheable misses 144011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1257789500 # number of ReadReq MSHR miss cycles 144111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 1257789500 # number of ReadReq MSHR miss cycles 144211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1961692747 # number of WriteReq MSHR miss cycles 144311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1961692747 # number of WriteReq MSHR miss cycles 144411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39632000 # number of LoadLockedReq MSHR miss cycles 144511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39632000 # number of LoadLockedReq MSHR miss cycles 144611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14049500 # number of StoreCondReq MSHR miss cycles 144711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14049500 # number of StoreCondReq MSHR miss cycles 144811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3219482247 # number of demand (read+write) MSHR miss cycles 144911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 3219482247 # number of demand (read+write) MSHR miss cycles 145011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3219482247 # number of overall MSHR miss cycles 145111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 3219482247 # number of overall MSHR miss cycles 145211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41842500 # number of ReadReq MSHR uncacheable cycles 145311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41842500 # number of ReadReq MSHR uncacheable cycles 145411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41842500 # number of overall MSHR uncacheable cycles 145511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 41842500 # number of overall MSHR uncacheable cycles 145611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042617 # mshr miss rate for ReadReq accesses 145711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042617 # mshr miss rate for ReadReq accesses 145811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses 145911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses 146011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097440 # mshr miss rate for LoadLockedReq accesses 146111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097440 # mshr miss rate for LoadLockedReq accesses 146211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076574 # mshr miss rate for StoreCondReq accesses 146311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076574 # mshr miss rate for StoreCondReq accesses 146411860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for demand accesses 146511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses 146611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for overall accesses 146711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses 146811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13524.327434 # average ReadReq mshr miss latency 146911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13524.327434 # average ReadReq mshr miss latency 147011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40530.841880 # average WriteReq mshr miss latency 147111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40530.841880 # average WriteReq mshr miss latency 147211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8870.188004 # average LoadLockedReq mshr miss latency 147311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8870.188004 # average LoadLockedReq mshr miss latency 147411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.708549 # average StoreCondReq mshr miss latency 147511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.708549 # average StoreCondReq mshr miss latency 147611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency 147711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency 147811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency 147911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency 148011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191938.073394 # average ReadReq mshr uncacheable latency 148111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191938.073394 # average ReadReq mshr uncacheable latency 148211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12401.452282 # average overall mshr uncacheable latency 148311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12401.452282 # average overall mshr uncacheable latency 148411860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 148511860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 256309 # number of replacements 148611860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 470.814625 # Cycle average of tags in use 148711860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 1714023 # Total number of references to valid blocks. 148811860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 256821 # Sample count of references to valid blocks. 148911860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 6.673999 # Average number of references to valid blocks. 149011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1883968823500 # Cycle when the warmup percentage was hit. 149111860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 470.814625 # Average occupied blocks per requestor 149211860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.919560 # Average percentage of cache occupancy 149311860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.919560 # Average percentage of cache occupancy 149411680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 149511860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 149611860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 149711754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id 149811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 149911860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 2239848 # Number of tag accesses 150011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 2239848 # Number of data accesses 150111860Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 150211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 1714023 # number of ReadReq hits 150311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 1714023 # number of ReadReq hits 150411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 1714023 # number of demand (read+write) hits 150511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 1714023 # number of demand (read+write) hits 150611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 1714023 # number of overall hits 150711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 1714023 # number of overall hits 150811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 268930 # number of ReadReq misses 150911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 268930 # number of ReadReq misses 151011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 268930 # number of demand (read+write) misses 151111860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 268930 # number of demand (read+write) misses 151211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 268930 # number of overall misses 151311860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 268930 # number of overall misses 151411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3748012499 # number of ReadReq miss cycles 151511860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 3748012499 # number of ReadReq miss cycles 151611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 3748012499 # number of demand (read+write) miss cycles 151711860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 3748012499 # number of demand (read+write) miss cycles 151811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 3748012499 # number of overall miss cycles 151911860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 3748012499 # number of overall miss cycles 152011860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 1982953 # number of ReadReq accesses(hits+misses) 152111860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 1982953 # number of ReadReq accesses(hits+misses) 152211860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 1982953 # number of demand (read+write) accesses 152311860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 1982953 # number of demand (read+write) accesses 152411860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 1982953 # number of overall (read+write) accesses 152511860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 1982953 # number of overall (read+write) accesses 152611860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.135621 # miss rate for ReadReq accesses 152711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.135621 # miss rate for ReadReq accesses 152811860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.135621 # miss rate for demand accesses 152911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.135621 # miss rate for demand accesses 153011860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.135621 # miss rate for overall accesses 153111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.135621 # miss rate for overall accesses 153211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13936.758632 # average ReadReq miss latency 153311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 13936.758632 # average ReadReq miss latency 153411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency 153511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 13936.758632 # average overall miss latency 153611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency 153711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 13936.758632 # average overall miss latency 153811860Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 558 # number of cycles access was blocked 153910576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 154011860Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 46 # number of cycles access was blocked 154110576Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 154211860Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 12.130435 # average number of cycles each access was blocked 154310576Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 154411860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 256309 # number of writebacks 154511860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 256309 # number of writebacks 154611860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12035 # number of ReadReq MSHR hits 154711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 12035 # number of ReadReq MSHR hits 154811860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 12035 # number of demand (read+write) MSHR hits 154911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 12035 # number of demand (read+write) MSHR hits 155011860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 12035 # number of overall MSHR hits 155111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 12035 # number of overall MSHR hits 155211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 256895 # number of ReadReq MSHR misses 155311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 256895 # number of ReadReq MSHR misses 155411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 256895 # number of demand (read+write) MSHR misses 155511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 256895 # number of demand (read+write) MSHR misses 155611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 256895 # number of overall MSHR misses 155711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 256895 # number of overall MSHR misses 155811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3358325499 # number of ReadReq MSHR miss cycles 155911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 3358325499 # number of ReadReq MSHR miss cycles 156011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3358325499 # number of demand (read+write) MSHR miss cycles 156111860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 3358325499 # number of demand (read+write) MSHR miss cycles 156211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3358325499 # number of overall MSHR miss cycles 156311860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 3358325499 # number of overall MSHR miss cycles 156411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for ReadReq accesses 156511860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129552 # mshr miss rate for ReadReq accesses 156611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for demand accesses 156711860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.129552 # mshr miss rate for demand accesses 156811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for overall accesses 156911860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.129552 # mshr miss rate for overall accesses 157011860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average ReadReq mshr miss latency 157111860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13072.755402 # average ReadReq mshr miss latency 157211860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency 157311860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency 157411860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency 157511860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency 157610576Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 157710576Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 157810576Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 157910576Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 158010576Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 158110576Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 158210576Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 158310576Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 158410576Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 158510576Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 158610576Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 158710576Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 158811860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 158911606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadReq 7374 # Transaction distribution 159011606Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadResp 7374 # Transaction distribution 159111860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 54617 # Transaction distribution 159211860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 54617 # Transaction distribution 159311860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11920 # Packet count per connected master and slave (bytes) 159411606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 159510576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 159610576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 159710892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 159810892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 159910576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 160011570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 160110576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 160211860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 40520 # Packet count per connected master and slave (bytes) 160311606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 160411606Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 160511860Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) 160611860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47680 # Cumulative packet size per connected master and slave (bytes) 160711606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 160810576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 160910576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 161010892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 161110892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 161210576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 161311570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 161410576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 161511860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 73906 # Cumulative packet size per connected master and slave (bytes) 161611606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 161711606Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 161811860Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) 161911860Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 12368500 # Layer occupancy (ticks) 162010576Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 162111860Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) 162210576Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 162311860Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 162410576Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 162511860Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 162610576Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 162711860Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 176500 # Layer occupancy (ticks) 162810576Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 162911860Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 14153500 # Layer occupancy (ticks) 163010576Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 163111860Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2825500 # Layer occupancy (ticks) 163210576Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 163311860Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 6058000 # Layer occupancy (ticks) 163410576Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 163511860Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks) 163610576Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 163711860Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 216256520 # Layer occupancy (ticks) 163810576Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 163911860Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 27455000 # Layer occupancy (ticks) 164010576Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 164111606Sandreas.sandberg@arm.comsystem.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) 164210576Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 164311860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 164411606Sandreas.sandberg@arm.comsystem.iocache.tags.replacements 41699 # number of replacements 164511860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.514549 # Cycle average of tags in use 164610576Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 164711606Sandreas.sandberg@arm.comsystem.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 164810576Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 164911860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1714263350000 # Cycle when the warmup percentage was hit. 165011860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.514549 # Average occupied blocks per requestor 165111860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.032159 # Average percentage of cache occupancy 165211860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.032159 # Average percentage of cache occupancy 165310576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 165411606Sandreas.sandberg@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 165510576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 165611606Sandreas.sandberg@arm.comsystem.iocache.tags.tag_accesses 375579 # Number of tag accesses 165711606Sandreas.sandberg@arm.comsystem.iocache.tags.data_accesses 375579 # Number of data accesses 165811860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 165911606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 166011606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 166110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 166210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 166311606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 166411606Sandreas.sandberg@arm.comsystem.iocache.demand_misses::total 41731 # number of demand (read+write) misses 166511606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 166611606Sandreas.sandberg@arm.comsystem.iocache.overall_misses::total 41731 # number of overall misses 166711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 22652883 # number of ReadReq miss cycles 166811860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 22652883 # number of ReadReq miss cycles 166911860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 4915863637 # number of WriteLineReq miss cycles 167011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 4915863637 # number of WriteLineReq miss cycles 167111860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 4938516520 # number of demand (read+write) miss cycles 167211860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 4938516520 # number of demand (read+write) miss cycles 167311860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 4938516520 # number of overall miss cycles 167411860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 4938516520 # number of overall miss cycles 167511606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 167611606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 167710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 167810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 167911606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 168011606Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 168111606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 168211606Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 168310576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 168410576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 168510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 168610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 168710576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 168810576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 168910576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 169010576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 169111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 126552.418994 # average ReadReq miss latency 169211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 126552.418994 # average ReadReq miss latency 169311860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118306.306243 # average WriteLineReq miss latency 169411860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 118306.306243 # average WriteLineReq miss latency 169511860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency 169611860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 118341.676931 # average overall miss latency 169711860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency 169811860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 118341.676931 # average overall miss latency 169911860Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked 170010576Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170111860Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 4 # number of cycles access was blocked 170210576Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 170311860Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 173.750000 # average number of cycles each access was blocked 170410576Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 170511103Snilay@cs.wisc.edusystem.iocache.writebacks::writebacks 41520 # number of writebacks 170611103Snilay@cs.wisc.edusystem.iocache.writebacks::total 41520 # number of writebacks 170711606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 170811606Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 170910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 171010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 171111606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 171211606Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 171311606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 171411606Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses 171511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13702883 # number of ReadReq MSHR miss cycles 171611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13702883 # number of ReadReq MSHR miss cycles 171711860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2835827584 # number of WriteLineReq MSHR miss cycles 171811860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 2835827584 # number of WriteLineReq MSHR miss cycles 171911860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 2849530467 # number of demand (read+write) MSHR miss cycles 172011860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 2849530467 # number of demand (read+write) MSHR miss cycles 172111860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 2849530467 # number of overall MSHR miss cycles 172211860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 2849530467 # number of overall MSHR miss cycles 172310576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 172410576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 172510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 172610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 172710576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 172810576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 172910576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 173010576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 173111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76552.418994 # average ReadReq mshr miss latency 173211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 76552.418994 # average ReadReq mshr miss latency 173311860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68247.679630 # average WriteLineReq mshr miss latency 173411860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.679630 # average WriteLineReq mshr miss latency 173511860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency 173611860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency 173711860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency 173811860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency 173911860Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 174011860Sandreas.hansson@arm.comsystem.l2c.tags.replacements 345895 # number of replacements 174111860Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65423.250509 # Cycle average of tags in use 174211860Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4330734 # Total number of references to valid blocks. 174311860Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 411417 # Sample count of references to valid blocks. 174411860Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 10.526386 # Average number of references to valid blocks. 174511860Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 6416604000 # Cycle when the warmup percentage was hit. 174611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 292.398395 # Average occupied blocks per requestor 174711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5320.578215 # Average occupied blocks per requestor 174811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 58825.194930 # Average occupied blocks per requestor 174911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 208.100344 # Average occupied blocks per requestor 175011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 776.978626 # Average occupied blocks per requestor 175111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.004462 # Average percentage of cache occupancy 175211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.081186 # Average percentage of cache occupancy 175311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.897601 # Average percentage of cache occupancy 175411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.003175 # Average percentage of cache occupancy 175511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011856 # Average percentage of cache occupancy 175611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.998280 # Average percentage of cache occupancy 175711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 175811860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id 175911860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 1663 # Occupied blocks per task id 176011860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1868 # Occupied blocks per task id 176111860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5665 # Occupied blocks per task id 176211860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 56191 # Occupied blocks per task id 176311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 176411860Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 38351741 # Number of tag accesses 176511860Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 38351741 # Number of data accesses 176611860Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 176711860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 822397 # number of WritebackDirty hits 176811860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 822397 # number of WritebackDirty hits 176911860Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::writebacks 872029 # number of WritebackClean hits 177011860Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::total 872029 # number of WritebackClean hits 177111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 2840 # number of UpgradeReq hits 177211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 1502 # number of UpgradeReq hits 177311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 4342 # number of UpgradeReq hits 177411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits 177511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 466 # number of SCUpgradeReq hits 177611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 967 # number of SCUpgradeReq hits 177711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 145832 # number of ReadExReq hits 177811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 30945 # number of ReadExReq hits 177911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 176777 # number of ReadExReq hits 178011860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 879111 # number of ReadCleanReq hits 178111860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 254952 # number of ReadCleanReq hits 178211860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::total 1134063 # number of ReadCleanReq hits 178311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 723239 # number of ReadSharedReq hits 178411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 83990 # number of ReadSharedReq hits 178511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 807229 # number of ReadSharedReq hits 178611860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 879111 # number of demand (read+write) hits 178711860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 869071 # number of demand (read+write) hits 178811860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 254952 # number of demand (read+write) hits 178911860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 114935 # number of demand (read+write) hits 179011860Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2118069 # number of demand (read+write) hits 179111860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 879111 # number of overall hits 179211860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 869071 # number of overall hits 179311860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 254952 # number of overall hits 179411860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 114935 # number of overall hits 179511860Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2118069 # number of overall hits 179611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 7 # number of UpgradeReq misses 179711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses 179811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses 179911606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses 180011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 180111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 109607 # number of ReadExReq misses 180211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 12062 # number of ReadExReq misses 180311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 121669 # number of ReadExReq misses 180411860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 13385 # number of ReadCleanReq misses 180511860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 1902 # number of ReadCleanReq misses 180611860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::total 15287 # number of ReadCleanReq misses 180711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 272541 # number of ReadSharedReq misses 180811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1968 # number of ReadSharedReq misses 180911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 274509 # number of ReadSharedReq misses 181011860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 13385 # number of demand (read+write) misses 181111860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 382148 # number of demand (read+write) misses 181211860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1902 # number of demand (read+write) misses 181311754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses 181411860Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 411465 # number of demand (read+write) misses 181511860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 13385 # number of overall misses 181611860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 382148 # number of overall misses 181711860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1902 # number of overall misses 181811754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 14030 # number of overall misses 181911860Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 411465 # number of overall misses 182011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 361500 # number of UpgradeReq miss cycles 182111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 116000 # number of UpgradeReq miss cycles 182211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 477500 # number of UpgradeReq miss cycles 182311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 11326788500 # number of ReadExReq miss cycles 182411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 1531540500 # number of ReadExReq miss cycles 182511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 12858329000 # number of ReadExReq miss cycles 182611860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu0.inst 1345659000 # number of ReadCleanReq miss cycles 182711860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu1.inst 188021500 # number of ReadCleanReq miss cycles 182811860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::total 1533680500 # number of ReadCleanReq miss cycles 182911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 22177607000 # number of ReadSharedReq miss cycles 183011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 225042000 # number of ReadSharedReq miss cycles 183111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 22402649000 # number of ReadSharedReq miss cycles 183211860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 1345659000 # number of demand (read+write) miss cycles 183311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 33504395500 # number of demand (read+write) miss cycles 183411860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 188021500 # number of demand (read+write) miss cycles 183511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 1756582500 # number of demand (read+write) miss cycles 183611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 36794658500 # number of demand (read+write) miss cycles 183711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 1345659000 # number of overall miss cycles 183811860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 33504395500 # number of overall miss cycles 183911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 188021500 # number of overall miss cycles 184011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 1756582500 # number of overall miss cycles 184111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 36794658500 # number of overall miss cycles 184211860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 822397 # number of WritebackDirty accesses(hits+misses) 184311860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 822397 # number of WritebackDirty accesses(hits+misses) 184411860Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::writebacks 872029 # number of WritebackClean accesses(hits+misses) 184511860Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::total 872029 # number of WritebackClean accesses(hits+misses) 184611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2847 # number of UpgradeReq accesses(hits+misses) 184711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 1507 # number of UpgradeReq accesses(hits+misses) 184811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 4354 # number of UpgradeReq accesses(hits+misses) 184911860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 501 # number of SCUpgradeReq accesses(hits+misses) 185011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 467 # number of SCUpgradeReq accesses(hits+misses) 185111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 968 # number of SCUpgradeReq accesses(hits+misses) 185211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 255439 # number of ReadExReq accesses(hits+misses) 185311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 43007 # number of ReadExReq accesses(hits+misses) 185411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 298446 # number of ReadExReq accesses(hits+misses) 185511860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 892496 # number of ReadCleanReq accesses(hits+misses) 185611860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 256854 # number of ReadCleanReq accesses(hits+misses) 185711860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::total 1149350 # number of ReadCleanReq accesses(hits+misses) 185811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 995780 # number of ReadSharedReq accesses(hits+misses) 185911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 85958 # number of ReadSharedReq accesses(hits+misses) 186011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 1081738 # number of ReadSharedReq accesses(hits+misses) 186111860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 892496 # number of demand (read+write) accesses 186211860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1251219 # number of demand (read+write) accesses 186311860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 256854 # number of demand (read+write) accesses 186411860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 128965 # number of demand (read+write) accesses 186511860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2529534 # number of demand (read+write) accesses 186611860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 892496 # number of overall (read+write) accesses 186711860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1251219 # number of overall (read+write) accesses 186811860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 256854 # number of overall (read+write) accesses 186911860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 128965 # number of overall (read+write) accesses 187011860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2529534 # number of overall (read+write) accesses 187111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.002459 # miss rate for UpgradeReq accesses 187211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.003318 # miss rate for UpgradeReq accesses 187311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.002756 # miss rate for UpgradeReq accesses 187411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002141 # miss rate for SCUpgradeReq accesses 187511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.001033 # miss rate for SCUpgradeReq accesses 187611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.429093 # miss rate for ReadExReq accesses 187711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.280466 # miss rate for ReadExReq accesses 187811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.407675 # miss rate for ReadExReq accesses 187911860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014997 # miss rate for ReadCleanReq accesses 188011860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007405 # miss rate for ReadCleanReq accesses 188111860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.013301 # miss rate for ReadCleanReq accesses 188211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273696 # miss rate for ReadSharedReq accesses 188311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022895 # miss rate for ReadSharedReq accesses 188411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.253767 # miss rate for ReadSharedReq accesses 188511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.014997 # miss rate for demand accesses 188611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.305421 # miss rate for demand accesses 188711860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.007405 # miss rate for demand accesses 188811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.108789 # miss rate for demand accesses 188911860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.162664 # miss rate for demand accesses 189011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.014997 # miss rate for overall accesses 189111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.305421 # miss rate for overall accesses 189211860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.007405 # miss rate for overall accesses 189311860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.108789 # miss rate for overall accesses 189411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.162664 # miss rate for overall accesses 189511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 51642.857143 # average UpgradeReq miss latency 189611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23200 # average UpgradeReq miss latency 189711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 39791.666667 # average UpgradeReq miss latency 189811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 103340.010218 # average ReadExReq miss latency 189911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 126972.351186 # average ReadExReq miss latency 190011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 105682.869096 # average ReadExReq miss latency 190111860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100534.852447 # average ReadCleanReq miss latency 190211860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 98854.626709 # average ReadCleanReq miss latency 190311860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::total 100325.799699 # average ReadCleanReq miss latency 190411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81373.470414 # average ReadSharedReq miss latency 190511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 114350.609756 # average ReadSharedReq miss latency 190611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 81609.888929 # average ReadSharedReq miss latency 190711860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency 190811860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency 190911860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency 191011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency 191111860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 89423.543922 # average overall miss latency 191211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency 191311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency 191411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency 191511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency 191611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 89423.543922 # average overall miss latency 191710576Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 191810576Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 191910576Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 192010576Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 192110576Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 192210576Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 192311860Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 82068 # number of writebacks 192411860Sandreas.hansson@arm.comsystem.l2c.writebacks::total 82068 # number of writebacks 192511860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu1.inst 16 # number of ReadCleanReq MSHR hits 192611860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_hits::total 16 # number of ReadCleanReq MSHR hits 192711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits 192811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits 192911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 193011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 193111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 193211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 193311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 193411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits 193511754Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 193611754Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 193711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 7 # number of UpgradeReq MSHR misses 193811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses 193911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses 194011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses 194111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 194211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 109607 # number of ReadExReq MSHR misses 194311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 12062 # number of ReadExReq MSHR misses 194411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 121669 # number of ReadExReq MSHR misses 194511860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13385 # number of ReadCleanReq MSHR misses 194611860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1886 # number of ReadCleanReq MSHR misses 194711860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_misses::total 15271 # number of ReadCleanReq MSHR misses 194811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 272541 # number of ReadSharedReq MSHR misses 194911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 1967 # number of ReadSharedReq MSHR misses 195011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses 195111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 13385 # number of demand (read+write) MSHR misses 195211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 382148 # number of demand (read+write) MSHR misses 195311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 1886 # number of demand (read+write) MSHR misses 195411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses 195511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 411448 # number of demand (read+write) MSHR misses 195611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 13385 # number of overall MSHR misses 195711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 382148 # number of overall MSHR misses 195811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 1886 # number of overall MSHR misses 195911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses 196011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 411448 # number of overall MSHR misses 196111680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable 196211680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable 196311606Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable 196411860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable 196511860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable 196611860Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 13065 # number of WriteReq MSHR uncacheable 196711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses 196811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses 196911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 20260 # number of overall MSHR uncacheable misses 197011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 291500 # number of UpgradeReq MSHR miss cycles 197111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 94500 # number of UpgradeReq MSHR miss cycles 197211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 386000 # number of UpgradeReq MSHR miss cycles 197311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles 197411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles 197511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10230718500 # number of ReadExReq MSHR miss cycles 197611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1410920500 # number of ReadExReq MSHR miss cycles 197711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 11641639000 # number of ReadExReq MSHR miss cycles 197811860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1211809000 # number of ReadCleanReq MSHR miss cycles 197911860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 167908000 # number of ReadCleanReq MSHR miss cycles 198011860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::total 1379717000 # number of ReadCleanReq MSHR miss cycles 198111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19458079003 # number of ReadSharedReq MSHR miss cycles 198211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 205283000 # number of ReadSharedReq MSHR miss cycles 198311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 19663362003 # number of ReadSharedReq MSHR miss cycles 198411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 1211809000 # number of demand (read+write) MSHR miss cycles 198511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 29688797503 # number of demand (read+write) MSHR miss cycles 198611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 167908000 # number of demand (read+write) MSHR miss cycles 198711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 1616203500 # number of demand (read+write) MSHR miss cycles 198811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency::total 32684718003 # number of demand (read+write) MSHR miss cycles 198911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 1211809000 # number of overall MSHR miss cycles 199011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 29688797503 # number of overall MSHR miss cycles 199111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 167908000 # number of overall MSHR miss cycles 199211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 1616203500 # number of overall MSHR miss cycles 199311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 32684718003 # number of overall MSHR miss cycles 199411860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1470022500 # number of ReadReq MSHR uncacheable cycles 199511860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39117500 # number of ReadReq MSHR uncacheable cycles 199611860Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1509140000 # number of ReadReq MSHR uncacheable cycles 199711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 1470022500 # number of overall MSHR uncacheable cycles 199811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 39117500 # number of overall MSHR uncacheable cycles 199911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 1509140000 # number of overall MSHR uncacheable cycles 200010892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 200110892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 200211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002459 # mshr miss rate for UpgradeReq accesses 200311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003318 # mshr miss rate for UpgradeReq accesses 200411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.002756 # mshr miss rate for UpgradeReq accesses 200511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002141 # mshr miss rate for SCUpgradeReq accesses 200611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001033 # mshr miss rate for SCUpgradeReq accesses 200711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.429093 # mshr miss rate for ReadExReq accesses 200811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280466 # mshr miss rate for ReadExReq accesses 200911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.407675 # mshr miss rate for ReadExReq accesses 201011860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for ReadCleanReq accesses 201111860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for ReadCleanReq accesses 201211860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::total 0.013287 # mshr miss rate for ReadCleanReq accesses 201311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273696 # mshr miss rate for ReadSharedReq accesses 201411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022883 # mshr miss rate for ReadSharedReq accesses 201511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.253766 # mshr miss rate for ReadSharedReq accesses 201611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for demand accesses 201711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for demand accesses 201811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for demand accesses 201911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for demand accesses 202011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.162658 # mshr miss rate for demand accesses 202111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for overall accesses 202211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for overall accesses 202311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for overall accesses 202411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for overall accesses 202511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.162658 # mshr miss rate for overall accesses 202611860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 41642.857143 # average UpgradeReq mshr miss latency 202711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18900 # average UpgradeReq mshr miss latency 202811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 32166.666667 # average UpgradeReq mshr miss latency 202911606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency 203011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency 203111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93340.010218 # average ReadExReq mshr miss latency 203211860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116972.351186 # average ReadExReq mshr miss latency 203311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 95682.869096 # average ReadExReq mshr miss latency 203411860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average ReadCleanReq mshr miss latency 203511860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average ReadCleanReq mshr miss latency 203611860Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90348.831118 # average ReadCleanReq mshr miss latency 203711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71395.052499 # average ReadSharedReq mshr miss latency 203811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 104363.497712 # average ReadSharedReq mshr miss latency 203911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71631.289445 # average ReadSharedReq mshr miss latency 204011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency 204111860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency 204211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency 204311860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency 204411860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency 204511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency 204611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency 204711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency 204811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency 204911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency 205011860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210695.499498 # average ReadReq mshr uncacheable latency 205111860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179438.073394 # average ReadReq mshr uncacheable latency 205211860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209748.436414 # average ReadReq mshr uncacheable latency 205311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87055.697027 # average overall mshr uncacheable latency 205411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11593.805572 # average overall mshr uncacheable latency 205511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 74488.647581 # average overall mshr uncacheable latency 205611860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 851998 # Total number of requests made to the snoop filter. 205711860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 399673 # Number of requests hitting in the snoop filter with a single holder of the requested data. 205811860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 205911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 206011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 206111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 206211860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 206311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadReq 7195 # Transaction distribution 206411860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 297108 # Transaction distribution 206511860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 13065 # Transaction distribution 206611860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 13065 # Transaction distribution 206711860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 123588 # Transaction distribution 206811860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 263109 # Transaction distribution 206911860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 6612 # Transaction distribution 207011860Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 5150 # Transaction distribution 207111336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 207211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 121960 # Transaction distribution 207311860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 121558 # Transaction distribution 207411860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 289958 # Transaction distribution 207511754Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 45 # Transaction distribution 207610892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 207711754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 134 # Transaction distribution 207811860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40520 # Packet count per connected master and slave (bytes) 207911860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179462 # Packet count per connected master and slave (bytes) 208011754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) 208111860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 1220072 # Packet count per connected master and slave (bytes) 208211606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) 208311606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) 208411860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1303517 # Packet count per connected master and slave (bytes) 208511860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73906 # Cumulative packet size per connected master and slave (bytes) 208611860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31556864 # Cumulative packet size per connected master and slave (bytes) 208711860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 31630770 # Cumulative packet size per connected master and slave (bytes) 208811103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 208911103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 209011860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 34289010 # Cumulative packet size per connected master and slave (bytes) 209111860Sandreas.hansson@arm.comsystem.membus.snoops 12625 # Total snoops (count) 209211860Sandreas.hansson@arm.comsystem.membus.snoopTraffic 28672 # Total snoop traffic (bytes) 209311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 485492 # Request fanout histogram 209411860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.001421 # Request fanout histogram 209511860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.037673 # Request fanout histogram 209610576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 209711860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 484802 99.86% 99.86% # Request fanout histogram 209811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 690 0.14% 100.00% # Request fanout histogram 209910576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 210010576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 210111502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 210210576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 210311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 485492 # Request fanout histogram 210411860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 36514000 # Layer occupancy (ticks) 210510576Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 210611860Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1353680299 # Layer occupancy (ticks) 210710576Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 210811860Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 56000 # Layer occupancy (ticks) 210910576Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 211011860Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2179395750 # Layer occupancy (ticks) 211110726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 211211860Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 1105081 # Layer occupancy (ticks) 211310576Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 211411860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 211511860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 5103450 # Total number of requests made to the snoop filter. 211611860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 2546310 # Number of requests hitting in the snoop filter with a single holder of the requested data. 211711860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 356575 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 211811860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. 211911860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 212011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 212111860Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 212211606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution 212311860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2260935 # Transaction distribution 212411860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 13065 # Transaction distribution 212511860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 13065 # Transaction distribution 212611860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 904465 # Transaction distribution 212711860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1148228 # Transaction distribution 212811860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 826225 # Transaction distribution 212911860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 10843 # Transaction distribution 213011860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 6117 # Transaction distribution 213111860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 16960 # Transaction distribution 213211860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 299845 # Transaction distribution 213311860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 299845 # Transaction distribution 213411860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1149557 # Transaction distribution 213511860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 1104232 # Transaction distribution 213611754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution 213711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution 213811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution 213911860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2677077 # Packet count per connected master and slave (bytes) 214011860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3814281 # Packet count per connected master and slave (bytes) 214111860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 770058 # Packet count per connected master and slave (bytes) 214211860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417575 # Packet count per connected master and slave (bytes) 214311860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 7678991 # Packet count per connected master and slave (bytes) 214411860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114202560 # Cumulative packet size per connected master and slave (bytes) 214511860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127366412 # Cumulative packet size per connected master and slave (bytes) 214611860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32842432 # Cumulative packet size per connected master and slave (bytes) 214711860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13680230 # Cumulative packet size per connected master and slave (bytes) 214811860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 288091634 # Cumulative packet size per connected master and slave (bytes) 214911860Sandreas.hansson@arm.comsystem.toL2Bus.snoops 382034 # Total snoops (count) 215011860Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 6794496 # Total snoop traffic (bytes) 215111860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 2936985 # Request fanout histogram 215211860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.126280 # Request fanout histogram 215311860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.332605 # Request fanout histogram 215410576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 215511860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 2566512 87.39% 87.39% # Request fanout histogram 215611860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 370085 12.60% 99.99% # Request fanout histogram 215711860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 367 0.01% 100.00% # Request fanout histogram 215811860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 21 0.00% 100.00% # Request fanout histogram 215911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 216010576Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 216111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 216211138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 216311860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 2936985 # Request fanout histogram 216411860Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 4539093837 # Layer occupancy (ticks) 216510892Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 216611860Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 303384 # Layer occupancy (ticks) 216710576Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 216811860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 1340375720 # Layer occupancy (ticks) 216911103Snilay@cs.wisc.edusystem.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 217011860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 1912124205 # Layer occupancy (ticks) 217110726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 217211860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.occupancy 386934286 # Layer occupancy (ticks) 217310628Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 217411860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.occupancy 217615473 # Layer occupancy (ticks) 217510576Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 217611860Sandreas.hansson@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 217711860Sandreas.hansson@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 217811860Sandreas.hansson@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 217911860Sandreas.hansson@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 218010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 218110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 218210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 218310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 218410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 218510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 218610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 218710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 218810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 218910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 219010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 219110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 219210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 219310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 219410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 219510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 219610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 219710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 219810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 219910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 220010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 220110576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 220210576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 220310576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 220410576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 220510576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 220610576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 220710576Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 220810576Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 220910576Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 221010576Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 221111860Sandreas.hansson@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221211860Sandreas.hansson@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221311860Sandreas.hansson@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221411860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221511860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221611860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221711860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221811860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 221911860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222011860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222111860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222211860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222311860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222411860Sandreas.hansson@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222511860Sandreas.hansson@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222611860Sandreas.hansson@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222711860Sandreas.hansson@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222811860Sandreas.hansson@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 222911860Sandreas.hansson@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 223011860Sandreas.hansson@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 223111860Sandreas.hansson@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 223211860Sandreas.hansson@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 223311860Sandreas.hansson@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states 22348464SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 223511860Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6479 # number of quiesce instructions executed 223611860Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 176756 # number of hwrei instructions executed 223711860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 62790 40.27% 40.27% # number of times we switched to this ipl 223811680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl 223911860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1928 1.24% 41.59% # number of times we switched to this ipl 224011860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl 224111860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 90883 58.29% 100.00% # number of times we switched to this ipl 224211860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 155913 # number of times we switched to this ipl 224311860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 61775 49.18% 49.18% # number of times we switched to this ipl from a different ipl 224411860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 131 0.10% 49.28% # number of times we switched to this ipl from a different ipl 224511860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1928 1.53% 50.82% # number of times we switched to this ipl from a different ipl 224611860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl 224711860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 61594 49.04% 100.00% # number of times we switched to this ipl from a different ipl 224811860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 125609 # number of times we switched to this ipl from a different ipl 224911860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1865241808000 97.65% 97.65% # number of cycles we spent at this ipl 225011860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 64326000 0.00% 97.65% # number of cycles we spent at this ipl 225111860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 577244500 0.03% 97.68% # number of cycles we spent at this ipl 225211860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 87620000 0.00% 97.69% # number of cycles we spent at this ipl 225311860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 44188694000 2.31% 100.00% # number of cycles we spent at this ipl 225411860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1910159692500 # number of cycles we spent at this ipl 225511860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.983835 # fraction of swpipl calls that actually changed the ipl 22568464SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 22578464SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 22588464SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 225911860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.677729 # fraction of swpipl calls that actually changed the ipl 226011860Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.805635 # fraction of swpipl calls that actually changed the ipl 22618464SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 226211860Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed 226311680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed 226411680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed 226511680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed 226611860Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed 226711680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed 226811860Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed 226911860Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 149358 91.35% 93.61% # number of callpals executed 227011860Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 5686 3.48% 97.09% # number of callpals executed 227111680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed 227211680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed 227311754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed 227411680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed 227511860Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4314 2.64% 99.73% # number of callpals executed 227611680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed 227711606Sandreas.sandberg@arm.comsystem.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed 227811860Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 163506 # number of callpals executed 227911860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6667 # number of protection mode switches 228011860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1071 # number of protection mode switches 22818464SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 228211860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1071 228311860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1071 22848464SN/Asystem.cpu0.kern.mode_good::idle 0 228511860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.160642 # fraction of useful protection mode switches 22868464SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 22878983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 228811860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.276816 # fraction of useful protection mode switches 228911860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1908119380500 99.91% 99.91% # number of ticks spent at the given mode 229011860Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1686628500 0.09% 100.00% # number of ticks spent at the given mode 22918464SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 229211860Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3350 # number of times the context was actually changed 22938464SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 229411860Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2544 # number of quiesce instructions executed 229511860Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 62917 # number of hwrei instructions executed 229611860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 19565 37.60% 37.60% # number of times we switched to this ipl 229711860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1926 3.70% 41.30% # number of times we switched to this ipl 229811860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl 229911860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 30256 58.14% 100.00% # number of times we switched to this ipl 230011860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 52040 # number of times we switched to this ipl 230111860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 19203 47.61% 47.61% # number of times we switched to this ipl from a different ipl 230211860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1926 4.78% 52.39% # number of times we switched to this ipl from a different ipl 230311860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl 230411860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 18910 46.89% 100.00% # number of times we switched to this ipl from a different ipl 230511860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 40332 # number of times we switched to this ipl from a different ipl 230611860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1875855078000 98.19% 98.19% # number of cycles we spent at this ipl 230711860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 566007000 0.03% 98.22% # number of cycles we spent at this ipl 230811860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 141529500 0.01% 98.23% # number of cycles we spent at this ipl 230911860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 33893640500 1.77% 100.00% # number of cycles we spent at this ipl 231011860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1910456255000 # number of cycles we spent at this ipl 231111860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.981498 # fraction of swpipl calls that actually changed the ipl 23128464SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 23138464SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 231411860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.625000 # fraction of swpipl calls that actually changed the ipl 231511860Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.775019 # fraction of swpipl calls that actually changed the ipl 23168464SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 231711860Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed 231811606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 231911606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 232011860Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed 232111680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed 232211680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed 232311860Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 46571 85.30% 87.91% # number of callpals executed 232411860Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 3080 5.64% 93.55% # number of callpals executed 232511754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed 232611754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed 232711860Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed 232811680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed 232911860Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 3249 5.95% 99.52% # number of callpals executed 233011680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed 233111606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed 23328464SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 233311860Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 54596 # number of callpals executed 233411754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches 233511860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 669 # number of protection mode switches 233611860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2431 # number of protection mode switches 233711860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 888 233811860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 669 233911860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 219 234011860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.522353 # fraction of useful protection mode switches 23418464SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 234211860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.090086 # fraction of useful protection mode switches 234311860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.370000 # fraction of useful protection mode switches 234411860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 5325548500 0.28% 0.28% # number of ticks spent at the given mode 234511860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 1057057500 0.06% 0.33% # number of ticks spent at the given mode 234611860Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1904073641000 99.67% 100.00% # number of ticks spent at the given mode 234711860Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 1229 # number of times the context was actually changed 23485703SN/A 23495703SN/A---------- End Simulation Statistics ---------- 2350