config.ini revision 9481:b0fa6b872f40
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000 15console=/scratch/nilay/GEM5/system/binaries/console 16init_param=0 17kernel=/scratch/nilay/GEM5/system/binaries/vmlinux 18load_addr_mask=1099511627775 19mem_mode=timing 20mem_ranges=0:134217727 21memories=system.physmem 22num_work_ids=16 23pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 24readfile=tests/halt.sh 25symbolfile= 26system_rev=1024 27system_type=34 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39clock=1000 40delay=50000 41ranges=8796093022208:18446744073709551615 42req_size=16 43resp_size=16 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cpu0] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu0.branchPred 59cachePorts=200 60checker=Null 61clock=500 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu0.dtb 76fetchToDecodeDelay=1 77fetchTrapLatency=1 78fetchWidth=8 79forwardComSize=5 80fuPool=system.cpu0.fuPool 81function_trace=false 82function_trace_start=0 83iewToCommitDelay=1 84iewToDecodeDelay=1 85iewToFetchDelay=1 86iewToRenameDelay=1 87interrupts=system.cpu0.interrupts 88isa=system.cpu0.isa 89issueToExecuteDelay=1 90issueWidth=8 91itb=system.cpu0.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysFloatRegs=256 99numPhysIntRegs=256 100numROBEntries=192 101numRobs=1 102numThreads=1 103profile=0 104progress_interval=0 105renameToDecodeDelay=1 106renameToFetchDelay=1 107renameToIEWDelay=2 108renameToROBDelay=1 109renameWidth=8 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 119squashWidth=8 120store_set_clear_period=250000 121switched_out=false 122system=system 123tracer=system.cpu0.tracer 124trapLatency=13 125wbDepth=1 126wbWidth=8 127workload= 128dcache_port=system.cpu0.dcache.cpu_side 129icache_port=system.cpu0.icache.cpu_side 130 131[system.cpu0.branchPred] 132type=BranchPredictor 133BTBEntries=4096 134BTBTagSize=16 135RASSize=16 136choiceCtrBits=2 137choicePredictorSize=8192 138globalCtrBits=2 139globalHistoryBits=13 140globalPredictorSize=8192 141instShiftAmt=2 142localCtrBits=2 143localHistoryBits=11 144localHistoryTableSize=2048 145localPredictorSize=2048 146numThreads=1 147predType=tournament 148 149[system.cpu0.dcache] 150type=BaseCache 151addr_ranges=0:18446744073709551615 152assoc=4 153block_size=64 154clock=500 155forward_snoops=true 156hit_latency=2 157is_top_level=true 158max_miss_count=0 159mshrs=4 160prefetch_on_access=false 161prefetcher=Null 162response_latency=2 163size=32768 164system=system 165tgts_per_mshr=20 166two_queue=false 167write_buffers=8 168cpu_side=system.cpu0.dcache_port 169mem_side=system.toL2Bus.slave[1] 170 171[system.cpu0.dtb] 172type=AlphaTLB 173size=64 174 175[system.cpu0.fuPool] 176type=FUPool 177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 178FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 179 180[system.cpu0.fuPool.FUList0] 181type=FUDesc 182children=opList 183count=6 184opList=system.cpu0.fuPool.FUList0.opList 185 186[system.cpu0.fuPool.FUList0.opList] 187type=OpDesc 188issueLat=1 189opClass=IntAlu 190opLat=1 191 192[system.cpu0.fuPool.FUList1] 193type=FUDesc 194children=opList0 opList1 195count=2 196opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 197 198[system.cpu0.fuPool.FUList1.opList0] 199type=OpDesc 200issueLat=1 201opClass=IntMult 202opLat=3 203 204[system.cpu0.fuPool.FUList1.opList1] 205type=OpDesc 206issueLat=19 207opClass=IntDiv 208opLat=20 209 210[system.cpu0.fuPool.FUList2] 211type=FUDesc 212children=opList0 opList1 opList2 213count=4 214opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 215 216[system.cpu0.fuPool.FUList2.opList0] 217type=OpDesc 218issueLat=1 219opClass=FloatAdd 220opLat=2 221 222[system.cpu0.fuPool.FUList2.opList1] 223type=OpDesc 224issueLat=1 225opClass=FloatCmp 226opLat=2 227 228[system.cpu0.fuPool.FUList2.opList2] 229type=OpDesc 230issueLat=1 231opClass=FloatCvt 232opLat=2 233 234[system.cpu0.fuPool.FUList3] 235type=FUDesc 236children=opList0 opList1 opList2 237count=2 238opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 239 240[system.cpu0.fuPool.FUList3.opList0] 241type=OpDesc 242issueLat=1 243opClass=FloatMult 244opLat=4 245 246[system.cpu0.fuPool.FUList3.opList1] 247type=OpDesc 248issueLat=12 249opClass=FloatDiv 250opLat=12 251 252[system.cpu0.fuPool.FUList3.opList2] 253type=OpDesc 254issueLat=24 255opClass=FloatSqrt 256opLat=24 257 258[system.cpu0.fuPool.FUList4] 259type=FUDesc 260children=opList 261count=0 262opList=system.cpu0.fuPool.FUList4.opList 263 264[system.cpu0.fuPool.FUList4.opList] 265type=OpDesc 266issueLat=1 267opClass=MemRead 268opLat=1 269 270[system.cpu0.fuPool.FUList5] 271type=FUDesc 272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 273count=4 274opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 275 276[system.cpu0.fuPool.FUList5.opList00] 277type=OpDesc 278issueLat=1 279opClass=SimdAdd 280opLat=1 281 282[system.cpu0.fuPool.FUList5.opList01] 283type=OpDesc 284issueLat=1 285opClass=SimdAddAcc 286opLat=1 287 288[system.cpu0.fuPool.FUList5.opList02] 289type=OpDesc 290issueLat=1 291opClass=SimdAlu 292opLat=1 293 294[system.cpu0.fuPool.FUList5.opList03] 295type=OpDesc 296issueLat=1 297opClass=SimdCmp 298opLat=1 299 300[system.cpu0.fuPool.FUList5.opList04] 301type=OpDesc 302issueLat=1 303opClass=SimdCvt 304opLat=1 305 306[system.cpu0.fuPool.FUList5.opList05] 307type=OpDesc 308issueLat=1 309opClass=SimdMisc 310opLat=1 311 312[system.cpu0.fuPool.FUList5.opList06] 313type=OpDesc 314issueLat=1 315opClass=SimdMult 316opLat=1 317 318[system.cpu0.fuPool.FUList5.opList07] 319type=OpDesc 320issueLat=1 321opClass=SimdMultAcc 322opLat=1 323 324[system.cpu0.fuPool.FUList5.opList08] 325type=OpDesc 326issueLat=1 327opClass=SimdShift 328opLat=1 329 330[system.cpu0.fuPool.FUList5.opList09] 331type=OpDesc 332issueLat=1 333opClass=SimdShiftAcc 334opLat=1 335 336[system.cpu0.fuPool.FUList5.opList10] 337type=OpDesc 338issueLat=1 339opClass=SimdSqrt 340opLat=1 341 342[system.cpu0.fuPool.FUList5.opList11] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatAdd 346opLat=1 347 348[system.cpu0.fuPool.FUList5.opList12] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatAlu 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList13] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatCmp 358opLat=1 359 360[system.cpu0.fuPool.FUList5.opList14] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatCvt 364opLat=1 365 366[system.cpu0.fuPool.FUList5.opList15] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatDiv 370opLat=1 371 372[system.cpu0.fuPool.FUList5.opList16] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMisc 376opLat=1 377 378[system.cpu0.fuPool.FUList5.opList17] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatMult 382opLat=1 383 384[system.cpu0.fuPool.FUList5.opList18] 385type=OpDesc 386issueLat=1 387opClass=SimdFloatMultAcc 388opLat=1 389 390[system.cpu0.fuPool.FUList5.opList19] 391type=OpDesc 392issueLat=1 393opClass=SimdFloatSqrt 394opLat=1 395 396[system.cpu0.fuPool.FUList6] 397type=FUDesc 398children=opList 399count=0 400opList=system.cpu0.fuPool.FUList6.opList 401 402[system.cpu0.fuPool.FUList6.opList] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu0.fuPool.FUList7] 409type=FUDesc 410children=opList0 opList1 411count=4 412opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 413 414[system.cpu0.fuPool.FUList7.opList0] 415type=OpDesc 416issueLat=1 417opClass=MemRead 418opLat=1 419 420[system.cpu0.fuPool.FUList7.opList1] 421type=OpDesc 422issueLat=1 423opClass=MemWrite 424opLat=1 425 426[system.cpu0.fuPool.FUList8] 427type=FUDesc 428children=opList 429count=1 430opList=system.cpu0.fuPool.FUList8.opList 431 432[system.cpu0.fuPool.FUList8.opList] 433type=OpDesc 434issueLat=3 435opClass=IprAccess 436opLat=3 437 438[system.cpu0.icache] 439type=BaseCache 440addr_ranges=0:18446744073709551615 441assoc=1 442block_size=64 443clock=500 444forward_snoops=true 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451response_latency=2 452size=32768 453system=system 454tgts_per_mshr=20 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu0.icache_port 458mem_side=system.toL2Bus.slave[0] 459 460[system.cpu0.interrupts] 461type=AlphaInterrupts 462 463[system.cpu0.isa] 464type=AlphaISA 465 466[system.cpu0.itb] 467type=AlphaTLB 468size=48 469 470[system.cpu0.tracer] 471type=ExeTracer 472 473[system.cpu1] 474type=DerivO3CPU 475children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 476LFSTSize=1024 477LQEntries=32 478LSQCheckLoads=true 479LSQDepCheckShift=4 480SQEntries=32 481SSITSize=1024 482activity=0 483backComSize=5 484branchPred=system.cpu1.branchPred 485cachePorts=200 486checker=Null 487clock=500 488commitToDecodeDelay=1 489commitToFetchDelay=1 490commitToIEWDelay=1 491commitToRenameDelay=1 492commitWidth=8 493cpu_id=1 494decodeToFetchDelay=1 495decodeToRenameDelay=1 496decodeWidth=8 497dispatchWidth=8 498do_checkpoint_insts=true 499do_quiesce=true 500do_statistics_insts=true 501dtb=system.cpu1.dtb 502fetchToDecodeDelay=1 503fetchTrapLatency=1 504fetchWidth=8 505forwardComSize=5 506fuPool=system.cpu1.fuPool 507function_trace=false 508function_trace_start=0 509iewToCommitDelay=1 510iewToDecodeDelay=1 511iewToFetchDelay=1 512iewToRenameDelay=1 513interrupts=system.cpu1.interrupts 514isa=system.cpu1.isa 515issueToExecuteDelay=1 516issueWidth=8 517itb=system.cpu1.itb 518max_insts_all_threads=0 519max_insts_any_thread=0 520max_loads_all_threads=0 521max_loads_any_thread=0 522needsTSO=false 523numIQEntries=64 524numPhysFloatRegs=256 525numPhysIntRegs=256 526numROBEntries=192 527numRobs=1 528numThreads=1 529profile=0 530progress_interval=0 531renameToDecodeDelay=1 532renameToFetchDelay=1 533renameToIEWDelay=2 534renameToROBDelay=1 535renameWidth=8 536smtCommitPolicy=RoundRobin 537smtFetchPolicy=SingleThread 538smtIQPolicy=Partitioned 539smtIQThreshold=100 540smtLSQPolicy=Partitioned 541smtLSQThreshold=100 542smtNumFetchingThreads=1 543smtROBPolicy=Partitioned 544smtROBThreshold=100 545squashWidth=8 546store_set_clear_period=250000 547switched_out=false 548system=system 549tracer=system.cpu1.tracer 550trapLatency=13 551wbDepth=1 552wbWidth=8 553workload= 554dcache_port=system.cpu1.dcache.cpu_side 555icache_port=system.cpu1.icache.cpu_side 556 557[system.cpu1.branchPred] 558type=BranchPredictor 559BTBEntries=4096 560BTBTagSize=16 561RASSize=16 562choiceCtrBits=2 563choicePredictorSize=8192 564globalCtrBits=2 565globalHistoryBits=13 566globalPredictorSize=8192 567instShiftAmt=2 568localCtrBits=2 569localHistoryBits=11 570localHistoryTableSize=2048 571localPredictorSize=2048 572numThreads=1 573predType=tournament 574 575[system.cpu1.dcache] 576type=BaseCache 577addr_ranges=0:18446744073709551615 578assoc=4 579block_size=64 580clock=500 581forward_snoops=true 582hit_latency=2 583is_top_level=true 584max_miss_count=0 585mshrs=4 586prefetch_on_access=false 587prefetcher=Null 588response_latency=2 589size=32768 590system=system 591tgts_per_mshr=20 592two_queue=false 593write_buffers=8 594cpu_side=system.cpu1.dcache_port 595mem_side=system.toL2Bus.slave[3] 596 597[system.cpu1.dtb] 598type=AlphaTLB 599size=64 600 601[system.cpu1.fuPool] 602type=FUPool 603children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 604FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 605 606[system.cpu1.fuPool.FUList0] 607type=FUDesc 608children=opList 609count=6 610opList=system.cpu1.fuPool.FUList0.opList 611 612[system.cpu1.fuPool.FUList0.opList] 613type=OpDesc 614issueLat=1 615opClass=IntAlu 616opLat=1 617 618[system.cpu1.fuPool.FUList1] 619type=FUDesc 620children=opList0 opList1 621count=2 622opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 623 624[system.cpu1.fuPool.FUList1.opList0] 625type=OpDesc 626issueLat=1 627opClass=IntMult 628opLat=3 629 630[system.cpu1.fuPool.FUList1.opList1] 631type=OpDesc 632issueLat=19 633opClass=IntDiv 634opLat=20 635 636[system.cpu1.fuPool.FUList2] 637type=FUDesc 638children=opList0 opList1 opList2 639count=4 640opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 641 642[system.cpu1.fuPool.FUList2.opList0] 643type=OpDesc 644issueLat=1 645opClass=FloatAdd 646opLat=2 647 648[system.cpu1.fuPool.FUList2.opList1] 649type=OpDesc 650issueLat=1 651opClass=FloatCmp 652opLat=2 653 654[system.cpu1.fuPool.FUList2.opList2] 655type=OpDesc 656issueLat=1 657opClass=FloatCvt 658opLat=2 659 660[system.cpu1.fuPool.FUList3] 661type=FUDesc 662children=opList0 opList1 opList2 663count=2 664opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 665 666[system.cpu1.fuPool.FUList3.opList0] 667type=OpDesc 668issueLat=1 669opClass=FloatMult 670opLat=4 671 672[system.cpu1.fuPool.FUList3.opList1] 673type=OpDesc 674issueLat=12 675opClass=FloatDiv 676opLat=12 677 678[system.cpu1.fuPool.FUList3.opList2] 679type=OpDesc 680issueLat=24 681opClass=FloatSqrt 682opLat=24 683 684[system.cpu1.fuPool.FUList4] 685type=FUDesc 686children=opList 687count=0 688opList=system.cpu1.fuPool.FUList4.opList 689 690[system.cpu1.fuPool.FUList4.opList] 691type=OpDesc 692issueLat=1 693opClass=MemRead 694opLat=1 695 696[system.cpu1.fuPool.FUList5] 697type=FUDesc 698children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 699count=4 700opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 701 702[system.cpu1.fuPool.FUList5.opList00] 703type=OpDesc 704issueLat=1 705opClass=SimdAdd 706opLat=1 707 708[system.cpu1.fuPool.FUList5.opList01] 709type=OpDesc 710issueLat=1 711opClass=SimdAddAcc 712opLat=1 713 714[system.cpu1.fuPool.FUList5.opList02] 715type=OpDesc 716issueLat=1 717opClass=SimdAlu 718opLat=1 719 720[system.cpu1.fuPool.FUList5.opList03] 721type=OpDesc 722issueLat=1 723opClass=SimdCmp 724opLat=1 725 726[system.cpu1.fuPool.FUList5.opList04] 727type=OpDesc 728issueLat=1 729opClass=SimdCvt 730opLat=1 731 732[system.cpu1.fuPool.FUList5.opList05] 733type=OpDesc 734issueLat=1 735opClass=SimdMisc 736opLat=1 737 738[system.cpu1.fuPool.FUList5.opList06] 739type=OpDesc 740issueLat=1 741opClass=SimdMult 742opLat=1 743 744[system.cpu1.fuPool.FUList5.opList07] 745type=OpDesc 746issueLat=1 747opClass=SimdMultAcc 748opLat=1 749 750[system.cpu1.fuPool.FUList5.opList08] 751type=OpDesc 752issueLat=1 753opClass=SimdShift 754opLat=1 755 756[system.cpu1.fuPool.FUList5.opList09] 757type=OpDesc 758issueLat=1 759opClass=SimdShiftAcc 760opLat=1 761 762[system.cpu1.fuPool.FUList5.opList10] 763type=OpDesc 764issueLat=1 765opClass=SimdSqrt 766opLat=1 767 768[system.cpu1.fuPool.FUList5.opList11] 769type=OpDesc 770issueLat=1 771opClass=SimdFloatAdd 772opLat=1 773 774[system.cpu1.fuPool.FUList5.opList12] 775type=OpDesc 776issueLat=1 777opClass=SimdFloatAlu 778opLat=1 779 780[system.cpu1.fuPool.FUList5.opList13] 781type=OpDesc 782issueLat=1 783opClass=SimdFloatCmp 784opLat=1 785 786[system.cpu1.fuPool.FUList5.opList14] 787type=OpDesc 788issueLat=1 789opClass=SimdFloatCvt 790opLat=1 791 792[system.cpu1.fuPool.FUList5.opList15] 793type=OpDesc 794issueLat=1 795opClass=SimdFloatDiv 796opLat=1 797 798[system.cpu1.fuPool.FUList5.opList16] 799type=OpDesc 800issueLat=1 801opClass=SimdFloatMisc 802opLat=1 803 804[system.cpu1.fuPool.FUList5.opList17] 805type=OpDesc 806issueLat=1 807opClass=SimdFloatMult 808opLat=1 809 810[system.cpu1.fuPool.FUList5.opList18] 811type=OpDesc 812issueLat=1 813opClass=SimdFloatMultAcc 814opLat=1 815 816[system.cpu1.fuPool.FUList5.opList19] 817type=OpDesc 818issueLat=1 819opClass=SimdFloatSqrt 820opLat=1 821 822[system.cpu1.fuPool.FUList6] 823type=FUDesc 824children=opList 825count=0 826opList=system.cpu1.fuPool.FUList6.opList 827 828[system.cpu1.fuPool.FUList6.opList] 829type=OpDesc 830issueLat=1 831opClass=MemWrite 832opLat=1 833 834[system.cpu1.fuPool.FUList7] 835type=FUDesc 836children=opList0 opList1 837count=4 838opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 839 840[system.cpu1.fuPool.FUList7.opList0] 841type=OpDesc 842issueLat=1 843opClass=MemRead 844opLat=1 845 846[system.cpu1.fuPool.FUList7.opList1] 847type=OpDesc 848issueLat=1 849opClass=MemWrite 850opLat=1 851 852[system.cpu1.fuPool.FUList8] 853type=FUDesc 854children=opList 855count=1 856opList=system.cpu1.fuPool.FUList8.opList 857 858[system.cpu1.fuPool.FUList8.opList] 859type=OpDesc 860issueLat=3 861opClass=IprAccess 862opLat=3 863 864[system.cpu1.icache] 865type=BaseCache 866addr_ranges=0:18446744073709551615 867assoc=1 868block_size=64 869clock=500 870forward_snoops=true 871hit_latency=2 872is_top_level=true 873max_miss_count=0 874mshrs=4 875prefetch_on_access=false 876prefetcher=Null 877response_latency=2 878size=32768 879system=system 880tgts_per_mshr=20 881two_queue=false 882write_buffers=8 883cpu_side=system.cpu1.icache_port 884mem_side=system.toL2Bus.slave[2] 885 886[system.cpu1.interrupts] 887type=AlphaInterrupts 888 889[system.cpu1.isa] 890type=AlphaISA 891 892[system.cpu1.itb] 893type=AlphaTLB 894size=48 895 896[system.cpu1.tracer] 897type=ExeTracer 898 899[system.disk0] 900type=IdeDisk 901children=image 902delay=1000000 903driveID=master 904image=system.disk0.image 905 906[system.disk0.image] 907type=CowDiskImage 908children=child 909child=system.disk0.image.child 910image_file= 911read_only=false 912table_size=65536 913 914[system.disk0.image.child] 915type=RawDiskImage 916image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img 917read_only=true 918 919[system.disk2] 920type=IdeDisk 921children=image 922delay=1000000 923driveID=master 924image=system.disk2.image 925 926[system.disk2.image] 927type=CowDiskImage 928children=child 929child=system.disk2.image.child 930image_file= 931read_only=false 932table_size=65536 933 934[system.disk2.image.child] 935type=RawDiskImage 936image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img 937read_only=true 938 939[system.intrctrl] 940type=IntrControl 941sys=system 942 943[system.iobus] 944type=NoncoherentBus 945block_size=64 946clock=1000 947header_cycles=1 948use_default_range=true 949width=8 950default=system.tsunami.pciconfig.pio 951master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 952slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 953 954[system.iocache] 955type=BaseCache 956addr_ranges=0:134217727 957assoc=8 958block_size=64 959clock=1000 960forward_snoops=false 961hit_latency=50 962is_top_level=true 963max_miss_count=0 964mshrs=20 965prefetch_on_access=false 966prefetcher=Null 967response_latency=50 968size=1024 969system=system 970tgts_per_mshr=12 971two_queue=false 972write_buffers=8 973cpu_side=system.iobus.master[29] 974mem_side=system.membus.slave[2] 975 976[system.l2c] 977type=BaseCache 978addr_ranges=0:18446744073709551615 979assoc=8 980block_size=64 981clock=500 982forward_snoops=true 983hit_latency=20 984is_top_level=false 985max_miss_count=0 986mshrs=20 987prefetch_on_access=false 988prefetcher=Null 989response_latency=20 990size=4194304 991system=system 992tgts_per_mshr=12 993two_queue=false 994write_buffers=8 995cpu_side=system.toL2Bus.master[0] 996mem_side=system.membus.slave[1] 997 998[system.membus] 999type=CoherentBus 1000children=badaddr_responder 1001block_size=64 1002clock=1000 1003header_cycles=1 1004use_default_range=false 1005width=8 1006default=system.membus.badaddr_responder.pio 1007master=system.bridge.slave system.physmem.port 1008slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1009 1010[system.membus.badaddr_responder] 1011type=IsaFake 1012clock=1000 1013fake_mem=false 1014pio_addr=0 1015pio_latency=100000 1016pio_size=8 1017ret_bad_addr=true 1018ret_data16=65535 1019ret_data32=4294967295 1020ret_data64=18446744073709551615 1021ret_data8=255 1022system=system 1023update_data=false 1024warn_access= 1025pio=system.membus.default 1026 1027[system.physmem] 1028type=SimpleDRAM 1029addr_mapping=openmap 1030banks_per_rank=8 1031clock=1000 1032conf_table_reported=false 1033in_addr_map=true 1034lines_per_rowbuffer=64 1035mem_sched_policy=fcfs 1036null=false 1037page_policy=open 1038range=0:134217727 1039ranks_per_channel=2 1040read_buffer_size=32 1041tBURST=4000 1042tCL=14000 1043tRCD=14000 1044tREFI=7800000 1045tRFC=300000 1046tRP=14000 1047tWTR=1000 1048write_buffer_size=32 1049write_thresh_perc=70 1050zero=false 1051port=system.membus.master[1] 1052 1053[system.simple_disk] 1054type=SimpleDisk 1055children=disk 1056disk=system.simple_disk.disk 1057system=system 1058 1059[system.simple_disk.disk] 1060type=RawDiskImage 1061image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img 1062read_only=true 1063 1064[system.terminal] 1065type=Terminal 1066intr_control=system.intrctrl 1067number=0 1068output=true 1069port=3456 1070 1071[system.toL2Bus] 1072type=CoherentBus 1073block_size=64 1074clock=500 1075header_cycles=1 1076use_default_range=false 1077width=8 1078master=system.l2c.cpu_side 1079slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1080 1081[system.tsunami] 1082type=Tsunami 1083children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1084intrctrl=system.intrctrl 1085system=system 1086 1087[system.tsunami.backdoor] 1088type=AlphaBackdoor 1089clock=1000 1090cpu=system.cpu0 1091disk=system.simple_disk 1092pio_addr=8804682956800 1093pio_latency=100000 1094platform=system.tsunami 1095system=system 1096terminal=system.terminal 1097pio=system.iobus.master[24] 1098 1099[system.tsunami.cchip] 1100type=TsunamiCChip 1101clock=1000 1102pio_addr=8803072344064 1103pio_latency=100000 1104system=system 1105tsunami=system.tsunami 1106pio=system.iobus.master[0] 1107 1108[system.tsunami.ethernet] 1109type=NSGigE 1110BAR0=1 1111BAR0LegacyIO=false 1112BAR0Size=256 1113BAR1=0 1114BAR1LegacyIO=false 1115BAR1Size=4096 1116BAR2=0 1117BAR2LegacyIO=false 1118BAR2Size=0 1119BAR3=0 1120BAR3LegacyIO=false 1121BAR3Size=0 1122BAR4=0 1123BAR4LegacyIO=false 1124BAR4Size=0 1125BAR5=0 1126BAR5LegacyIO=false 1127BAR5Size=0 1128BIST=0 1129CacheLineSize=0 1130CardbusCIS=0 1131ClassCode=2 1132Command=0 1133DeviceID=34 1134ExpansionROM=0 1135HeaderType=0 1136InterruptLine=30 1137InterruptPin=1 1138LatencyTimer=0 1139MaximumLatency=52 1140MinimumGrant=176 1141ProgIF=0 1142Revision=0 1143Status=656 1144SubClassCode=0 1145SubsystemID=0 1146SubsystemVendorID=0 1147VendorID=4107 1148clock=2000 1149config_latency=20000 1150dma_data_free=false 1151dma_desc_free=false 1152dma_no_allocate=true 1153dma_read_delay=0 1154dma_read_factor=0 1155dma_write_delay=0 1156dma_write_factor=0 1157hardware_address=00:90:00:00:00:01 1158intr_delay=10000000 1159pci_bus=0 1160pci_dev=1 1161pci_func=0 1162pio_latency=30000 1163platform=system.tsunami 1164rss=false 1165rx_delay=1000000 1166rx_fifo_size=524288 1167rx_filter=true 1168rx_thread=false 1169system=system 1170tx_delay=1000000 1171tx_fifo_size=524288 1172tx_thread=false 1173config=system.iobus.master[28] 1174dma=system.iobus.slave[2] 1175pio=system.iobus.master[27] 1176 1177[system.tsunami.fake_OROM] 1178type=IsaFake 1179clock=1000 1180fake_mem=false 1181pio_addr=8796093677568 1182pio_latency=100000 1183pio_size=393216 1184ret_bad_addr=false 1185ret_data16=65535 1186ret_data32=4294967295 1187ret_data64=18446744073709551615 1188ret_data8=255 1189system=system 1190update_data=false 1191warn_access= 1192pio=system.iobus.master[8] 1193 1194[system.tsunami.fake_ata0] 1195type=IsaFake 1196clock=1000 1197fake_mem=false 1198pio_addr=8804615848432 1199pio_latency=100000 1200pio_size=8 1201ret_bad_addr=false 1202ret_data16=65535 1203ret_data32=4294967295 1204ret_data64=18446744073709551615 1205ret_data8=255 1206system=system 1207update_data=false 1208warn_access= 1209pio=system.iobus.master[19] 1210 1211[system.tsunami.fake_ata1] 1212type=IsaFake 1213clock=1000 1214fake_mem=false 1215pio_addr=8804615848304 1216pio_latency=100000 1217pio_size=8 1218ret_bad_addr=false 1219ret_data16=65535 1220ret_data32=4294967295 1221ret_data64=18446744073709551615 1222ret_data8=255 1223system=system 1224update_data=false 1225warn_access= 1226pio=system.iobus.master[20] 1227 1228[system.tsunami.fake_pnp_addr] 1229type=IsaFake 1230clock=1000 1231fake_mem=false 1232pio_addr=8804615848569 1233pio_latency=100000 1234pio_size=8 1235ret_bad_addr=false 1236ret_data16=65535 1237ret_data32=4294967295 1238ret_data64=18446744073709551615 1239ret_data8=255 1240system=system 1241update_data=false 1242warn_access= 1243pio=system.iobus.master[9] 1244 1245[system.tsunami.fake_pnp_read0] 1246type=IsaFake 1247clock=1000 1248fake_mem=false 1249pio_addr=8804615848451 1250pio_latency=100000 1251pio_size=8 1252ret_bad_addr=false 1253ret_data16=65535 1254ret_data32=4294967295 1255ret_data64=18446744073709551615 1256ret_data8=255 1257system=system 1258update_data=false 1259warn_access= 1260pio=system.iobus.master[11] 1261 1262[system.tsunami.fake_pnp_read1] 1263type=IsaFake 1264clock=1000 1265fake_mem=false 1266pio_addr=8804615848515 1267pio_latency=100000 1268pio_size=8 1269ret_bad_addr=false 1270ret_data16=65535 1271ret_data32=4294967295 1272ret_data64=18446744073709551615 1273ret_data8=255 1274system=system 1275update_data=false 1276warn_access= 1277pio=system.iobus.master[12] 1278 1279[system.tsunami.fake_pnp_read2] 1280type=IsaFake 1281clock=1000 1282fake_mem=false 1283pio_addr=8804615848579 1284pio_latency=100000 1285pio_size=8 1286ret_bad_addr=false 1287ret_data16=65535 1288ret_data32=4294967295 1289ret_data64=18446744073709551615 1290ret_data8=255 1291system=system 1292update_data=false 1293warn_access= 1294pio=system.iobus.master[13] 1295 1296[system.tsunami.fake_pnp_read3] 1297type=IsaFake 1298clock=1000 1299fake_mem=false 1300pio_addr=8804615848643 1301pio_latency=100000 1302pio_size=8 1303ret_bad_addr=false 1304ret_data16=65535 1305ret_data32=4294967295 1306ret_data64=18446744073709551615 1307ret_data8=255 1308system=system 1309update_data=false 1310warn_access= 1311pio=system.iobus.master[14] 1312 1313[system.tsunami.fake_pnp_read4] 1314type=IsaFake 1315clock=1000 1316fake_mem=false 1317pio_addr=8804615848707 1318pio_latency=100000 1319pio_size=8 1320ret_bad_addr=false 1321ret_data16=65535 1322ret_data32=4294967295 1323ret_data64=18446744073709551615 1324ret_data8=255 1325system=system 1326update_data=false 1327warn_access= 1328pio=system.iobus.master[15] 1329 1330[system.tsunami.fake_pnp_read5] 1331type=IsaFake 1332clock=1000 1333fake_mem=false 1334pio_addr=8804615848771 1335pio_latency=100000 1336pio_size=8 1337ret_bad_addr=false 1338ret_data16=65535 1339ret_data32=4294967295 1340ret_data64=18446744073709551615 1341ret_data8=255 1342system=system 1343update_data=false 1344warn_access= 1345pio=system.iobus.master[16] 1346 1347[system.tsunami.fake_pnp_read6] 1348type=IsaFake 1349clock=1000 1350fake_mem=false 1351pio_addr=8804615848835 1352pio_latency=100000 1353pio_size=8 1354ret_bad_addr=false 1355ret_data16=65535 1356ret_data32=4294967295 1357ret_data64=18446744073709551615 1358ret_data8=255 1359system=system 1360update_data=false 1361warn_access= 1362pio=system.iobus.master[17] 1363 1364[system.tsunami.fake_pnp_read7] 1365type=IsaFake 1366clock=1000 1367fake_mem=false 1368pio_addr=8804615848899 1369pio_latency=100000 1370pio_size=8 1371ret_bad_addr=false 1372ret_data16=65535 1373ret_data32=4294967295 1374ret_data64=18446744073709551615 1375ret_data8=255 1376system=system 1377update_data=false 1378warn_access= 1379pio=system.iobus.master[18] 1380 1381[system.tsunami.fake_pnp_write] 1382type=IsaFake 1383clock=1000 1384fake_mem=false 1385pio_addr=8804615850617 1386pio_latency=100000 1387pio_size=8 1388ret_bad_addr=false 1389ret_data16=65535 1390ret_data32=4294967295 1391ret_data64=18446744073709551615 1392ret_data8=255 1393system=system 1394update_data=false 1395warn_access= 1396pio=system.iobus.master[10] 1397 1398[system.tsunami.fake_ppc] 1399type=IsaFake 1400clock=1000 1401fake_mem=false 1402pio_addr=8804615848891 1403pio_latency=100000 1404pio_size=8 1405ret_bad_addr=false 1406ret_data16=65535 1407ret_data32=4294967295 1408ret_data64=18446744073709551615 1409ret_data8=255 1410system=system 1411update_data=false 1412warn_access= 1413pio=system.iobus.master[7] 1414 1415[system.tsunami.fake_sm_chip] 1416type=IsaFake 1417clock=1000 1418fake_mem=false 1419pio_addr=8804615848816 1420pio_latency=100000 1421pio_size=8 1422ret_bad_addr=false 1423ret_data16=65535 1424ret_data32=4294967295 1425ret_data64=18446744073709551615 1426ret_data8=255 1427system=system 1428update_data=false 1429warn_access= 1430pio=system.iobus.master[2] 1431 1432[system.tsunami.fake_uart1] 1433type=IsaFake 1434clock=1000 1435fake_mem=false 1436pio_addr=8804615848696 1437pio_latency=100000 1438pio_size=8 1439ret_bad_addr=false 1440ret_data16=65535 1441ret_data32=4294967295 1442ret_data64=18446744073709551615 1443ret_data8=255 1444system=system 1445update_data=false 1446warn_access= 1447pio=system.iobus.master[3] 1448 1449[system.tsunami.fake_uart2] 1450type=IsaFake 1451clock=1000 1452fake_mem=false 1453pio_addr=8804615848936 1454pio_latency=100000 1455pio_size=8 1456ret_bad_addr=false 1457ret_data16=65535 1458ret_data32=4294967295 1459ret_data64=18446744073709551615 1460ret_data8=255 1461system=system 1462update_data=false 1463warn_access= 1464pio=system.iobus.master[4] 1465 1466[system.tsunami.fake_uart3] 1467type=IsaFake 1468clock=1000 1469fake_mem=false 1470pio_addr=8804615848680 1471pio_latency=100000 1472pio_size=8 1473ret_bad_addr=false 1474ret_data16=65535 1475ret_data32=4294967295 1476ret_data64=18446744073709551615 1477ret_data8=255 1478system=system 1479update_data=false 1480warn_access= 1481pio=system.iobus.master[5] 1482 1483[system.tsunami.fake_uart4] 1484type=IsaFake 1485clock=1000 1486fake_mem=false 1487pio_addr=8804615848944 1488pio_latency=100000 1489pio_size=8 1490ret_bad_addr=false 1491ret_data16=65535 1492ret_data32=4294967295 1493ret_data64=18446744073709551615 1494ret_data8=255 1495system=system 1496update_data=false 1497warn_access= 1498pio=system.iobus.master[6] 1499 1500[system.tsunami.fb] 1501type=BadDevice 1502clock=1000 1503devicename=FrameBuffer 1504pio_addr=8804615848912 1505pio_latency=100000 1506system=system 1507pio=system.iobus.master[21] 1508 1509[system.tsunami.ide] 1510type=IdeController 1511BAR0=1 1512BAR0LegacyIO=false 1513BAR0Size=8 1514BAR1=1 1515BAR1LegacyIO=false 1516BAR1Size=4 1517BAR2=1 1518BAR2LegacyIO=false 1519BAR2Size=8 1520BAR3=1 1521BAR3LegacyIO=false 1522BAR3Size=4 1523BAR4=1 1524BAR4LegacyIO=false 1525BAR4Size=16 1526BAR5=1 1527BAR5LegacyIO=false 1528BAR5Size=0 1529BIST=0 1530CacheLineSize=0 1531CardbusCIS=0 1532ClassCode=1 1533Command=0 1534DeviceID=28945 1535ExpansionROM=0 1536HeaderType=0 1537InterruptLine=31 1538InterruptPin=1 1539LatencyTimer=0 1540MaximumLatency=0 1541MinimumGrant=0 1542ProgIF=133 1543Revision=0 1544Status=640 1545SubClassCode=1 1546SubsystemID=0 1547SubsystemVendorID=0 1548VendorID=32902 1549clock=1000 1550config_latency=20000 1551ctrl_offset=0 1552disks=system.disk0 system.disk2 1553io_shift=0 1554pci_bus=0 1555pci_dev=0 1556pci_func=0 1557pio_latency=30000 1558platform=system.tsunami 1559system=system 1560config=system.iobus.master[26] 1561dma=system.iobus.slave[1] 1562pio=system.iobus.master[25] 1563 1564[system.tsunami.io] 1565type=TsunamiIO 1566clock=1000 1567frequency=976562500 1568pio_addr=8804615847936 1569pio_latency=100000 1570system=system 1571time=Thu Jan 1 00:00:00 2009 1572tsunami=system.tsunami 1573year_is_bcd=false 1574pio=system.iobus.master[22] 1575 1576[system.tsunami.pchip] 1577type=TsunamiPChip 1578clock=1000 1579pio_addr=8802535473152 1580pio_latency=100000 1581system=system 1582tsunami=system.tsunami 1583pio=system.iobus.master[1] 1584 1585[system.tsunami.pciconfig] 1586type=PciConfigAll 1587bus=0 1588clock=1000 1589pio_latency=30000 1590platform=system.tsunami 1591size=16777216 1592system=system 1593pio=system.iobus.default 1594 1595[system.tsunami.uart] 1596type=Uart8250 1597clock=1000 1598pio_addr=8804615848952 1599pio_latency=100000 1600platform=system.tsunami 1601system=system 1602terminal=system.terminal 1603pio=system.iobus.master[23] 1604 1605