stats.txt revision 11687:b3d5f0e9e258
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.893221 # Number of seconds simulated 4sim_ticks 1893220881500 # Number of ticks simulated 5final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 27932 # Simulator instruction rate (inst/s) 8host_op_rate 27932 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 941819152 # Simulator tick rate (ticks/s) 10host_mem_usage 393408 # Number of bytes of host memory used 11host_seconds 2010.17 # Real time elapsed on the host 12sim_insts 56147815 # Number of instructions simulated 13sim_ops 56147815 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 404812 # Number of read requests accepted 45system.physmem.writeReqs 118228 # Number of write requests accepted 46system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 56system.physmem.perBankRdBursts::0 25483 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25705 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25813 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25775 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25223 # Per bank write bursts 61system.physmem.perBankRdBursts::5 24955 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24789 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24583 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25108 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25258 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25518 # Per bank write bursts 67system.physmem.perBankRdBursts::11 24875 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24528 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25564 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25798 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25721 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7829 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7671 # Per bank write bursts 74system.physmem.perBankWrBursts::2 8071 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7745 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7318 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6944 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6788 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6427 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7237 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6873 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7386 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6888 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7081 # Per bank write bursts 85system.physmem.perBankWrBursts::13 8010 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7995 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7945 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 68 # Number of times write queue was full causing retry 90system.physmem.totGap 1893211891000 # Total gap between requests 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) 97system.physmem.readPktSize::6 404812 # Read request sizes (log2) 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) 104system.physmem.writePktSize::6 118228 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 137system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads 256system.physmem.totQLat 5895300250 # Total ticks spent queuing 257system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM 258system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers 259system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst 260system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 261system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst 262system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s 263system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s 264system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s 265system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s 266system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 267system.physmem.busUtil 0.14 # Data bus utilization in percentage 268system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 269system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 270system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 271system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing 272system.physmem.readRowHits 363810 # Number of row buffer hits during reads 273system.physmem.writeRowHits 95775 # Number of row buffer hits during writes 274system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads 275system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes 276system.physmem.avgGap 3619631.18 # Average gap between requests 277system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined 278system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ) 279system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ) 280system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ) 281system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) 282system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ) 283system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ) 284system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ) 285system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ) 286system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ) 287system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ) 288system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ) 289system.physmem_0.averagePower 249.054730 # Core power per rank (mW) 290system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank 291system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states 292system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states 293system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states 294system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states 295system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states 296system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states 297system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ) 298system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ) 299system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) 300system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ) 301system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ) 302system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ) 303system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ) 304system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ) 305system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ) 306system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ) 307system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ) 308system.physmem_1.averagePower 249.269176 # Core power per rank (mW) 309system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank 310system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states 311system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states 312system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states 313system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states 314system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states 315system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states 316system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 317system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 318system.cpu.branchPred.lookups 15264339 # Number of BP lookups 319system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted 320system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect 321system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups 322system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits 323system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 324system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage 325system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target. 326system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions. 327system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups. 328system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits. 329system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses. 330system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches. 331system.cpu_clk_domain.clock 500 # Clock period in ticks 332system.cpu.dtb.fetch_hits 0 # ITB hits 333system.cpu.dtb.fetch_misses 0 # ITB misses 334system.cpu.dtb.fetch_acv 0 # ITB acv 335system.cpu.dtb.fetch_accesses 0 # ITB accesses 336system.cpu.dtb.read_hits 9321681 # DTB read hits 337system.cpu.dtb.read_misses 17691 # DTB read misses 338system.cpu.dtb.read_acv 211 # DTB read access violations 339system.cpu.dtb.read_accesses 764795 # DTB read accesses 340system.cpu.dtb.write_hits 6394158 # DTB write hits 341system.cpu.dtb.write_misses 2442 # DTB write misses 342system.cpu.dtb.write_acv 159 # DTB write access violations 343system.cpu.dtb.write_accesses 298776 # DTB write accesses 344system.cpu.dtb.data_hits 15715839 # DTB hits 345system.cpu.dtb.data_misses 20133 # DTB misses 346system.cpu.dtb.data_acv 370 # DTB access violations 347system.cpu.dtb.data_accesses 1063571 # DTB accesses 348system.cpu.itb.fetch_hits 4020046 # ITB hits 349system.cpu.itb.fetch_misses 6280 # ITB misses 350system.cpu.itb.fetch_acv 699 # ITB acv 351system.cpu.itb.fetch_accesses 4026326 # ITB accesses 352system.cpu.itb.read_hits 0 # DTB read hits 353system.cpu.itb.read_misses 0 # DTB read misses 354system.cpu.itb.read_acv 0 # DTB read access violations 355system.cpu.itb.read_accesses 0 # DTB read accesses 356system.cpu.itb.write_hits 0 # DTB write hits 357system.cpu.itb.write_misses 0 # DTB write misses 358system.cpu.itb.write_acv 0 # DTB write access violations 359system.cpu.itb.write_accesses 0 # DTB write accesses 360system.cpu.itb.data_hits 0 # DTB hits 361system.cpu.itb.data_misses 0 # DTB misses 362system.cpu.itb.data_acv 0 # DTB access violations 363system.cpu.itb.data_accesses 0 # DTB accesses 364system.cpu.numPwrStateTransitions 12752 # Number of power state transitions 365system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state 366system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state 367system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state 368system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state 369system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state 370system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 371system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state 372system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states 373system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states 374system.cpu.numCycles 193121889 # number of cpu cycles simulated 375system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 376system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 377system.cpu.committedInsts 56147815 # Number of instructions committed 378system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed 379system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit 380system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching 381system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 382system.cpu.cpi 3.439526 # CPI: cycles per instruction 383system.cpu.ipc 0.290738 # IPC: instructions per cycle 384system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction 385system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction 386system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction 387system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 388system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction 389system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 390system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 391system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 392system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction 393system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction 394system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction 395system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction 396system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction 397system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction 398system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction 399system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction 400system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction 401system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction 402system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction 403system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction 404system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction 405system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction 406system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction 407system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction 408system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction 409system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction 410system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction 411system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction 412system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction 413system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction 414system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction 415system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction 416system.cpu.op_class_0::MemRead 9175906 16.34% 86.70% # Class of committed instruction 417system.cpu.op_class_0::MemWrite 6235361 11.11% 97.80% # Class of committed instruction 418system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction 419system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction 420system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction 421system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 422system.cpu.op_class_0::total 56147815 # Class of committed instruction 423system.cpu.kern.inst.arm 0 # number of arm instructions executed 424system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 425system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed 426system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl 427system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl 428system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl 429system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl 430system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl 431system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl 432system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 433system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl 434system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl 435system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl 436system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl 437system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl 438system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl 439system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl 440system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl 441system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl 442system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 443system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 444system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl 445system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl 446system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 447system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 448system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 449system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 450system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 451system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 452system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 453system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 454system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 455system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 456system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 457system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 458system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 459system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 460system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 461system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 462system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 463system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 464system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 465system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 466system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 467system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 468system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 469system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 470system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 471system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 472system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 473system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 474system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 475system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 476system.cpu.kern.syscall::total 326 # number of syscalls executed 477system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 478system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 479system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 480system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 481system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed 482system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 483system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 484system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed 485system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed 486system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 487system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 488system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 489system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 490system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed 491system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 492system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 493system.cpu.kern.callpal::total 192465 # number of callpals executed 494system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches 495system.cpu.kern.mode_switch::user 1737 # number of protection mode switches 496system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 497system.cpu.kern.mode_good::kernel 1905 498system.cpu.kern.mode_good::user 1737 499system.cpu.kern.mode_good::idle 168 500system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches 501system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 502system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches 503system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches 504system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode 505system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode 506system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode 507system.cpu.kern.swap_context 4174 # number of times the context was actually changed 508system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked 509system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped 510system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 511system.cpu.dcache.tags.replacements 1394246 # number of replacements 512system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use 513system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks. 514system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks. 515system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks. 516system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. 517system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor 518system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy 519system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy 520system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 521system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id 522system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id 523system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 524system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 525system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses 526system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses 527system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 528system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits 529system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits 530system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits 531system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits 532system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits 533system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits 534system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits 535system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits 536system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits 537system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits 538system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits 539system.cpu.dcache.overall_hits::total 13563977 # number of overall hits 540system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses 541system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses 542system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses 543system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses 544system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses 545system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses 546system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses 547system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses 548system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses 549system.cpu.dcache.overall_misses::total 1670044 # number of overall misses 550system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles 551system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles 552system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles 553system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles 554system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles 555system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles 556system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles 557system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles 558system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles 559system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles 560system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses) 561system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses) 562system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses) 563system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses) 564system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses) 565system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses) 566system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses) 567system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses) 568system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses 569system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses 570system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses 571system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses 572system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses 573system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses 574system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses 575system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses 576system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses 577system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses 578system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses 579system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses 580system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses 581system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses 582system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency 583system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency 584system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency 585system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency 586system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency 587system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency 588system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency 589system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency 590system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency 591system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency 592system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 596system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 597system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 598system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks 599system.cpu.dcache.writebacks::total 837664 # number of writebacks 600system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits 601system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits 602system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits 603system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits 604system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 605system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 606system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits 607system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits 608system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits 609system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits 610system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses 611system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses 612system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses 613system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses 614system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses 615system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses 616system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses 617system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses 618system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses 619system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses 620system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 621system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 622system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable 623system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable 624system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses 625system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses 626system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles 627system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles 628system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles 629system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles 630system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles 631system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles 632system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles 633system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles 634system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles 635system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles 636system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles 637system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles 638system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles 639system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles 640system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses 641system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses 642system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses 643system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses 644system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses 645system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses 646system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses 647system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses 648system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses 649system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses 650system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency 651system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency 652system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency 653system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency 654system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency 655system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency 656system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency 657system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency 658system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency 659system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency 660system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency 661system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency 662system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency 663system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency 664system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 665system.cpu.icache.tags.replacements 1477105 # number of replacements 666system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use 667system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks. 668system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks. 669system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks. 670system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit. 671system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor 672system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id 678system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 679system.cpu.icache.tags.tag_accesses 22188623 # Number of tag accesses 680system.cpu.icache.tags.data_accesses 22188623 # Number of data accesses 681system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 682system.cpu.icache.ReadReq_hits::cpu.inst 19233043 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 19233043 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 19233043 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 19233043 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 19233043 # number of overall hits 687system.cpu.icache.overall_hits::total 19233043 # number of overall hits 688system.cpu.icache.ReadReq_misses::cpu.inst 1477790 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 1477790 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 1477790 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 1477790 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 1477790 # number of overall misses 693system.cpu.icache.overall_misses::total 1477790 # number of overall misses 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 20696583500 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 20696583500 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 20696583500 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 20696583500 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 20696583500 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 20696583500 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 20710833 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 20710833 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 20710833 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 20710833 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 20710833 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 20710833 # number of overall (read+write) accesses 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071353 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.071353 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.071353 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.071353 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.071353 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.071353 # miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14005.091048 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 14005.091048 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 14005.091048 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 14005.091048 # average overall miss latency 718system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.writebacks::writebacks 1477105 # number of writebacks 725system.cpu.icache.writebacks::total 1477105 # number of writebacks 726system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477790 # number of ReadReq MSHR misses 727system.cpu.icache.ReadReq_mshr_misses::total 1477790 # number of ReadReq MSHR misses 728system.cpu.icache.demand_mshr_misses::cpu.inst 1477790 # number of demand (read+write) MSHR misses 729system.cpu.icache.demand_mshr_misses::total 1477790 # number of demand (read+write) MSHR misses 730system.cpu.icache.overall_mshr_misses::cpu.inst 1477790 # number of overall MSHR misses 731system.cpu.icache.overall_mshr_misses::total 1477790 # number of overall MSHR misses 732system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19218793500 # number of ReadReq MSHR miss cycles 733system.cpu.icache.ReadReq_mshr_miss_latency::total 19218793500 # number of ReadReq MSHR miss cycles 734system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19218793500 # number of demand (read+write) MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::total 19218793500 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19218793500 # number of overall MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::total 19218793500 # number of overall MSHR miss cycles 738system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for ReadReq accesses 739system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071353 # mshr miss rate for ReadReq accesses 740system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for demand accesses 741system.cpu.icache.demand_mshr_miss_rate::total 0.071353 # mshr miss rate for demand accesses 742system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for overall accesses 743system.cpu.icache.overall_mshr_miss_rate::total 0.071353 # mshr miss rate for overall accesses 744system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13005.091048 # average ReadReq mshr miss latency 745system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048 # average ReadReq mshr miss latency 746system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency 747system.cpu.icache.demand_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency 748system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency 749system.cpu.icache.overall_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency 750system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 751system.cpu.l2cache.tags.replacements 339628 # number of replacements 752system.cpu.l2cache.tags.tagsinuse 65408.612363 # Cycle average of tags in use 753system.cpu.l2cache.tags.total_refs 5336325 # Total number of references to valid blocks. 754system.cpu.l2cache.tags.sampled_refs 405150 # Sample count of references to valid blocks. 755system.cpu.l2cache.tags.avg_refs 13.171233 # Average number of references to valid blocks. 756system.cpu.l2cache.tags.warmup_cycle 6812996000 # Cycle when the warmup percentage was hit. 757system.cpu.l2cache.tags.occ_blocks::writebacks 268.308875 # Average occupied blocks per requestor 758system.cpu.l2cache.tags.occ_blocks::cpu.inst 5785.000603 # Average occupied blocks per requestor 759system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.302886 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy 761system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088272 # Average percentage of cache occupancy 762system.cpu.l2cache.tags.occ_percent::cpu.data 0.905690 # Average percentage of cache occupancy 763system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 765system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 766system.cpu.l2cache.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id 767system.cpu.l2cache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5137 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59344 # Occupied blocks per task id 770system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 771system.cpu.l2cache.tags.tag_accesses 46341016 # Number of tag accesses 772system.cpu.l2cache.tags.data_accesses 46341016 # Number of data accesses 773system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 774system.cpu.l2cache.WritebackDirty_hits::writebacks 837664 # number of WritebackDirty hits 775system.cpu.l2cache.WritebackDirty_hits::total 837664 # number of WritebackDirty hits 776system.cpu.l2cache.WritebackClean_hits::writebacks 1476525 # number of WritebackClean hits 777system.cpu.l2cache.WritebackClean_hits::total 1476525 # number of WritebackClean hits 778system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits 779system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits 780system.cpu.l2cache.ReadExReq_hits::cpu.data 187358 # number of ReadExReq hits 781system.cpu.l2cache.ReadExReq_hits::total 187358 # number of ReadExReq hits 782system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461386 # number of ReadCleanReq hits 783system.cpu.l2cache.ReadCleanReq_hits::total 1461386 # number of ReadCleanReq hits 784system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818548 # number of ReadSharedReq hits 785system.cpu.l2cache.ReadSharedReq_hits::total 818548 # number of ReadSharedReq hits 786system.cpu.l2cache.demand_hits::cpu.inst 1461386 # number of demand (read+write) hits 787system.cpu.l2cache.demand_hits::cpu.data 1005906 # number of demand (read+write) hits 788system.cpu.l2cache.demand_hits::total 2467292 # number of demand (read+write) hits 789system.cpu.l2cache.overall_hits::cpu.inst 1461386 # number of overall hits 790system.cpu.l2cache.overall_hits::cpu.data 1005906 # number of overall hits 791system.cpu.l2cache.overall_hits::total 2467292 # number of overall hits 792system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 793system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 794system.cpu.l2cache.ReadExReq_misses::cpu.data 116652 # number of ReadExReq misses 795system.cpu.l2cache.ReadExReq_misses::total 116652 # number of ReadExReq misses 796system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16348 # number of ReadCleanReq misses 797system.cpu.l2cache.ReadCleanReq_misses::total 16348 # number of ReadCleanReq misses 798system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272226 # number of ReadSharedReq misses 799system.cpu.l2cache.ReadSharedReq_misses::total 272226 # number of ReadSharedReq misses 800system.cpu.l2cache.demand_misses::cpu.inst 16348 # number of demand (read+write) misses 801system.cpu.l2cache.demand_misses::cpu.data 388878 # number of demand (read+write) misses 802system.cpu.l2cache.demand_misses::total 405226 # number of demand (read+write) misses 803system.cpu.l2cache.overall_misses::cpu.inst 16348 # number of overall misses 804system.cpu.l2cache.overall_misses::cpu.data 388878 # number of overall misses 805system.cpu.l2cache.overall_misses::total 405226 # number of overall misses 806system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331000 # number of UpgradeReq miss cycles 807system.cpu.l2cache.UpgradeReq_miss_latency::total 331000 # number of UpgradeReq miss cycles 808system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10499091500 # number of ReadExReq miss cycles 809system.cpu.l2cache.ReadExReq_miss_latency::total 10499091500 # number of ReadExReq miss cycles 810system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1618484000 # number of ReadCleanReq miss cycles 811system.cpu.l2cache.ReadCleanReq_miss_latency::total 1618484000 # number of ReadCleanReq miss cycles 812system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21963269500 # number of ReadSharedReq miss cycles 813system.cpu.l2cache.ReadSharedReq_miss_latency::total 21963269500 # number of ReadSharedReq miss cycles 814system.cpu.l2cache.demand_miss_latency::cpu.inst 1618484000 # number of demand (read+write) miss cycles 815system.cpu.l2cache.demand_miss_latency::cpu.data 32462361000 # number of demand (read+write) miss cycles 816system.cpu.l2cache.demand_miss_latency::total 34080845000 # number of demand (read+write) miss cycles 817system.cpu.l2cache.overall_miss_latency::cpu.inst 1618484000 # number of overall miss cycles 818system.cpu.l2cache.overall_miss_latency::cpu.data 32462361000 # number of overall miss cycles 819system.cpu.l2cache.overall_miss_latency::total 34080845000 # number of overall miss cycles 820system.cpu.l2cache.WritebackDirty_accesses::writebacks 837664 # number of WritebackDirty accesses(hits+misses) 821system.cpu.l2cache.WritebackDirty_accesses::total 837664 # number of WritebackDirty accesses(hits+misses) 822system.cpu.l2cache.WritebackClean_accesses::writebacks 1476525 # number of WritebackClean accesses(hits+misses) 823system.cpu.l2cache.WritebackClean_accesses::total 1476525 # number of WritebackClean accesses(hits+misses) 824system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) 825system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 826system.cpu.l2cache.ReadExReq_accesses::cpu.data 304010 # number of ReadExReq accesses(hits+misses) 827system.cpu.l2cache.ReadExReq_accesses::total 304010 # number of ReadExReq accesses(hits+misses) 828system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477734 # number of ReadCleanReq accesses(hits+misses) 829system.cpu.l2cache.ReadCleanReq_accesses::total 1477734 # number of ReadCleanReq accesses(hits+misses) 830system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090774 # number of ReadSharedReq accesses(hits+misses) 831system.cpu.l2cache.ReadSharedReq_accesses::total 1090774 # number of ReadSharedReq accesses(hits+misses) 832system.cpu.l2cache.demand_accesses::cpu.inst 1477734 # number of demand (read+write) accesses 833system.cpu.l2cache.demand_accesses::cpu.data 1394784 # number of demand (read+write) accesses 834system.cpu.l2cache.demand_accesses::total 2872518 # number of demand (read+write) accesses 835system.cpu.l2cache.overall_accesses::cpu.inst 1477734 # number of overall (read+write) accesses 836system.cpu.l2cache.overall_accesses::cpu.data 1394784 # number of overall (read+write) accesses 837system.cpu.l2cache.overall_accesses::total 2872518 # number of overall (read+write) accesses 838system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses 839system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses 840system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383711 # miss rate for ReadExReq accesses 841system.cpu.l2cache.ReadExReq_miss_rate::total 0.383711 # miss rate for ReadExReq accesses 842system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011063 # miss rate for ReadCleanReq accesses 843system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011063 # miss rate for ReadCleanReq accesses 844system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249571 # miss rate for ReadSharedReq accesses 845system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249571 # miss rate for ReadSharedReq accesses 846system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011063 # miss rate for demand accesses 847system.cpu.l2cache.demand_miss_rate::cpu.data 0.278809 # miss rate for demand accesses 848system.cpu.l2cache.demand_miss_rate::total 0.141070 # miss rate for demand accesses 849system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011063 # miss rate for overall accesses 850system.cpu.l2cache.overall_miss_rate::cpu.data 0.278809 # miss rate for overall accesses 851system.cpu.l2cache.overall_miss_rate::total 0.141070 # miss rate for overall accesses 852system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55166.666667 # average UpgradeReq miss latency 853system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55166.666667 # average UpgradeReq miss latency 854system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90003.527586 # average ReadExReq miss latency 855system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90003.527586 # average ReadExReq miss latency 856system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 99001.957426 # average ReadCleanReq miss latency 857system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 99001.957426 # average ReadCleanReq miss latency 858system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80680.278519 # average ReadSharedReq miss latency 859system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80680.278519 # average ReadSharedReq miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency 862system.cpu.l2cache.demand_avg_miss_latency::total 84103.302848 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::total 84103.302848 # average overall miss latency 866system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu.l2cache.writebacks::writebacks 76716 # number of writebacks 873system.cpu.l2cache.writebacks::total 76716 # number of writebacks 874system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 875system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 876system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116652 # number of ReadExReq MSHR misses 877system.cpu.l2cache.ReadExReq_mshr_misses::total 116652 # number of ReadExReq MSHR misses 878system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16348 # number of ReadCleanReq MSHR misses 879system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16348 # number of ReadCleanReq MSHR misses 880system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272226 # number of ReadSharedReq MSHR misses 881system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272226 # number of ReadSharedReq MSHR misses 882system.cpu.l2cache.demand_mshr_misses::cpu.inst 16348 # number of demand (read+write) MSHR misses 883system.cpu.l2cache.demand_mshr_misses::cpu.data 388878 # number of demand (read+write) MSHR misses 884system.cpu.l2cache.demand_mshr_misses::total 405226 # number of demand (read+write) MSHR misses 885system.cpu.l2cache.overall_mshr_misses::cpu.inst 16348 # number of overall MSHR misses 886system.cpu.l2cache.overall_mshr_misses::cpu.data 388878 # number of overall MSHR misses 887system.cpu.l2cache.overall_mshr_misses::total 405226 # number of overall MSHR misses 888system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 889system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 890system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable 891system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable 892system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses 893system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses 894system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271000 # number of UpgradeReq MSHR miss cycles 895system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271000 # number of UpgradeReq MSHR miss cycles 896system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9332571500 # number of ReadExReq MSHR miss cycles 897system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9332571500 # number of ReadExReq MSHR miss cycles 898system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1455004000 # number of ReadCleanReq MSHR miss cycles 899system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1455004000 # number of ReadCleanReq MSHR miss cycles 900system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19244147500 # number of ReadSharedReq MSHR miss cycles 901system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19244147500 # number of ReadSharedReq MSHR miss cycles 902system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1455004000 # number of demand (read+write) MSHR miss cycles 903system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28576719000 # number of demand (read+write) MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::total 30031723000 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1455004000 # number of overall MSHR miss cycles 906system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28576719000 # number of overall MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::total 30031723000 # number of overall MSHR miss cycles 908system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447540500 # number of ReadReq MSHR uncacheable cycles 909system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447540500 # number of ReadReq MSHR uncacheable cycles 910system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447540500 # number of overall MSHR uncacheable cycles 911system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447540500 # number of overall MSHR uncacheable cycles 912system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses 913system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses 914system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses 915system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses 916system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses 917system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses 918system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses 919system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses 920system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses 921system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses 922system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses 923system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses 924system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses 925system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses 926system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency 927system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency 928system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency 929system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency 930system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency 931system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency 932system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency 933system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency 934system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency 935system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency 936system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency 937system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency 938system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency 939system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency 940system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency 941system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency 942system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency 943system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency 944system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter. 945system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data. 946system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 947system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. 948system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 949system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 950system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 951system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 959system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 960system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution 961system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution 962system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution 963system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution 965system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution 966system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes) 967system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes) 968system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes) 969system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes) 970system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes) 971system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes) 972system.cpu.toL2Bus.snoops 340242 # Total snoops (count) 973system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes) 974system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram 977system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 978system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram 979system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram 980system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 983system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 984system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram 985system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks) 986system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 987system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 988system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 989system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks) 990system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 991system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks) 992system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 993system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 994system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 995system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 996system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 997system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 998system.disk0.dma_write_txs 395 # Number of DMA write transactions. 999system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1000system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1001system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1002system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1003system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1004system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1005system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1006system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1007system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 1008system.iobus.trans_dist::WriteReq 51175 # Transaction distribution 1009system.iobus.trans_dist::WriteResp 51175 # Transaction distribution 1010system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) 1011system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1012system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1013system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1014system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1015system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1016system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1017system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1018system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1019system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes) 1020system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1021system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 1022system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes) 1024system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1025system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1026system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1027system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1028system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1029system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1030system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1031system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1032system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) 1033system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1034system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1035system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) 1036system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks) 1037system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1038system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks) 1039system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1040system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 1041system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1042system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1043system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1044system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) 1045system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1046system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks) 1047system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1048system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) 1049system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1050system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks) 1051system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1052system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 1053system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1054system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks) 1055system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1056system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) 1057system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1058system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1059system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1060system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1061system.iocache.tags.replacements 41685 # number of replacements 1062system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use 1063system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1064system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1065system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1066system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit. 1067system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor 1068system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy 1069system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy 1070system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1071system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1072system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1073system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1074system.iocache.tags.data_accesses 375525 # Number of data accesses 1075system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1076system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1077system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1078system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1079system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1080system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1081system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1082system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1083system.iocache.overall_misses::total 41725 # number of overall misses 1084system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles 1085system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles 1086system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles 1087system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles 1088system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles 1089system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles 1090system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles 1091system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles 1092system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1093system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1094system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1095system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1096system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1097system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1098system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1099system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1100system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1101system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1102system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1103system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1104system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1105system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1106system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1107system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1108system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency 1109system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency 1110system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency 1111system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency 1112system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency 1113system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency 1114system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency 1115system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency 1116system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked 1117system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1118system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked 1119system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1120system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked 1121system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1122system.iocache.writebacks::writebacks 41512 # number of writebacks 1123system.iocache.writebacks::total 41512 # number of writebacks 1124system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1125system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1126system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1127system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1128system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1129system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1130system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1131system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1132system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles 1133system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles 1134system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles 1135system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles 1136system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles 1137system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles 1138system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles 1139system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles 1140system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1141system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1142system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1143system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1144system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1145system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1146system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1147system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1148system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency 1149system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency 1150system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency 1151system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency 1152system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency 1153system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency 1154system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency 1155system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency 1156system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter. 1157system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1158system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1159system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1160system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1161system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1162system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1163system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1164system.membus.trans_dist::ReadResp 295653 # Transaction distribution 1165system.membus.trans_dist::WriteReq 9623 # Transaction distribution 1166system.membus.trans_dist::WriteResp 9623 # Transaction distribution 1167system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution 1168system.membus.trans_dist::CleanEvict 262245 # Transaction distribution 1169system.membus.trans_dist::UpgradeReq 138 # Transaction distribution 1170system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1171system.membus.trans_dist::ReadExReq 116520 # Transaction distribution 1172system.membus.trans_dist::ReadExResp 116520 # Transaction distribution 1173system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution 1174system.membus.trans_dist::BadAddressError 24 # Transaction distribution 1175system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1176system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) 1177system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes) 1178system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) 1179system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes) 1180system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1181system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 1182system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes) 1183system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) 1184system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes) 1185system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes) 1186system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1187system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 1188system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes) 1189system.membus.snoops 434 # Total snoops (count) 1190system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) 1191system.membus.snoop_fanout::samples 463510 # Request fanout histogram 1192system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram 1193system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram 1194system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1195system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram 1196system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram 1197system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1198system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1199system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1200system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1201system.membus.snoop_fanout::total 463510 # Request fanout histogram 1202system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks) 1203system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1204system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks) 1205system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1206system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) 1207system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1208system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks) 1209system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1210system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) 1211system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1212system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1213system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1214system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1215system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1216system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1217system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1218system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1219system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1220system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1221system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1222system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1223system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1224system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1225system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1226system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1227system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1228system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1229system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1230system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1231system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1232system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1233system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1234system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1235system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1236system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1237system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1238system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1239system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1240system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1241system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1242system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1243system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1244system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1245system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1246system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1247system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1248system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1249system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1250system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1251system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1252system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1253system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1254system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1255system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1256system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1257system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1258system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1259system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1260system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1261system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1262system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1263system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1264system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1265system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1266system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1267system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1268system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1269system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1270system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states 1271 1272---------- End Simulation Statistics ---------- 1273