twosys-tsunami-simple-atomic.py revision 9793:6e6cefc1db1f
14661Sksewell@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
25222Sksewell@umich.edu# All rights reserved.
34661Sksewell@umich.edu#
44661Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without
54661Sksewell@umich.edu# modification, are permitted provided that the following conditions are
64661Sksewell@umich.edu# met: redistributions of source code must retain the above copyright
74661Sksewell@umich.edu# notice, this list of conditions and the following disclaimer;
84661Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright
94661Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the
104661Sksewell@umich.edu# documentation and/or other materials provided with the distribution;
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134661Sksewell@umich.edu# this software without specific prior written permission.
144661Sksewell@umich.edu#
154661Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
164661Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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254661Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
264661Sksewell@umich.edu#
274661Sksewell@umich.edu# Authors: Lisa Hsu
284661Sksewell@umich.edu
294661Sksewell@umich.eduimport m5
304661Sksewell@umich.edufrom m5.objects import *
314661Sksewell@umich.edum5.util.addToPath('../configs/common')
324661Sksewell@umich.edufrom FSConfig import *
334661Sksewell@umich.edufrom Benchmarks import *
344661Sksewell@umich.edu
354661Sksewell@umich.edutest_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
364661Sksewell@umich.edu                                 SysConfig('netperf-stream-client.rcS'))
374661Sksewell@umich.edu
384661Sksewell@umich.edu# Create the system clock domain
394661Sksewell@umich.edutest_sys.clk_domain = SrcClockDomain(clock = '1GHz')
404661Sksewell@umich.edu
414661Sksewell@umich.edutest_sys.cpu = AtomicSimpleCPU(cpu_id=0)
424661Sksewell@umich.edu# create the interrupt controller
434661Sksewell@umich.edutest_sys.cpu.createInterruptController()
444661Sksewell@umich.edutest_sys.cpu.connectAllPorts(test_sys.membus)
454661Sksewell@umich.edu
464661Sksewell@umich.edu# Create a seperate clock domain for components that should run at
474661Sksewell@umich.edu# CPUs frequency
484661Sksewell@umich.edutest_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
494661Sksewell@umich.edu
504661Sksewell@umich.edu# Create a separate clock domain for Ethernet
514661Sksewell@umich.edutest_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
524661Sksewell@umich.edu
534661Sksewell@umich.edu# In contrast to the other (one-system) Tsunami configurations we do
544661Sksewell@umich.edu# not have an IO cache but instead rely on an IO bridge for accesses
554661Sksewell@umich.edu# from masters on the IO bus to the memory bus
564661Sksewell@umich.edutest_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
574661Sksewell@umich.edutest_sys.iobridge.slave = test_sys.iobus.master
584661Sksewell@umich.edutest_sys.iobridge.master = test_sys.membus.slave
594661Sksewell@umich.edu
604661Sksewell@umich.edudrive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
614661Sksewell@umich.edu                                 SysConfig('netperf-server.rcS'))
624661Sksewell@umich.edu# Create the system clock domain
634661Sksewell@umich.edudrive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
644661Sksewell@umich.edudrive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
654661Sksewell@umich.edu# create the interrupt controller
664661Sksewell@umich.edudrive_sys.cpu.createInterruptController()
674661Sksewell@umich.edudrive_sys.cpu.connectAllPorts(drive_sys.membus)
684661Sksewell@umich.edu
694661Sksewell@umich.edu# Create a seperate clock domain for components that should run at
704661Sksewell@umich.edu# CPUs frequency
714661Sksewell@umich.edudrive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz')
724661Sksewell@umich.edu
734661Sksewell@umich.edu# Create a separate clock domain for Ethernet
744661Sksewell@umich.edudrive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
754661Sksewell@umich.edu
764661Sksewell@umich.edudrive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
774661Sksewell@umich.edudrive_sys.iobridge.slave = drive_sys.iobus.master
784661Sksewell@umich.edudrive_sys.iobridge.master = drive_sys.membus.slave
794661Sksewell@umich.edu
804661Sksewell@umich.eduroot = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
814661Sksewell@umich.edu
824661Sksewell@umich.edumaxtick = 199999999
834661Sksewell@umich.edu