twosys-tsunami-simple-atomic.py revision 9793:6e6cefc1db1f 
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from FSConfig import *
33from Benchmarks import *
34
35test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
36                                 SysConfig('netperf-stream-client.rcS'))
37
38# Create the system clock domain
39test_sys.clk_domain = SrcClockDomain(clock = '1GHz')
40
41test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
42# create the interrupt controller
43test_sys.cpu.createInterruptController()
44test_sys.cpu.connectAllPorts(test_sys.membus)
45
46# Create a seperate clock domain for components that should run at
47# CPUs frequency
48test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
49
50# Create a separate clock domain for Ethernet
51test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
52
53# In contrast to the other (one-system) Tsunami configurations we do
54# not have an IO cache but instead rely on an IO bridge for accesses
55# from masters on the IO bus to the memory bus
56test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
57test_sys.iobridge.slave = test_sys.iobus.master
58test_sys.iobridge.master = test_sys.membus.slave
59
60drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
61                                 SysConfig('netperf-server.rcS'))
62# Create the system clock domain
63drive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
64drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
65# create the interrupt controller
66drive_sys.cpu.createInterruptController()
67drive_sys.cpu.connectAllPorts(drive_sys.membus)
68
69# Create a seperate clock domain for components that should run at
70# CPUs frequency
71drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz')
72
73# Create a separate clock domain for Ethernet
74drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
75
76drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
77drive_sys.iobridge.slave = drive_sys.iobus.master
78drive_sys.iobridge.master = drive_sys.membus.slave
79
80root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
81
82maxtick = 199999999
83