twosys-tsunami-simple-atomic.py revision 13916:efa5b9e899e3
18968Snilay@cs.wisc.edu# Copyright (c) 2006 The Regents of The University of Michigan 28968Snilay@cs.wisc.edu# All rights reserved. 38968Snilay@cs.wisc.edu# 48968Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 58968Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 68968Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 78968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 88968Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 98968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 108968Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 118968Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 128968Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 138968Snilay@cs.wisc.edu# this software without specific prior written permission. 148968Snilay@cs.wisc.edu# 158968Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168968Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178968Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188968Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198968Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208968Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218968Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228968Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238968Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248968Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258968Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268968Snilay@cs.wisc.edu# 278968Snilay@cs.wisc.edu# Authors: Lisa Hsu 288968Snilay@cs.wisc.edu 298968Snilay@cs.wisc.eduimport m5 308968Snilay@cs.wisc.edufrom m5.objects import * 318968Snilay@cs.wisc.edum5.util.addToPath('../configs/') 328968Snilay@cs.wisc.edufrom common import Benchmarks, FSConfig, SysPaths 338968Snilay@cs.wisc.edu 348968Snilay@cs.wisc.edutest_sys = makeLinuxAlphaSystem('atomic', 358968Snilay@cs.wisc.edu SysConfig('netperf-stream-client.rcS')) 369123Sandreas.hansson@arm.comtest_sys.kernel = SysPaths.binary('vmlinux') 378968Snilay@cs.wisc.edu 388968Snilay@cs.wisc.edu# Dummy voltage domain for all test_sys clock domains 398968Snilay@cs.wisc.edutest_sys.voltage_domain = VoltageDomain() 408968Snilay@cs.wisc.edu 418968Snilay@cs.wisc.edu# Create the system clock domain 428968Snilay@cs.wisc.edutest_sys.clk_domain = SrcClockDomain(clock = '1GHz', 438968Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 448968Snilay@cs.wisc.edu 458968Snilay@cs.wisc.edutest_sys.cpu = AtomicSimpleCPU(cpu_id=0) 468968Snilay@cs.wisc.edu# create the interrupt controller 478968Snilay@cs.wisc.edutest_sys.cpu.createInterruptController() 488968Snilay@cs.wisc.edutest_sys.cpu.connectAllPorts(test_sys.membus) 498968Snilay@cs.wisc.edu 508968Snilay@cs.wisc.edu# Create a seperate clock domain for components that should run at 518968Snilay@cs.wisc.edu# CPUs frequency 528968Snilay@cs.wisc.edutest_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 538968Snilay@cs.wisc.edu voltage_domain = 548968Snilay@cs.wisc.edu test_sys.voltage_domain) 558968Snilay@cs.wisc.edu 568968Snilay@cs.wisc.edu# Create a separate clock domain for Ethernet 578968Snilay@cs.wisc.edutest_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', 589826Sandreas.hansson@arm.com voltage_domain = 599802Snilay@cs.wisc.edu test_sys.voltage_domain) 609827Sakash.bagdia@arm.com 619827Sakash.bagdia@arm.com# In contrast to the other (one-system) Tsunami configurations we do 629793Sakash.bagdia@arm.com# not have an IO cache but instead rely on an IO bridge for accesses 638968Snilay@cs.wisc.edu# from masters on the IO bus to the memory bus 649827Sakash.bagdia@arm.comtest_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 659827Sakash.bagdia@arm.comtest_sys.iobridge.slave = test_sys.iobus.master 669827Sakash.bagdia@arm.comtest_sys.iobridge.master = test_sys.membus.slave 679827Sakash.bagdia@arm.com 689802Snilay@cs.wisc.edutest_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0]) 699802Snilay@cs.wisc.edutest_sys.physmem.port = test_sys.membus.master 709793Sakash.bagdia@arm.com 7110519Snilay@cs.wisc.edudrive_sys = makeLinuxAlphaSystem('atomic', 728968Snilay@cs.wisc.edu SysConfig('netperf-server.rcS')) 739793Sakash.bagdia@arm.comdrive_sys.kernel = SysPaths.binary('vmlinux') 749827Sakash.bagdia@arm.com# Dummy voltage domain for all drive_sys clock domains 759827Sakash.bagdia@arm.comdrive_sys.voltage_domain = VoltageDomain() 769793Sakash.bagdia@arm.com# Create the system clock domain 7710519Snilay@cs.wisc.edudrive_sys.clk_domain = SrcClockDomain(clock = '1GHz', 7810519Snilay@cs.wisc.edu voltage_domain = 7910519Snilay@cs.wisc.edu drive_sys.voltage_domain) 8010519Snilay@cs.wisc.edudrive_sys.cpu = AtomicSimpleCPU(cpu_id=0) 818968Snilay@cs.wisc.edu# create the interrupt controller 828968Snilay@cs.wisc.edudrive_sys.cpu.createInterruptController() 838968Snilay@cs.wisc.edudrive_sys.cpu.connectAllPorts(drive_sys.membus) 848968Snilay@cs.wisc.edu 8510120Snilay@cs.wisc.edu# Create a seperate clock domain for components that should run at 8610120Snilay@cs.wisc.edu# CPUs frequency 8710120Snilay@cs.wisc.edudrive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz', 8810120Snilay@cs.wisc.edu voltage_domain = 8910519Snilay@cs.wisc.edu drive_sys.voltage_domain) 9011150Smitch.hayenga@arm.com 9111150Smitch.hayenga@arm.com# Create a separate clock domain for Ethernet 9211150Smitch.hayenga@arm.comdrive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', 938968Snilay@cs.wisc.edu voltage_domain = 948968Snilay@cs.wisc.edu drive_sys.voltage_domain) 958968Snilay@cs.wisc.edu 96drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) 97drive_sys.iobridge.slave = drive_sys.iobus.master 98drive_sys.iobridge.master = drive_sys.membus.slave 99 100drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0]) 101drive_sys.physmem.port = drive_sys.membus.master 102 103root = makeDualRoot(True, test_sys, drive_sys, "ethertrace") 104 105maxtick = 199999999 106