tsunami-simple-timing.py revision 9315:2e00867b5001
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32import FSConfig 33from Caches import * 34 35#cpu 36cpu = TimingSimpleCPU(cpu_id=0) 37#the system 38system = FSConfig.makeLinuxAlphaSystem('timing') 39 40system.cpu = cpu 41 42#create the iocache 43system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) 44system.iocache.cpu_side = system.iobus.master 45system.iocache.mem_side = system.membus.slave 46 47#connect up the cpu and caches 48cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), 49 L1Cache(size = '32kB', assoc = 4), 50 L2Cache(size = '4MB', assoc = 8)) 51# create the interrupt controller 52cpu.createInterruptController() 53# connect cpu and caches to the rest of the system 54cpu.connectAllPorts(system.membus) 55# set the cpu clock along with the caches and l1-l2 bus 56cpu.clock = '2GHz' 57 58root = Root(full_system=True, system=system) 59m5.ticks.setGlobalFrequency('1THz') 60 61