xref: /gem5/tests/configs/tsunami-simple-timing-dual.py

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# Authors: Steve Reinhardt

import m5
from m5.objects import *
m5.AddToPath('../configs/common')
import FSConfig

# --------------------
# Base L1 Cache
# ====================

class L1(BaseCache):
    latency = '1ns'
    block_size = 64
    mshrs = 4
    tgts_per_mshr = 8
    protocol = CoherenceProtocol(protocol='moesi')

# ----------------------
# Base L2 Cache
# ----------------------

class L2(BaseCache):
    block_size = 64
    latency = '10ns'
    mshrs = 92
    tgts_per_mshr = 16
    write_buffers = 8

#cpu
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')

system.cpu = cpus
#create the l1/l2 bus
system.toL2Bus = Bus()

#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.port
system.l2c.mem_side = system.membus.port

#connect up the cpu and l1s
for c in cpus:
    c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                L1(size = '32kB', assoc = 4))
    # connect cpu level-1 caches to shared level-2 cache
    c.connectMemPorts(system.toL2Bus)
    c.clock = '2GHz'

root = Root(system=system)
m5.ticks.setGlobalFrequency('1THz')