tsunami-simple-atomic.py revision 4876:a18cedc19da5 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39    latency = '1ns'
40    block_size = 64
41    mshrs = 4
42    tgts_per_mshr = 8
43
44# ----------------------
45# Base L2 Cache
46# ----------------------
47
48class L2(BaseCache):
49    block_size = 64
50    latency = '10ns'
51    mshrs = 92
52    tgts_per_mshr = 16
53    write_buffers = 8
54
55#cpu
56cpu = AtomicSimpleCPU(cpu_id=0)
57#the system
58system = FSConfig.makeLinuxAlphaSystem('atomic')
59
60system.cpu = cpu
61#create the l1/l2 bus
62system.toL2Bus = Bus()
63
64#connect up the l2 cache
65system.l2c = L2(size='4MB', assoc=8)
66system.l2c.cpu_side = system.toL2Bus.port
67system.l2c.mem_side = system.membus.port
68
69#connect up the cpu and l1s
70cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
71                            L1(size = '32kB', assoc = 4))
72# connect cpu level-1 caches to shared level-2 cache
73cpu.connectMemPorts(system.toL2Bus)
74cpu.clock = '2GHz'
75
76root = Root(system=system)
77m5.ticks.setGlobalFrequency('1THz')
78
79