tsunami-simple-atomic.py revision 4444
11689SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 210333Smitch.hayenga@arm.com# All rights reserved. 37782Sminkyu.jeong@arm.com# 47782Sminkyu.jeong@arm.com# Redistribution and use in source and binary forms, with or without 57782Sminkyu.jeong@arm.com# modification, are permitted provided that the following conditions are 67782Sminkyu.jeong@arm.com# met: redistributions of source code must retain the above copyright 77782Sminkyu.jeong@arm.com# notice, this list of conditions and the following disclaimer; 87782Sminkyu.jeong@arm.com# redistributions in binary form must reproduce the above copyright 97782Sminkyu.jeong@arm.com# notice, this list of conditions and the following disclaimer in the 107782Sminkyu.jeong@arm.com# documentation and/or other materials provided with the distribution; 117782Sminkyu.jeong@arm.com# neither the name of the copyright holders nor the names of its 127782Sminkyu.jeong@arm.com# contributors may be used to endorse or promote products derived from 137782Sminkyu.jeong@arm.com# this software without specific prior written permission. 142326SN/A# 151689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 161689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 171689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 181689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 191689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 201689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 211689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 221689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 231689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 241689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 251689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 261689SN/A# 271689SN/A# Authors: Steve Reinhardt 281689SN/A 291689SN/Aimport m5 301689SN/Afrom m5.objects import * 311689SN/Am5.AddToPath('../configs/common') 321689SN/Aimport FSConfig 331689SN/A 341689SN/A# -------------------- 351689SN/A# Base L1 Cache 361689SN/A# ==================== 371689SN/A 381689SN/Aclass L1(BaseCache): 392665Ssaidi@eecs.umich.edu latency = '1ns' 402665Ssaidi@eecs.umich.edu block_size = 64 411689SN/A mshrs = 4 421689SN/A tgts_per_mshr = 8 432292SN/A protocol = CoherenceProtocol(protocol='moesi') 442292SN/A 451060SN/A# ---------------------- 461060SN/A# Base L2 Cache 478230Snate@binkert.org# ---------------------- 481060SN/A 491461SN/Aclass L2(BaseCache): 501717SN/A block_size = 64 518229Snate@binkert.org latency = '10ns' 522292SN/A mshrs = 92 538229Snate@binkert.org tgts_per_mshr = 16 548232Snate@binkert.org write_buffers = 8 5510023Smatt.horsnell@ARM.com 561060SN/A#cpu 578737Skoansin.tan@gmail.comcpu = AtomicSimpleCPU(cpu_id=0) 582292SN/A#the system 592292SN/Asystem = FSConfig.makeLinuxAlphaSystem('atomic') 602292SN/A 612326SN/Asystem.cpu = cpu 622326SN/A#create the l1/l2 bus 632326SN/Asystem.toL2Bus = Bus() 642326SN/A 652326SN/A#connect up the l2 cache 662292SN/Asystem.l2c = L2(size='4MB', assoc=8) 672326SN/Asystem.l2c.cpu_side = system.toL2Bus.port 682326SN/Asystem.l2c.mem_side = system.membus.port 692326SN/A 702326SN/A#connect up the cpu and l1s 712326SN/Acpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 722326SN/A L1(size = '32kB', assoc = 4)) 732326SN/A# connect cpu level-1 caches to shared level-2 cache 742326SN/Acpu.connectMemPorts(system.toL2Bus) 752326SN/Acpu.clock = '2GHz' 762326SN/A 772326SN/Aroot = Root(system=system) 782292SN/Am5.ticks.setGlobalFrequency('1THz') 791681SN/A 802292SN/A