tsunami-o3-dual.py revision 8713:2f1a3e335255
19241Sandreas.hansson@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 212396SRiken.Gohil@arm.com# All rights reserved. 39241Sandreas.hansson@arm.com# 49241Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 59241Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 69241Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 79241Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 89241Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 99241Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 109241Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 119241Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 129241Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 139241Sandreas.hansson@arm.com# this software without specific prior written permission. 149241Sandreas.hansson@arm.com# 159241Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169241Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179241Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189241Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199241Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209241Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219241Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229241Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239241Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249241Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259241Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269241Sandreas.hansson@arm.com# 279241Sandreas.hansson@arm.com# Authors: Steve Reinhardt 289241Sandreas.hansson@arm.com 299241Sandreas.hansson@arm.comimport m5 309241Sandreas.hansson@arm.comfrom m5.objects import * 319241Sandreas.hansson@arm.comm5.util.addToPath('../configs/common') 329241Sandreas.hansson@arm.comimport FSConfig 339241Sandreas.hansson@arm.com 349241Sandreas.hansson@arm.com 359241Sandreas.hansson@arm.com# -------------------- 369241Sandreas.hansson@arm.com# Base L1 Cache 379241Sandreas.hansson@arm.com# ==================== 389241Sandreas.hansson@arm.com 399241Sandreas.hansson@arm.comclass L1(BaseCache): 409241Sandreas.hansson@arm.com latency = '1ns' 4112396SRiken.Gohil@arm.com block_size = 64 429666Sandreas.hansson@arm.com mshrs = 4 439666Sandreas.hansson@arm.com tgts_per_mshr = 20 449241Sandreas.hansson@arm.com is_top_level = True 4511168Sandreas.hansson@arm.com 4611168Sandreas.hansson@arm.com# ---------------------- 479719Sandreas.hansson@arm.com# Base L2 Cache 4812396SRiken.Gohil@arm.com# ---------------------- 4912396SRiken.Gohil@arm.com 5012396SRiken.Gohil@arm.comclass L2(BaseCache): 5112396SRiken.Gohil@arm.com block_size = 64 5212396SRiken.Gohil@arm.com latency = '10ns' 5312396SRiken.Gohil@arm.com mshrs = 92 5412396SRiken.Gohil@arm.com tgts_per_mshr = 16 559241Sandreas.hansson@arm.com write_buffers = 8 569241Sandreas.hansson@arm.com 579241Sandreas.hansson@arm.com# --------------------- 589241Sandreas.hansson@arm.com# I/O Cache 599241Sandreas.hansson@arm.com# --------------------- 609241Sandreas.hansson@arm.comclass IOCache(BaseCache): 619717Sandreas.hansson@arm.com assoc = 8 629717Sandreas.hansson@arm.com block_size = 64 639717Sandreas.hansson@arm.com latency = '50ns' 649717Sandreas.hansson@arm.com mshrs = 20 659717Sandreas.hansson@arm.com size = '1kB' 669717Sandreas.hansson@arm.com tgts_per_mshr = 12 679241Sandreas.hansson@arm.com addr_range=AddrRange(0, size='8GB') 689241Sandreas.hansson@arm.com forward_snoops = False 699241Sandreas.hansson@arm.com is_top_level = True 709241Sandreas.hansson@arm.com 719241Sandreas.hansson@arm.com#cpu 729241Sandreas.hansson@arm.comcpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] 739241Sandreas.hansson@arm.com#the system 749717Sandreas.hansson@arm.comsystem = FSConfig.makeLinuxAlphaSystem('timing') 759717Sandreas.hansson@arm.com 769717Sandreas.hansson@arm.comsystem.cpu = cpus 779717Sandreas.hansson@arm.com#create the l1/l2 bus 789717Sandreas.hansson@arm.comsystem.toL2Bus = Bus() 799717Sandreas.hansson@arm.comsystem.iocache = IOCache() 809717Sandreas.hansson@arm.comsystem.iocache.cpu_side = system.iobus.port 819717Sandreas.hansson@arm.comsystem.iocache.mem_side = system.membus.port 829717Sandreas.hansson@arm.com 839717Sandreas.hansson@arm.com 849717Sandreas.hansson@arm.com#connect up the l2 cache 859717Sandreas.hansson@arm.comsystem.l2c = L2(size='4MB', assoc=8) 8611540Sandreas.sandberg@arm.comsystem.l2c.cpu_side = system.toL2Bus.port 8711540Sandreas.sandberg@arm.comsystem.l2c.mem_side = system.membus.port 8811540Sandreas.sandberg@arm.comsystem.l2c.num_cpus = 2 8911540Sandreas.sandberg@arm.com 9011540Sandreas.sandberg@arm.com#connect up the cpu and l1s 9111540Sandreas.sandberg@arm.comfor c in cpus: 9211540Sandreas.sandberg@arm.com c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 9311540Sandreas.sandberg@arm.com L1(size = '32kB', assoc = 4)) 9411540Sandreas.sandberg@arm.com # connect cpu level-1 caches to shared level-2 cache 9511540Sandreas.sandberg@arm.com c.connectAllPorts(system.toL2Bus, system.membus) 9611540Sandreas.sandberg@arm.com c.clock = '2GHz' 9711540Sandreas.sandberg@arm.com 9811540Sandreas.sandberg@arm.comroot = Root(system=system) 9911540Sandreas.sandberg@arm.comm5.ticks.setGlobalFrequency('1THz') 10011540Sandreas.sandberg@arm.com 1019717Sandreas.hansson@arm.com