tsunami-o3-dual.py revision 5703
16906SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26906SBrad.Beckmann@amd.com# All rights reserved. 36906SBrad.Beckmann@amd.com# 46906SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 56906SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 66906SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 76906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 86906SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 96906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 106906SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 116906SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 126906SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 136906SBrad.Beckmann@amd.com# this software without specific prior written permission. 146906SBrad.Beckmann@amd.com# 156906SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166906SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176906SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186906SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196906SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206906SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216906SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226906SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236906SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246906SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256906SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266906SBrad.Beckmann@amd.com# 276906SBrad.Beckmann@amd.com# Authors: Steve Reinhardt 286906SBrad.Beckmann@amd.com 296906SBrad.Beckmann@amd.comimport m5 308183Snilay@cs.wisc.edufrom m5.objects import * 316906SBrad.Beckmann@amd.comm5.AddToPath('../configs/common') 326906SBrad.Beckmann@amd.comimport FSConfig 336906SBrad.Beckmann@amd.com 349100SBrad.Beckmann@amd.com 356906SBrad.Beckmann@amd.com# -------------------- 366906SBrad.Beckmann@amd.com# Base L1 Cache 376906SBrad.Beckmann@amd.com# ==================== 386906SBrad.Beckmann@amd.com 396906SBrad.Beckmann@amd.comclass L1(BaseCache): 406906SBrad.Beckmann@amd.com latency = '1ns' 416906SBrad.Beckmann@amd.com block_size = 64 427538SBrad.Beckmann@amd.com mshrs = 4 437538SBrad.Beckmann@amd.com tgts_per_mshr = 8 447538SBrad.Beckmann@amd.com 458929Snilay@cs.wisc.edu# ---------------------- 466906SBrad.Beckmann@amd.com# Base L2 Cache 476906SBrad.Beckmann@amd.com# ---------------------- 486906SBrad.Beckmann@amd.com 496906SBrad.Beckmann@amd.comclass L2(BaseCache): 506906SBrad.Beckmann@amd.com block_size = 64 516906SBrad.Beckmann@amd.com latency = '10ns' 526906SBrad.Beckmann@amd.com mshrs = 92 536906SBrad.Beckmann@amd.com tgts_per_mshr = 16 546906SBrad.Beckmann@amd.com write_buffers = 8 556906SBrad.Beckmann@amd.com 566906SBrad.Beckmann@amd.com# --------------------- 576906SBrad.Beckmann@amd.com# I/O Cache 586906SBrad.Beckmann@amd.com# --------------------- 596906SBrad.Beckmann@amd.comclass IOCache(BaseCache): 606906SBrad.Beckmann@amd.com assoc = 8 616906SBrad.Beckmann@amd.com block_size = 64 626906SBrad.Beckmann@amd.com latency = '50ns' 636906SBrad.Beckmann@amd.com mshrs = 20 646906SBrad.Beckmann@amd.com size = '1kB' 658180SBrad.Beckmann@amd.com tgts_per_mshr = 12 668257SBrad.Beckmann@amd.com mem_side_filter_ranges=[AddrRange(0, Addr.max)] 678257SBrad.Beckmann@amd.com cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] 686906SBrad.Beckmann@amd.com 696906SBrad.Beckmann@amd.com#cpu 706906SBrad.Beckmann@amd.comcpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] 716906SBrad.Beckmann@amd.com#the system 726906SBrad.Beckmann@amd.comsystem = FSConfig.makeLinuxAlphaSystem('timing') 736906SBrad.Beckmann@amd.com 746906SBrad.Beckmann@amd.comsystem.cpu = cpus 756906SBrad.Beckmann@amd.com#create the l1/l2 bus 768180SBrad.Beckmann@amd.comsystem.toL2Bus = Bus() 778180SBrad.Beckmann@amd.comsystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 786906SBrad.Beckmann@amd.comsystem.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] 796906SBrad.Beckmann@amd.comsystem.iocache = IOCache() 806906SBrad.Beckmann@amd.comsystem.iocache.cpu_side = system.iobus.port 816906SBrad.Beckmann@amd.comsystem.iocache.mem_side = system.membus.port 828322Ssteve.reinhardt@amd.com 838322Ssteve.reinhardt@amd.com 848436SBrad.Beckmann@amd.com#connect up the l2 cache 858717Snilay@cs.wisc.edusystem.l2c = L2(size='4MB', assoc=8) 868717Snilay@cs.wisc.edusystem.l2c.cpu_side = system.toL2Bus.port 878436SBrad.Beckmann@amd.comsystem.l2c.mem_side = system.membus.port 888322Ssteve.reinhardt@amd.com 897015SBrad.Beckmann@amd.com#connect up the cpu and l1s 907015SBrad.Beckmann@amd.comfor c in cpus: 916906SBrad.Beckmann@amd.com c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 928436SBrad.Beckmann@amd.com L1(size = '32kB', assoc = 4)) 936906SBrad.Beckmann@amd.com # connect cpu level-1 caches to shared level-2 cache 948322Ssteve.reinhardt@amd.com c.connectMemPorts(system.toL2Bus) 958322Ssteve.reinhardt@amd.com c.clock = '2GHz' 966906SBrad.Beckmann@amd.com 978845Sandreas.hansson@arm.comroot = Root(system=system) 986906SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1THz') 999468Smalek.musleh@gmail.com 1006906SBrad.Beckmann@amd.com