tgen-simple-mem.py revision 9242:256143419b40
19241Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 29717Sandreas.hansson@arm.com# All rights reserved. 39241Sandreas.hansson@arm.com# 49241Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 59241Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 69241Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 79241Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 89241Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 99241Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 109241Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 119241Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 129241Sandreas.hansson@arm.com# 139241Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 149241Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 159241Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 169241Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 179241Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 189241Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 199241Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 209241Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 219241Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 229241Sandreas.hansson@arm.com# this software without specific prior written permission. 239241Sandreas.hansson@arm.com# 249241Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259241Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269241Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279241Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289241Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299241Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309241Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319241Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329241Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339241Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349241Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359241Sandreas.hansson@arm.com# 369241Sandreas.hansson@arm.com# Authors: Andreas Hansson 379241Sandreas.hansson@arm.com 389241Sandreas.hansson@arm.comimport m5 399241Sandreas.hansson@arm.comfrom m5.objects import * 409241Sandreas.hansson@arm.com 419241Sandreas.hansson@arm.com# even if this is only a traffic generator, call it cpu to make sure 429241Sandreas.hansson@arm.com# the scripts are happy 439241Sandreas.hansson@arm.comcpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") 4410138Sneha.agarwal@arm.com 459241Sandreas.hansson@arm.com# system simulated 469241Sandreas.hansson@arm.comsystem = System(cpu = cpu, physmem = SimpleMemory(), 479241Sandreas.hansson@arm.com membus = NoncoherentBus(clock="1GHz", width = 16)) 489241Sandreas.hansson@arm.com 499241Sandreas.hansson@arm.com# add a communication monitor 509241Sandreas.hansson@arm.comsystem.monitor = CommMonitor() 519241Sandreas.hansson@arm.com 529241Sandreas.hansson@arm.com# connect the traffic generator to the bus via a communication monitor 539241Sandreas.hansson@arm.comsystem.cpu.port = system.monitor.slave 549241Sandreas.hansson@arm.comsystem.monitor.master = system.membus.slave 559241Sandreas.hansson@arm.com 569241Sandreas.hansson@arm.com# connect the system port even if it is not used in this example 579241Sandreas.hansson@arm.comsystem.system_port = system.membus.slave 589718Sandreas.hansson@arm.com 599720Sandreas.hansson@arm.com# connect memory to the membus 609717Sandreas.hansson@arm.comsystem.physmem.port = system.membus.master 619719Sandreas.hansson@arm.com 6210360Sandreas.hansson@arm.com# ----------------------- 639241Sandreas.hansson@arm.com# run simulation 649719Sandreas.hansson@arm.com# ----------------------- 659719Sandreas.hansson@arm.com 669719Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 679719Sandreas.hansson@arm.comroot.system.mem_mode = 'timing' 689241Sandreas.hansson@arm.com