tgen-dram-ctrl.py revision 9793 
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36# Authors: Andreas Hansson
37
38import m5
39from m5.objects import *
40
41# both traffic generator and communication monitor are only available
42# if we have protobuf support, so potentially skip this test
43require_sim_object("TrafficGen")
44require_sim_object("CommMonitor")
45
46# even if this is only a traffic generator, call it cpu to make sure
47# the scripts are happy
48cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
49
50# system simulated
51system = System(cpu = cpu, physmem = DDR3_1600_x64(),
52                membus = NoncoherentBus(width = 16),
53                clk_domain = SrcClockDomain(clock = '1GHz'))
54
55# add a communication monitor
56system.monitor = CommMonitor()
57
58# connect the traffic generator to the bus via a communication monitor
59system.cpu.port = system.monitor.slave
60system.monitor.master = system.membus.slave
61
62# connect the system port even if it is not used in this example
63system.system_port = system.membus.slave
64
65# connect memory to the membus
66system.physmem.port = system.membus.master
67
68# -----------------------
69# run simulation
70# -----------------------
71
72root = Root(full_system = False, system = system)
73root.system.mem_mode = 'timing'
74