t1000-simple-atomic.py revision 9680:217bdd9a3ad9
18968Snilay@cs.wisc.edu# Copyright (c) 2007 The Regents of The University of Michigan 28968Snilay@cs.wisc.edu# All rights reserved. 38968Snilay@cs.wisc.edu# 48968Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 58968Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 68968Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 78968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 88968Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 98968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 108968Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 118968Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 128968Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 138968Snilay@cs.wisc.edu# this software without specific prior written permission. 148968Snilay@cs.wisc.edu# 158968Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168968Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178968Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188968Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198968Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208968Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218968Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228968Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238968Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248968Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258968Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268968Snilay@cs.wisc.edu# 278968Snilay@cs.wisc.edu# Authors: Ali Saidi 288968Snilay@cs.wisc.edu 298968Snilay@cs.wisc.eduimport m5 308968Snilay@cs.wisc.edufrom m5.objects import * 318968Snilay@cs.wisc.edum5.util.addToPath('../configs/common') 328968Snilay@cs.wisc.eduimport FSConfig 338968Snilay@cs.wisc.edu 348968Snilay@cs.wisc.educpu = AtomicSimpleCPU(cpu_id=0) 358968Snilay@cs.wisc.edusystem = FSConfig.makeSparcSystem('atomic', SimpleDDR3) 368968Snilay@cs.wisc.edusystem.cpu = cpu 378968Snilay@cs.wisc.edu# create the interrupt controller 388968Snilay@cs.wisc.educpu.createInterruptController() 398968Snilay@cs.wisc.educpu.connectAllPorts(system.membus) 408968Snilay@cs.wisc.edu 418968Snilay@cs.wisc.eduroot = Root(full_system=True, system=system) 428968Snilay@cs.wisc.edu 438968Snilay@cs.wisc.edum5.ticks.setGlobalFrequency('2GHz') 448968Snilay@cs.wisc.edu