t1000-simple-atomic.py revision 9680:217bdd9a3ad9
18968Snilay@cs.wisc.edu# Copyright (c) 2007 The Regents of The University of Michigan
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278968Snilay@cs.wisc.edu# Authors: Ali Saidi
288968Snilay@cs.wisc.edu
298968Snilay@cs.wisc.eduimport m5
308968Snilay@cs.wisc.edufrom m5.objects import *
318968Snilay@cs.wisc.edum5.util.addToPath('../configs/common')
328968Snilay@cs.wisc.eduimport FSConfig
338968Snilay@cs.wisc.edu
348968Snilay@cs.wisc.educpu = AtomicSimpleCPU(cpu_id=0)
358968Snilay@cs.wisc.edusystem = FSConfig.makeSparcSystem('atomic', SimpleDDR3)
368968Snilay@cs.wisc.edusystem.cpu = cpu
378968Snilay@cs.wisc.edu# create the interrupt controller
388968Snilay@cs.wisc.educpu.createInterruptController()
398968Snilay@cs.wisc.educpu.connectAllPorts(system.membus)
408968Snilay@cs.wisc.edu
418968Snilay@cs.wisc.eduroot = Root(full_system=True, system=system)
428968Snilay@cs.wisc.edu
438968Snilay@cs.wisc.edum5.ticks.setGlobalFrequency('2GHz')
448968Snilay@cs.wisc.edu