simple-timing-ruby.py revision 9826:014ff1fbff6d
19793Sakash.bagdia@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 29518SAndreas.Sandberg@ARM.com# All rights reserved. 311320Ssteve.reinhardt@amd.com# 49518SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 59518SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 69518SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 79518SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 89518SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 99518SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 109518SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 119518SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 129518SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 135347Ssaidi@eecs.umich.edu# this software without specific prior written permission. 147534Ssteve.reinhardt@amd.com# 153395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263395Shsul@eecs.umich.edu# 273395Shsul@eecs.umich.edu# Authors: Steve Reinhardt 283395Shsul@eecs.umich.edu 293395Shsul@eecs.umich.eduimport m5 303395Shsul@eecs.umich.edufrom m5.objects import * 313395Shsul@eecs.umich.edufrom m5.defines import buildEnv 323395Shsul@eecs.umich.edufrom m5.util import addToPath 333395Shsul@eecs.umich.eduimport os, optparse, sys 343395Shsul@eecs.umich.edu 353395Shsul@eecs.umich.edu# Get paths we might need 363395Shsul@eecs.umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 373395Shsul@eecs.umich.educonfig_root = os.path.dirname(config_path) 383395Shsul@eecs.umich.eduaddToPath(config_root+'/configs/common') 393395Shsul@eecs.umich.eduaddToPath(config_root+'/configs/ruby') 403395Shsul@eecs.umich.eduaddToPath(config_root+'/configs/topologies') 413395Shsul@eecs.umich.edu 4212564Sgabeblack@google.comimport Ruby 4312564Sgabeblack@google.comimport Options 449457Svilanova@ac.upc.edu 453395Shsul@eecs.umich.eduparser = optparse.OptionParser() 463509Shsul@eecs.umich.eduOptions.addCommonOptions(parser) 476654Snate@binkert.org 4811688Sandreas.hansson@arm.com# Add the ruby specific and protocol specific options 4911688Sandreas.hansson@arm.comRuby.define_options(parser) 509520SAndreas.Sandberg@ARM.com 513395Shsul@eecs.umich.edu(options, args) = parser.parse_args() 526654Snate@binkert.org 533395Shsul@eecs.umich.edu# 546654Snate@binkert.org# Set the default cache size and associativity to be very small to encourage 556654Snate@binkert.org# races between requests and writebacks. 566654Snate@binkert.org# 573395Shsul@eecs.umich.eduoptions.l1d_size="256B" 589139Snilay@cs.wisc.eduoptions.l1i_size="256B" 599520SAndreas.Sandberg@ARM.comoptions.l2_size="512B" 609520SAndreas.Sandberg@ARM.comoptions.l3_size="1kB" 619520SAndreas.Sandberg@ARM.comoptions.l1d_assoc=2 629139Snilay@cs.wisc.eduoptions.l1i_assoc=2 633481Shsul@eecs.umich.eduoptions.l2_assoc=2 649139Snilay@cs.wisc.eduoptions.l3_assoc=2 653481Shsul@eecs.umich.edu 669139Snilay@cs.wisc.edu# this is a uniprocessor only test 679139Snilay@cs.wisc.eduoptions.num_cpus = 1 689139Snilay@cs.wisc.edu 699139Snilay@cs.wisc.educpu = TimingSimpleCPU(cpu_id=0) 709139Snilay@cs.wisc.edusystem = System(cpu = cpu, physmem = SimpleMemory(null = True), 719139Snilay@cs.wisc.edu clk_domain = SrcClockDomain(clock = '1GHz')) 729139Snilay@cs.wisc.edu 739139Snilay@cs.wisc.edu# Create a seperate clock domain for components that should run at 743481Shsul@eecs.umich.edu# CPUs frequency 759518SAndreas.Sandberg@ARM.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 769518SAndreas.Sandberg@ARM.com 779518SAndreas.Sandberg@ARM.comsystem.mem_ranges = AddrRange('256MB') 783481Shsul@eecs.umich.edu 799139Snilay@cs.wisc.eduRuby.create_system(options, system) 809139Snilay@cs.wisc.edu 813481Shsul@eecs.umich.edu# Create a separate clock for Ruby 829139Snilay@cs.wisc.edusystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 839139Snilay@cs.wisc.edu 849139Snilay@cs.wisc.eduassert(len(system.ruby._cpu_ruby_ports) == 1) 859139Snilay@cs.wisc.edu 869139Snilay@cs.wisc.edu# create the interrupt controller 873481Shsul@eecs.umich.educpu.createInterruptController() 8812395Sswapnilster@gmail.com 8912395Sswapnilster@gmail.com# 9012395Sswapnilster@gmail.com# Tie the cpu cache ports to the ruby cpu ports and 9112395Sswapnilster@gmail.com# physmem, respectively 9212395Sswapnilster@gmail.com# 933481Shsul@eecs.umich.educpu.connectAllPorts(system.ruby._cpu_ruby_ports[0]) 943481Shsul@eecs.umich.edu 959665Sandreas.hansson@arm.com# ----------------------- 969665Sandreas.hansson@arm.com# run simulation 979665Sandreas.hansson@arm.com# ----------------------- 989665Sandreas.hansson@arm.com 999665Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 1008919Snilay@cs.wisc.eduroot.system.mem_mode = 'timing' 1018919Snilay@cs.wisc.edu 1028919Snilay@cs.wisc.edu# Not much point in this being higher than the L1 latency 10310159Sgedare@rtems.orgm5.ticks.setGlobalFrequency('1ns') 10410159Sgedare@rtems.org