simple-timing-ruby.py revision 9826:014ff1fbff6d
112642Sgiacomo.travaglini@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
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2612642Sgiacomo.travaglini@arm.com#
2712642Sgiacomo.travaglini@arm.com# Authors: Steve Reinhardt
2812642Sgiacomo.travaglini@arm.com
2912642Sgiacomo.travaglini@arm.comimport m5
3012642Sgiacomo.travaglini@arm.comfrom m5.objects import *
3112642Sgiacomo.travaglini@arm.comfrom m5.defines import buildEnv
3212642Sgiacomo.travaglini@arm.comfrom m5.util import addToPath
3312642Sgiacomo.travaglini@arm.comimport os, optparse, sys
3412642Sgiacomo.travaglini@arm.com
3512642Sgiacomo.travaglini@arm.com# Get paths we might need
3612642Sgiacomo.travaglini@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__))
3712642Sgiacomo.travaglini@arm.comconfig_root = os.path.dirname(config_path)
3812642Sgiacomo.travaglini@arm.comaddToPath(config_root+'/configs/common')
3912642Sgiacomo.travaglini@arm.comaddToPath(config_root+'/configs/ruby')
4012642Sgiacomo.travaglini@arm.comaddToPath(config_root+'/configs/topologies')
4112642Sgiacomo.travaglini@arm.com
4212642Sgiacomo.travaglini@arm.comimport Ruby
4312642Sgiacomo.travaglini@arm.comimport Options
4412642Sgiacomo.travaglini@arm.com
4512642Sgiacomo.travaglini@arm.comparser = optparse.OptionParser()
4612642Sgiacomo.travaglini@arm.comOptions.addCommonOptions(parser)
4712642Sgiacomo.travaglini@arm.com
4812642Sgiacomo.travaglini@arm.com# Add the ruby specific and protocol specific options
4912642Sgiacomo.travaglini@arm.comRuby.define_options(parser)
5012642Sgiacomo.travaglini@arm.com
5112642Sgiacomo.travaglini@arm.com(options, args) = parser.parse_args()
5212642Sgiacomo.travaglini@arm.com
5312642Sgiacomo.travaglini@arm.com#
5412642Sgiacomo.travaglini@arm.com# Set the default cache size and associativity to be very small to encourage
5512642Sgiacomo.travaglini@arm.com# races between requests and writebacks.
5612642Sgiacomo.travaglini@arm.com#
5712642Sgiacomo.travaglini@arm.comoptions.l1d_size="256B"
5812642Sgiacomo.travaglini@arm.comoptions.l1i_size="256B"
5912642Sgiacomo.travaglini@arm.comoptions.l2_size="512B"
6012642Sgiacomo.travaglini@arm.comoptions.l3_size="1kB"
6112642Sgiacomo.travaglini@arm.comoptions.l1d_assoc=2
6212642Sgiacomo.travaglini@arm.comoptions.l1i_assoc=2
6312642Sgiacomo.travaglini@arm.comoptions.l2_assoc=2
6412642Sgiacomo.travaglini@arm.comoptions.l3_assoc=2
6512642Sgiacomo.travaglini@arm.com
6612642Sgiacomo.travaglini@arm.com# this is a uniprocessor only test
6712642Sgiacomo.travaglini@arm.comoptions.num_cpus = 1
6812642Sgiacomo.travaglini@arm.com
6912642Sgiacomo.travaglini@arm.comcpu = TimingSimpleCPU(cpu_id=0)
7012642Sgiacomo.travaglini@arm.comsystem = System(cpu = cpu, physmem = SimpleMemory(null = True),
7112642Sgiacomo.travaglini@arm.com                clk_domain = SrcClockDomain(clock = '1GHz'))
7212642Sgiacomo.travaglini@arm.com
7312642Sgiacomo.travaglini@arm.com# Create a seperate clock domain for components that should run at
7412642Sgiacomo.travaglini@arm.com# CPUs frequency
7512642Sgiacomo.travaglini@arm.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
7612642Sgiacomo.travaglini@arm.com
7712642Sgiacomo.travaglini@arm.comsystem.mem_ranges = AddrRange('256MB')
7812642Sgiacomo.travaglini@arm.com
7912642Sgiacomo.travaglini@arm.comRuby.create_system(options, system)
8012642Sgiacomo.travaglini@arm.com
8112642Sgiacomo.travaglini@arm.com# Create a separate clock for Ruby
8212642Sgiacomo.travaglini@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
8312642Sgiacomo.travaglini@arm.com
8412642Sgiacomo.travaglini@arm.comassert(len(system.ruby._cpu_ruby_ports) == 1)
8512642Sgiacomo.travaglini@arm.com
8612642Sgiacomo.travaglini@arm.com# create the interrupt controller
8712642Sgiacomo.travaglini@arm.comcpu.createInterruptController()
8812642Sgiacomo.travaglini@arm.com
8912642Sgiacomo.travaglini@arm.com#
9012642Sgiacomo.travaglini@arm.com# Tie the cpu cache ports to the ruby cpu ports and
9112642Sgiacomo.travaglini@arm.com# physmem, respectively
9212642Sgiacomo.travaglini@arm.com#
9312642Sgiacomo.travaglini@arm.comcpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
9412642Sgiacomo.travaglini@arm.com
9512642Sgiacomo.travaglini@arm.com# -----------------------
9612642Sgiacomo.travaglini@arm.com# run simulation
9712642Sgiacomo.travaglini@arm.com# -----------------------
9812642Sgiacomo.travaglini@arm.com
9912642Sgiacomo.travaglini@arm.comroot = Root(full_system = False, system = system)
10012642Sgiacomo.travaglini@arm.comroot.system.mem_mode = 'timing'
10112642Sgiacomo.travaglini@arm.com
10212642Sgiacomo.travaglini@arm.com# Not much point in this being higher than the L1 latency
10312642Sgiacomo.travaglini@arm.comm5.ticks.setGlobalFrequency('1ns')
10412642Sgiacomo.travaglini@arm.com