simple-timing-ruby.py revision 8931:7a1dfb191e3f
15222Sksewell@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 25254Sksewell@umich.edu# All rights reserved. 35254Sksewell@umich.edu# 45222Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 55254Sksewell@umich.edu# modification, are permitted provided that the following conditions are 65254Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 75254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 85254Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 95254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 105254Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 115254Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 125254Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 135254Sksewell@umich.edu# this software without specific prior written permission. 145254Sksewell@umich.edu# 155222Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165254Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175254Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185254Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195254Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205254Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215254Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225254Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235254Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245254Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255254Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265254Sksewell@umich.edu# 275222Sksewell@umich.edu# Authors: Steve Reinhardt 285254Sksewell@umich.edu 295254Sksewell@umich.eduimport m5 305222Sksewell@umich.edufrom m5.objects import * 315222Sksewell@umich.edufrom m5.defines import buildEnv 325222Sksewell@umich.edufrom m5.util import addToPath 335222Sksewell@umich.eduimport os, optparse, sys 345222Sksewell@umich.edu 355222Sksewell@umich.edu# Get paths we might need 365222Sksewell@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 375222Sksewell@umich.educonfig_root = os.path.dirname(config_path) 385222Sksewell@umich.eduaddToPath(config_root+'/configs/common') 395222Sksewell@umich.eduaddToPath(config_root+'/configs/ruby') 405222Sksewell@umich.edu 415222Sksewell@umich.eduimport Ruby 425222Sksewell@umich.eduimport Options 435222Sksewell@umich.edu 445222Sksewell@umich.eduparser = optparse.OptionParser() 455222Sksewell@umich.eduOptions.addCommonOptions(parser) 465222Sksewell@umich.edu 475222Sksewell@umich.edu# Add the ruby specific and protocol specific options 485222Sksewell@umich.eduRuby.define_options(parser) 495222Sksewell@umich.edu 505222Sksewell@umich.edu(options, args) = parser.parse_args() 515222Sksewell@umich.edu 525222Sksewell@umich.edu# 535222Sksewell@umich.edu# Set the default cache size and associativity to be very small to encourage 545222Sksewell@umich.edu# races between requests and writebacks. 555222Sksewell@umich.edu# 565222Sksewell@umich.eduoptions.l1d_size="256B" 575222Sksewell@umich.eduoptions.l1i_size="256B" 585222Sksewell@umich.eduoptions.l2_size="512B" 595222Sksewell@umich.eduoptions.l3_size="1kB" 60options.l1d_assoc=2 61options.l1i_assoc=2 62options.l2_assoc=2 63options.l3_assoc=2 64 65# this is a uniprocessor only test 66options.num_cpus = 1 67 68cpu = TimingSimpleCPU(cpu_id=0) 69system = System(cpu = cpu, physmem = SimpleMemory()) 70 71Ruby.create_system(options, system) 72 73assert(len(system.ruby._cpu_ruby_ports) == 1) 74 75# create the interrupt controller 76cpu.createInterruptController() 77 78# 79# Tie the cpu cache ports to the ruby cpu ports and 80# physmem, respectively 81# 82cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0]) 83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root(full_system = False, system = system) 89root.system.mem_mode = 'timing' 90 91# Not much point in this being higher than the L1 latency 92m5.ticks.setGlobalFrequency('1ns') 93