simple-timing-ruby.py revision 8802:ef66a9083bc4
15222Sksewell@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 25222Sksewell@umich.edu# All rights reserved. 35222Sksewell@umich.edu# 45222Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 55222Sksewell@umich.edu# modification, are permitted provided that the following conditions are 65222Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 75222Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 85222Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 95222Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 105222Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 115222Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 125222Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 135222Sksewell@umich.edu# this software without specific prior written permission. 145222Sksewell@umich.edu# 155222Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165222Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175222Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185222Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195222Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205222Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215222Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225222Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235222Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245222Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255222Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265222Sksewell@umich.edu# 275222Sksewell@umich.edu# Authors: Steve Reinhardt 285222Sksewell@umich.edu 295222Sksewell@umich.eduimport m5 305222Sksewell@umich.edufrom m5.objects import * 315222Sksewell@umich.edufrom m5.defines import buildEnv 325222Sksewell@umich.edufrom m5.util import addToPath 335222Sksewell@umich.eduimport os, optparse, sys 345222Sksewell@umich.edu 355222Sksewell@umich.edu# Get paths we might need 365222Sksewell@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 375222Sksewell@umich.educonfig_root = os.path.dirname(config_path) 385222Sksewell@umich.edum5_root = os.path.dirname(config_root) 395222Sksewell@umich.eduaddToPath(config_root+'/configs/common') 405222Sksewell@umich.eduaddToPath(config_root+'/configs/ruby') 415222Sksewell@umich.edu 425222Sksewell@umich.eduimport Ruby 435222Sksewell@umich.edu 445222Sksewell@umich.eduparser = optparse.OptionParser() 455222Sksewell@umich.edu 465222Sksewell@umich.edu# 475222Sksewell@umich.edu# Add the ruby specific and protocol specific options 485222Sksewell@umich.edu# 495222Sksewell@umich.eduRuby.define_options(parser) 505222Sksewell@umich.edu 515222Sksewell@umich.eduexecfile(os.path.join(config_root, "configs/common", "Options.py")) 525222Sksewell@umich.edu 535222Sksewell@umich.edu(options, args) = parser.parse_args() 545222Sksewell@umich.edu 555222Sksewell@umich.edu# 565222Sksewell@umich.edu# Set the default cache size and associativity to be very small to encourage 575222Sksewell@umich.edu# races between requests and writebacks. 585222Sksewell@umich.edu# 595222Sksewell@umich.eduoptions.l1d_size="256B" 605222Sksewell@umich.eduoptions.l1i_size="256B" 615222Sksewell@umich.eduoptions.l2_size="512B" 625222Sksewell@umich.eduoptions.l3_size="1kB" 635222Sksewell@umich.eduoptions.l1d_assoc=2 645222Sksewell@umich.eduoptions.l1i_assoc=2 655222Sksewell@umich.eduoptions.l2_assoc=2 66options.l3_assoc=2 67 68# this is a uniprocessor only test 69options.num_cpus = 1 70 71cpu = TimingSimpleCPU(cpu_id=0) 72system = System(cpu = cpu, physmem = PhysicalMemory()) 73 74Ruby.create_system(options, system) 75 76assert(len(system.ruby._cpu_ruby_ports) == 1) 77 78# 79# Tie the cpu cache ports to the ruby cpu ports and 80# physmem, respectively 81# 82cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0]) 83 84# Connect the system port for loading of binaries etc 85system.system_port = system.ruby._sys_port_proxy.port 86 87# ----------------------- 88# run simulation 89# ----------------------- 90 91root = Root(full_system = False, system = system) 92root.system.mem_mode = 'timing' 93 94# Not much point in this being higher than the L1 latency 95m5.ticks.setGlobalFrequency('1ns') 96