simple-timing-ruby.py revision 7034:6bf327b128c6
110447Snilay@cs.wisc.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 210447Snilay@cs.wisc.edu# All rights reserved. 310447Snilay@cs.wisc.edu# 410447Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 510447Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 610447Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 710447Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 810447Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 910447Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 1010447Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 1110447Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 1210447Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 1310447Snilay@cs.wisc.edu# this software without specific prior written permission. 1410447Snilay@cs.wisc.edu# 1510447Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1610447Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1710447Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1810447Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1910447Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2010447Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2110447Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2210447Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2310447Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2410447Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2510447Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2610447Snilay@cs.wisc.edu# 2710447Snilay@cs.wisc.edu# Authors: Steve Reinhardt 2810447Snilay@cs.wisc.edu 2910447Snilay@cs.wisc.eduimport m5 3010447Snilay@cs.wisc.edufrom m5.objects import * 3110447Snilay@cs.wisc.edufrom m5.defines import buildEnv 3210447Snilay@cs.wisc.edufrom m5.util import addToPath 3310447Snilay@cs.wisc.eduimport os, optparse, sys 34 35if buildEnv['FULL_SYSTEM']: 36 panic("This script requires system-emulation mode (*_SE).") 37 38# Get paths we might need 39config_path = os.path.dirname(os.path.abspath(__file__)) 40config_root = os.path.dirname(config_path) 41m5_root = os.path.dirname(config_root) 42addToPath(config_root+'/configs/common') 43addToPath(config_root+'/configs/ruby') 44addToPath(config_root+'/configs/ruby/protocols') 45addToPath(config_root+'/configs/ruby/topologies') 46 47import Ruby 48 49parser = optparse.OptionParser() 50 51# 52# Set the default cache size and associativity to be very small to encourage 53# races between requests and writebacks. 54# 55parser.add_option("--l1d_size", type="string", default="256B") 56parser.add_option("--l1i_size", type="string", default="256B") 57parser.add_option("--l2_size", type="string", default="512B") 58parser.add_option("--l1d_assoc", type="int", default=2) 59parser.add_option("--l1i_assoc", type="int", default=2) 60parser.add_option("--l2_assoc", type="int", default=2) 61 62execfile(os.path.join(config_root, "configs/common", "Options.py")) 63 64(options, args) = parser.parse_args() 65 66# this is a uniprocessor only test 67options.num_cpus = 1 68 69cpu = TimingSimpleCPU(cpu_id=0) 70system = System(cpu = cpu, 71 physmem = PhysicalMemory()) 72 73system.ruby = Ruby.create_system(options, system.physmem) 74 75assert(len(system.ruby.cpu_ruby_ports) == 1) 76 77# 78# Tie the cpu cache ports to the ruby cpu ports and 79# physmem, respectively 80# 81cpu.icache_port = system.ruby.cpu_ruby_ports[0].port 82cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port 83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root(system = system) 89root.system.mem_mode = 'timing' 90 91# Not much point in this being higher than the L1 latency 92m5.ticks.setGlobalFrequency('1ns') 93