simple-timing-ruby.py revision 11682
15331Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 25331Sgblack@eecs.umich.edu# All rights reserved. 35331Sgblack@eecs.umich.edu# 45331Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 55331Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 65331Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 75331Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 85331Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 95331Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 105331Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 115331Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 125331Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 135331Sgblack@eecs.umich.edu# this software without specific prior written permission. 145331Sgblack@eecs.umich.edu# 155331Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165331Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175331Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185331Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195331Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205331Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215331Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225331Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235331Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245331Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255331Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265331Sgblack@eecs.umich.edu# 275331Sgblack@eecs.umich.edu# Authors: Steve Reinhardt 285331Sgblack@eecs.umich.edu 295331Sgblack@eecs.umich.eduimport m5 304276Sgblack@eecs.umich.edufrom m5.objects import * 314276Sgblack@eecs.umich.edufrom m5.defines import buildEnv 324276Sgblack@eecs.umich.edufrom m5.util import addToPath 334276Sgblack@eecs.umich.eduimport os, optparse, sys 344276Sgblack@eecs.umich.edu 354276Sgblack@eecs.umich.edum5.util.addToPath('../configs/') 364276Sgblack@eecs.umich.edu 374276Sgblack@eecs.umich.edufrom ruby import Ruby 384276Sgblack@eecs.umich.edufrom common import Options 394276Sgblack@eecs.umich.edu 404276Sgblack@eecs.umich.eduparser = optparse.OptionParser() 414276Sgblack@eecs.umich.eduOptions.addCommonOptions(parser) 424276Sgblack@eecs.umich.edu 434276Sgblack@eecs.umich.edu# Add the ruby specific and protocol specific options 444276Sgblack@eecs.umich.eduRuby.define_options(parser) 454276Sgblack@eecs.umich.edu 464276Sgblack@eecs.umich.edu(options, args) = parser.parse_args() 474276Sgblack@eecs.umich.edu 484276Sgblack@eecs.umich.edu# 494276Sgblack@eecs.umich.edu# Set the default cache size and associativity to be very small to encourage 504276Sgblack@eecs.umich.edu# races between requests and writebacks. 514276Sgblack@eecs.umich.edu# 524276Sgblack@eecs.umich.eduoptions.l1d_size="256B" 534276Sgblack@eecs.umich.eduoptions.l1i_size="256B" 544276Sgblack@eecs.umich.eduoptions.l2_size="512B" 554276Sgblack@eecs.umich.eduoptions.l3_size="1kB" 564276Sgblack@eecs.umich.eduoptions.l1d_assoc=2 574276Sgblack@eecs.umich.eduoptions.l1i_assoc=2 584276Sgblack@eecs.umich.eduoptions.l2_assoc=2 594276Sgblack@eecs.umich.eduoptions.l3_assoc=2 604276Sgblack@eecs.umich.edu 614276Sgblack@eecs.umich.edu# this is a uniprocessor only test 624276Sgblack@eecs.umich.eduoptions.num_cpus = 1 634276Sgblack@eecs.umich.educpu = TimingSimpleCPU(cpu_id=0) 644276Sgblack@eecs.umich.edusystem = System(cpu = cpu) 654276Sgblack@eecs.umich.edu 664276Sgblack@eecs.umich.edu# Dummy voltage domain for all our clock domains 674276Sgblack@eecs.umich.edusystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 684276Sgblack@eecs.umich.edusystem.clk_domain = SrcClockDomain(clock = '1GHz', 694276Sgblack@eecs.umich.edu voltage_domain = system.voltage_domain) 704276Sgblack@eecs.umich.edu 714276Sgblack@eecs.umich.edu# Create a seperate clock domain for components that should run at 724276Sgblack@eecs.umich.edu# CPUs frequency 734276Sgblack@eecs.umich.edusystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 744276Sgblack@eecs.umich.edu voltage_domain = system.voltage_domain) 754276Sgblack@eecs.umich.edu 764276Sgblack@eecs.umich.edusystem.mem_ranges = AddrRange('256MB') 774276Sgblack@eecs.umich.eduRuby.create_system(options, False, system) 784276Sgblack@eecs.umich.edu 794276Sgblack@eecs.umich.edu# Create a separate clock for Ruby 804276Sgblack@eecs.umich.edusystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 814276Sgblack@eecs.umich.edu voltage_domain = system.voltage_domain) 824276Sgblack@eecs.umich.edu 834276Sgblack@eecs.umich.eduassert(len(system.ruby._cpu_ports) == 1) 844276Sgblack@eecs.umich.edu 854276Sgblack@eecs.umich.edu# create the interrupt controller 864276Sgblack@eecs.umich.educpu.createInterruptController() 874276Sgblack@eecs.umich.edu 884276Sgblack@eecs.umich.edu# 894711Sgblack@eecs.umich.edu# Tie the cpu cache ports to the ruby cpu ports and 904276Sgblack@eecs.umich.edu# physmem, respectively 914276Sgblack@eecs.umich.edu# 925238Sgblack@eecs.umich.educpu.connectAllPorts(system.ruby._cpu_ports[0]) 935238Sgblack@eecs.umich.edu 945238Sgblack@eecs.umich.edu# ----------------------- 955238Sgblack@eecs.umich.edu# run simulation 965937Sgblack@eecs.umich.edu# ----------------------- 975902Sgblack@eecs.umich.edu 985238Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 995238Sgblack@eecs.umich.eduroot.system.mem_mode = 'timing' 1005238Sgblack@eecs.umich.edu 1015238Sgblack@eecs.umich.edu# Not much point in this being higher than the L1 latency 1025238Sgblack@eecs.umich.edum5.ticks.setGlobalFrequency('1ns') 1035238Sgblack@eecs.umich.edu