simple-timing-ruby.py revision 11670:6ce719503eae 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31from m5.defines import buildEnv
32from m5.util import addToPath
33import os, optparse, sys
34
35m5.util.addToPath('../configs/common')
36m5.util.addToPath('../configs/')
37
38from ruby import Ruby
39import Options
40
41parser = optparse.OptionParser()
42Options.addCommonOptions(parser)
43
44# Add the ruby specific and protocol specific options
45Ruby.define_options(parser)
46
47(options, args) = parser.parse_args()
48
49#
50# Set the default cache size and associativity to be very small to encourage
51# races between requests and writebacks.
52#
53options.l1d_size="256B"
54options.l1i_size="256B"
55options.l2_size="512B"
56options.l3_size="1kB"
57options.l1d_assoc=2
58options.l1i_assoc=2
59options.l2_assoc=2
60options.l3_assoc=2
61
62# this is a uniprocessor only test
63options.num_cpus = 1
64cpu = TimingSimpleCPU(cpu_id=0)
65system = System(cpu = cpu)
66
67# Dummy voltage domain for all our clock domains
68system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
69system.clk_domain = SrcClockDomain(clock = '1GHz',
70                                   voltage_domain = system.voltage_domain)
71
72# Create a seperate clock domain for components that should run at
73# CPUs frequency
74system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
75                                       voltage_domain = system.voltage_domain)
76
77system.mem_ranges = AddrRange('256MB')
78Ruby.create_system(options, False, system)
79
80# Create a separate clock for Ruby
81system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
82                                        voltage_domain = system.voltage_domain)
83
84assert(len(system.ruby._cpu_ports) == 1)
85
86# create the interrupt controller
87cpu.createInterruptController()
88
89#
90# Tie the cpu cache ports to the ruby cpu ports and
91# physmem, respectively
92#
93cpu.connectAllPorts(system.ruby._cpu_ports[0])
94
95# -----------------------
96# run simulation
97# -----------------------
98
99root = Root(full_system = False, system = system)
100root.system.mem_mode = 'timing'
101
102# Not much point in this being higher than the L1 latency
103m5.ticks.setGlobalFrequency('1ns')
104