simple-timing-ruby.py revision 8801
16657Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 26657Snate@binkert.org# All rights reserved. 310972Sdavid.hashe@amd.com# 46657Snate@binkert.org# Redistribution and use in source and binary forms, with or without 56657Snate@binkert.org# modification, are permitted provided that the following conditions are 66657Snate@binkert.org# met: redistributions of source code must retain the above copyright 76657Snate@binkert.org# notice, this list of conditions and the following disclaimer; 86657Snate@binkert.org# redistributions in binary form must reproduce the above copyright 96657Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 106657Snate@binkert.org# documentation and/or other materials provided with the distribution; 116657Snate@binkert.org# neither the name of the copyright holders nor the names of its 126657Snate@binkert.org# contributors may be used to endorse or promote products derived from 136657Snate@binkert.org# this software without specific prior written permission. 146657Snate@binkert.org# 156657Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166657Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176657Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186657Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196657Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206657Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216657Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226657Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236657Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246657Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256657Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266657Snate@binkert.org# 276657Snate@binkert.org# Authors: Steve Reinhardt 286657Snate@binkert.org 296999Snate@binkert.orgimport m5 306657Snate@binkert.orgfrom m5.objects import * 316657Snate@binkert.orgfrom m5.defines import buildEnv 326657Snate@binkert.orgfrom m5.util import addToPath 336657Snate@binkert.orgimport os, optparse, sys 348189SLisa.Hsu@amd.com 356657Snate@binkert.orgif buildEnv['FULL_SYSTEM']: 369499Snilay@cs.wisc.edu panic("This script requires system-emulation mode (*_SE).") 379499Snilay@cs.wisc.edu 389364Snilay@cs.wisc.edu# Get paths we might need 397055Snate@binkert.orgconfig_path = os.path.dirname(os.path.abspath(__file__)) 406882SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 416882SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root) 428191SLisa.Hsu@amd.comaddToPath(config_root+'/configs/common') 436882SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/ruby') 446882SBrad.Beckmann@amd.com 459102SNuwan.Jayasena@amd.comimport Ruby 469366Snilay@cs.wisc.edu 479499Snilay@cs.wisc.eduparser = optparse.OptionParser() 489499Snilay@cs.wisc.edu 499499Snilay@cs.wisc.edu# 506882SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 516657Snate@binkert.org# 526657Snate@binkert.orgRuby.define_options(parser) 536657Snate@binkert.org 546657Snate@binkert.orgexecfile(os.path.join(config_root, "configs/common", "Options.py")) 5510311Snilay@cs.wisc.edu 5610311Snilay@cs.wisc.edu(options, args) = parser.parse_args() 5710311Snilay@cs.wisc.edu 5810311Snilay@cs.wisc.edu# 596657Snate@binkert.org# Set the default cache size and associativity to be very small to encourage 6010311Snilay@cs.wisc.edu# races between requests and writebacks. 619366Snilay@cs.wisc.edu# 627839Snilay@cs.wisc.eduoptions.l1d_size="256B" 636657Snate@binkert.orgoptions.l1i_size="256B" 646882SBrad.Beckmann@amd.comoptions.l2_size="512B" 6510308Snilay@cs.wisc.eduoptions.l3_size="1kB" 6610308Snilay@cs.wisc.eduoptions.l1d_assoc=2 676882SBrad.Beckmann@amd.comoptions.l1i_assoc=2 6810308Snilay@cs.wisc.eduoptions.l2_assoc=2 6910308Snilay@cs.wisc.eduoptions.l3_assoc=2 7010308Snilay@cs.wisc.edu 7110308Snilay@cs.wisc.edu# this is a uniprocessor only test 7210308Snilay@cs.wisc.eduoptions.num_cpus = 1 739366Snilay@cs.wisc.edu 749366Snilay@cs.wisc.educpu = TimingSimpleCPU(cpu_id=0) 756657Snate@binkert.orgsystem = System(cpu = cpu, physmem = PhysicalMemory()) 766657Snate@binkert.org 776657Snate@binkert.orgRuby.create_system(options, system) 786657Snate@binkert.org 799104Shestness@cs.utexas.eduassert(len(system.ruby._cpu_ruby_ports) == 1) 806657Snate@binkert.org 816657Snate@binkert.org# 826657Snate@binkert.org# Tie the cpu cache ports to the ruby cpu ports and 8310311Snilay@cs.wisc.edu# physmem, respectively 8410311Snilay@cs.wisc.edu# 8510311Snilay@cs.wisc.educpu.connectAllPorts(system.ruby._cpu_ruby_ports[0]) 8610311Snilay@cs.wisc.edu 876657Snate@binkert.org# Connect the system port for loading of binaries etc 887839Snilay@cs.wisc.edusystem.system_port = system.ruby._sys_port_proxy.port 897839Snilay@cs.wisc.edu 9010972Sdavid.hashe@amd.com# ----------------------- 9110972Sdavid.hashe@amd.com# run simulation 9210972Sdavid.hashe@amd.com# ----------------------- 936657Snate@binkert.org 946657Snate@binkert.orgroot = Root(full_system = False, system = system) 956657Snate@binkert.orgroot.system.mem_mode = 'timing' 966657Snate@binkert.org 976657Snate@binkert.org# Not much point in this being higher than the L1 latency 986657Snate@binkert.orgm5.ticks.setGlobalFrequency('1ns') 996657Snate@binkert.org