simple-timing-ruby.py revision 6928
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26166Ssteve.reinhardt@amd.com# All rights reserved. 36166Ssteve.reinhardt@amd.com# 46166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 56166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 66166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 76166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 86166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 96166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 106166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 116166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 126166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 136166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 146166Ssteve.reinhardt@amd.com# 156166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266166Ssteve.reinhardt@amd.com# 276166Ssteve.reinhardt@amd.com# Authors: Steve Reinhardt 286166Ssteve.reinhardt@amd.com 296166Ssteve.reinhardt@amd.comimport m5 306166Ssteve.reinhardt@amd.comfrom m5.objects import * 316928SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 326928SBrad.Beckmann@amd.comfrom m5.util import addToPath 336928SBrad.Beckmann@amd.comimport os, optparse, sys 346166Ssteve.reinhardt@amd.com 356928SBrad.Beckmann@amd.comif buildEnv['FULL_SYSTEM']: 366928SBrad.Beckmann@amd.com panic("This script requires system-emulation mode (*_SE).") 376928SBrad.Beckmann@amd.com 386928SBrad.Beckmann@amd.com# Get paths we might need 396928SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 406928SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 416928SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root) 426928SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/common') 436928SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/ruby') 446928SBrad.Beckmann@amd.com 456928SBrad.Beckmann@amd.comimport Ruby 466928SBrad.Beckmann@amd.com 476928SBrad.Beckmann@amd.comparser = optparse.OptionParser() 486928SBrad.Beckmann@amd.com 496928SBrad.Beckmann@amd.com# 506928SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 516928SBrad.Beckmann@amd.com# races between requests and writebacks. 526928SBrad.Beckmann@amd.com# 536928SBrad.Beckmann@amd.comparser.add_option("--l1d_size", type="string", default="256B") 546928SBrad.Beckmann@amd.comparser.add_option("--l1i_size", type="string", default="256B") 556928SBrad.Beckmann@amd.comparser.add_option("--l2_size", type="string", default="512B") 566928SBrad.Beckmann@amd.comparser.add_option("--l1d_assoc", type="int", default=2) 576928SBrad.Beckmann@amd.comparser.add_option("--l1i_assoc", type="int", default=2) 586928SBrad.Beckmann@amd.comparser.add_option("--l2_assoc", type="int", default=2) 596928SBrad.Beckmann@amd.com 606928SBrad.Beckmann@amd.comexecfile(os.path.join(config_root, "configs/common", "Options.py")) 616928SBrad.Beckmann@amd.com 626928SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 636928SBrad.Beckmann@amd.com 646928SBrad.Beckmann@amd.com# this is a uniprocessor only test 656928SBrad.Beckmann@amd.comoptions.num_cpus = 1 666289Snate@binkert.org 676166Ssteve.reinhardt@amd.comcpu = TimingSimpleCPU(cpu_id=0) 686166Ssteve.reinhardt@amd.comsystem = System(cpu = cpu, 696928SBrad.Beckmann@amd.com physmem = PhysicalMemory()) 706928SBrad.Beckmann@amd.com 716928SBrad.Beckmann@amd.comsystem.ruby = Ruby.create_system(options, system.physmem) 726928SBrad.Beckmann@amd.com 736928SBrad.Beckmann@amd.comassert(len(system.ruby.cpu_ruby_ports) == 1) 746928SBrad.Beckmann@amd.com 756928SBrad.Beckmann@amd.com# 766928SBrad.Beckmann@amd.com# Tie the cpu cache ports to the ruby cpu ports and 776928SBrad.Beckmann@amd.com# physmem, respectively 786928SBrad.Beckmann@amd.com# 796928SBrad.Beckmann@amd.comcpu.icache_port = system.ruby.cpu_ruby_ports[0].port 806928SBrad.Beckmann@amd.comcpu.dcache_port = system.ruby.cpu_ruby_ports[0].port 816928SBrad.Beckmann@amd.com 826928SBrad.Beckmann@amd.com# ----------------------- 836928SBrad.Beckmann@amd.com# run simulation 846928SBrad.Beckmann@amd.com# ----------------------- 856166Ssteve.reinhardt@amd.com 866166Ssteve.reinhardt@amd.comroot = Root(system = system) 876928SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing' 886928SBrad.Beckmann@amd.com 896928SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency 906928SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns') 91