simple-timing-mp-ruby.py revision 9113:9a72589ce4fd
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 27534Ssteve.reinhardt@amd.com# All rights reserved. 33395Shsul@eecs.umich.edu# 43395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 63395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133395Shsul@eecs.umich.edu# this software without specific prior written permission. 143395Shsul@eecs.umich.edu# 153395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263395Shsul@eecs.umich.edu# 273395Shsul@eecs.umich.edu# Authors: Ron Dreslinski 283395Shsul@eecs.umich.edu 293395Shsul@eecs.umich.eduimport m5 303395Shsul@eecs.umich.edufrom m5.objects import * 313509Shsul@eecs.umich.edufrom m5.defines import buildEnv 326654Snate@binkert.orgfrom m5.util import addToPath 333395Shsul@eecs.umich.eduimport os, optparse, sys 346654Snate@binkert.org 353395Shsul@eecs.umich.edu# Get paths we might need 366654Snate@binkert.orgconfig_path = os.path.dirname(os.path.abspath(__file__)) 378724Srdreslin@umich.educonfig_root = os.path.dirname(config_path) 386654Snate@binkert.orgm5_root = os.path.dirname(config_root) 396654Snate@binkert.orgaddToPath(config_root+'/configs/common') 403395Shsul@eecs.umich.eduaddToPath(config_root+'/configs/ruby') 419139Snilay@cs.wisc.eduaddToPath(config_root+'/configs/topologies') 429139Snilay@cs.wisc.edu 439139Snilay@cs.wisc.eduimport Options 449139Snilay@cs.wisc.eduimport Ruby 459139Snilay@cs.wisc.edu 469139Snilay@cs.wisc.eduparser = optparse.OptionParser() 479139Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 489139Snilay@cs.wisc.edu 499139Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 509139Snilay@cs.wisc.eduRuby.define_options(parser) 519139Snilay@cs.wisc.edu 529139Snilay@cs.wisc.edu(options, args) = parser.parse_args() 539139Snilay@cs.wisc.edu 549139Snilay@cs.wisc.edu# 559139Snilay@cs.wisc.edu# Set the default cache size and associativity to be very small to encourage 563481Shsul@eecs.umich.edu# races between requests and writebacks. 579139Snilay@cs.wisc.edu# 583481Shsul@eecs.umich.eduoptions.l1d_size="256B" 599139Snilay@cs.wisc.eduoptions.l1i_size="256B" 609139Snilay@cs.wisc.eduoptions.l2_size="512B" 619139Snilay@cs.wisc.eduoptions.l3_size="1kB" 629139Snilay@cs.wisc.eduoptions.l1d_assoc=2 639139Snilay@cs.wisc.eduoptions.l1i_assoc=2 649139Snilay@cs.wisc.eduoptions.l2_assoc=2 659139Snilay@cs.wisc.eduoptions.l3_assoc=2 669139Snilay@cs.wisc.edu 679139Snilay@cs.wisc.edunb_cores = 4 689139Snilay@cs.wisc.educpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 698718Snilay@cs.wisc.edu 709139Snilay@cs.wisc.edu# overwrite the num_cpus to equal nb_cores 713481Shsul@eecs.umich.eduoptions.num_cpus = nb_cores 729139Snilay@cs.wisc.edu 733481Shsul@eecs.umich.edu# system simulated 743481Shsul@eecs.umich.edusystem = System(cpu = cpus, physmem = SimpleMemory()) 759139Snilay@cs.wisc.edu 769139Snilay@cs.wisc.eduRuby.create_system(options, system) 773481Shsul@eecs.umich.edu 789139Snilay@cs.wisc.eduassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 799139Snilay@cs.wisc.edu 809139Snilay@cs.wisc.edufor (i, cpu) in enumerate(system.cpu): 819139Snilay@cs.wisc.edu # create the interrupt controller 829139Snilay@cs.wisc.edu cpu.createInterruptController() 833481Shsul@eecs.umich.edu 843481Shsul@eecs.umich.edu # 853481Shsul@eecs.umich.edu # Tie the cpu ports to the ruby cpu ports 868919Snilay@cs.wisc.edu # 878919Snilay@cs.wisc.edu cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i]) 888919Snilay@cs.wisc.edu 898919Snilay@cs.wisc.edu# ----------------------- 908919Snilay@cs.wisc.edu# run simulation 918919Snilay@cs.wisc.edu# ----------------------- 928919Snilay@cs.wisc.edu 938919Snilay@cs.wisc.eduroot = Root( full_system=False, system = system ) 948919Snilay@cs.wisc.eduroot.system.mem_mode = 'timing' 958919Snilay@cs.wisc.edu 968919Snilay@cs.wisc.edu# Not much point in this being higher than the L1 latency 978919Snilay@cs.wisc.edum5.ticks.setGlobalFrequency('1ns') 988919Snilay@cs.wisc.edu