simple-timing-mp-ruby.py revision 8808:8af87554ad7e
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 21762SN/A# All rights reserved. 32SN/A# 42SN/A# Redistribution and use in source and binary forms, with or without 52SN/A# modification, are permitted provided that the following conditions are 62SN/A# met: redistributions of source code must retain the above copyright 72SN/A# notice, this list of conditions and the following disclaimer; 82SN/A# redistributions in binary form must reproduce the above copyright 92SN/A# notice, this list of conditions and the following disclaimer in the 102SN/A# documentation and/or other materials provided with the distribution; 112SN/A# neither the name of the copyright holders nor the names of its 122SN/A# contributors may be used to endorse or promote products derived from 132SN/A# this software without specific prior written permission. 142SN/A# 152SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 282665Ssaidi@eecs.umich.edu 292SN/Aimport m5 302SN/Afrom m5.objects import * 312SN/Afrom m5.defines import buildEnv 322SN/Afrom m5.util import addToPath 332SN/Aimport os, optparse, sys 342SN/A 3556SN/A# Get paths we might need 361919SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 371919SN/Aconfig_root = os.path.dirname(config_path) 3856SN/Am5_root = os.path.dirname(config_root) 392SN/AaddToPath(config_root+'/configs/common') 401919SN/AaddToPath(config_root+'/configs/ruby') 412SN/A 422SN/Aimport Ruby 431919SN/A 441919SN/Aparser = optparse.OptionParser() 452SN/A 462SN/A# 472SN/A# Add the ruby specific and protocol specific options 481919SN/A# 491919SN/ARuby.define_options(parser) 502SN/A 511919SN/Aexecfile(os.path.join(config_root, "configs/common", "Options.py")) 521919SN/A 531919SN/A(options, args) = parser.parse_args() 542SN/A 552SN/A# 561919SN/A# Set the default cache size and associativity to be very small to encourage 571919SN/A# races between requests and writebacks. 582SN/A# 591919SN/Aoptions.l1d_size="256B" 601919SN/Aoptions.l1i_size="256B" 611919SN/Aoptions.l2_size="512B" 621919SN/Aoptions.l3_size="1kB" 631919SN/Aoptions.l1d_assoc=2 641919SN/Aoptions.l1i_assoc=2 651919SN/Aoptions.l2_assoc=2 661919SN/Aoptions.l3_assoc=2 671919SN/A 681919SN/Anb_cores = 4 692SN/Acpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 701919SN/A 711919SN/A# overwrite the num_cpus to equal nb_cores 721919SN/Aoptions.num_cpus = nb_cores 731919SN/A 741919SN/A# system simulated 751919SN/Asystem = System(cpu = cpus, physmem = PhysicalMemory()) 761919SN/A 771919SN/ARuby.create_system(options, system) 781919SN/A 791919SN/Aassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 801919SN/A 811919SN/Afor (i, cpu) in enumerate(system.cpu): 822SN/A # 832SN/A # Tie the cpu ports to the ruby cpu ports 842SN/A # 852SN/A cpu.icache_port = system.ruby._cpu_ruby_ports[i].port 86 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port 87 88# ----------------------- 89# run simulation 90# ----------------------- 91 92root = Root( full_system=False, system = system ) 93root.system.mem_mode = 'timing' 94 95# Not much point in this being higher than the L1 latency 96m5.ticks.setGlobalFrequency('1ns') 97