simple-timing-mp-ruby.py revision 8706
17841Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
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37841Sgblack@eecs.umich.edu#
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67841Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright
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137841Sgblack@eecs.umich.edu# this software without specific prior written permission.
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267841Sgblack@eecs.umich.edu#
277841Sgblack@eecs.umich.edu# Authors: Ron Dreslinski
287841Sgblack@eecs.umich.edu
297841Sgblack@eecs.umich.eduimport m5
307841Sgblack@eecs.umich.edufrom m5.objects import *
317841Sgblack@eecs.umich.edufrom m5.defines import buildEnv
327841Sgblack@eecs.umich.edufrom m5.util import addToPath
337841Sgblack@eecs.umich.eduimport os, optparse, sys
347841Sgblack@eecs.umich.edu
357841Sgblack@eecs.umich.eduif buildEnv['FULL_SYSTEM']:
367841Sgblack@eecs.umich.edu    panic("This script requires system-emulation mode (*_SE).")
377841Sgblack@eecs.umich.edu
387841Sgblack@eecs.umich.edu# Get paths we might need
397841Sgblack@eecs.umich.educonfig_path = os.path.dirname(os.path.abspath(__file__))
407841Sgblack@eecs.umich.educonfig_root = os.path.dirname(config_path)
417841Sgblack@eecs.umich.edum5_root = os.path.dirname(config_root)
427841Sgblack@eecs.umich.eduaddToPath(config_root+'/configs/common')
437841Sgblack@eecs.umich.eduaddToPath(config_root+'/configs/ruby')
447841Sgblack@eecs.umich.edu
457841Sgblack@eecs.umich.eduimport Ruby
467841Sgblack@eecs.umich.edu
477841Sgblack@eecs.umich.eduparser = optparse.OptionParser()
487841Sgblack@eecs.umich.edu
497841Sgblack@eecs.umich.edu#
507841Sgblack@eecs.umich.edu# Add the ruby specific and protocol specific options
517841Sgblack@eecs.umich.edu#
527841Sgblack@eecs.umich.eduRuby.define_options(parser)
537841Sgblack@eecs.umich.edu
547841Sgblack@eecs.umich.eduexecfile(os.path.join(config_root, "configs/common", "Options.py"))
557841Sgblack@eecs.umich.edu
567841Sgblack@eecs.umich.edu(options, args) = parser.parse_args()
577841Sgblack@eecs.umich.edu
587841Sgblack@eecs.umich.edu#
597841Sgblack@eecs.umich.edu# Set the default cache size and associativity to be very small to encourage
607841Sgblack@eecs.umich.edu# races between requests and writebacks.
617841Sgblack@eecs.umich.edu#
627841Sgblack@eecs.umich.eduoptions.l1d_size="256B"
637841Sgblack@eecs.umich.eduoptions.l1i_size="256B"
647841Sgblack@eecs.umich.eduoptions.l2_size="512B"
657841Sgblack@eecs.umich.eduoptions.l3_size="1kB"
667841Sgblack@eecs.umich.eduoptions.l1d_assoc=2
677841Sgblack@eecs.umich.eduoptions.l1i_assoc=2
687841Sgblack@eecs.umich.eduoptions.l2_assoc=2
697841Sgblack@eecs.umich.eduoptions.l3_assoc=2
707841Sgblack@eecs.umich.edu
717841Sgblack@eecs.umich.edunb_cores = 4
727841Sgblack@eecs.umich.educpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
737841Sgblack@eecs.umich.edu
747841Sgblack@eecs.umich.edu# overwrite the num_cpus to equal nb_cores
757841Sgblack@eecs.umich.eduoptions.num_cpus = nb_cores
767841Sgblack@eecs.umich.edu
777841Sgblack@eecs.umich.edu# system simulated
787841Sgblack@eecs.umich.edusystem = System(cpu = cpus, physmem = PhysicalMemory())
797841Sgblack@eecs.umich.edu
807841Sgblack@eecs.umich.eduRuby.create_system(options, system)
817841Sgblack@eecs.umich.edu
827841Sgblack@eecs.umich.eduassert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
837841Sgblack@eecs.umich.edu
847841Sgblack@eecs.umich.edufor (i, cpu) in enumerate(system.cpu):
857841Sgblack@eecs.umich.edu    #
867841Sgblack@eecs.umich.edu    # Tie the cpu ports to the ruby cpu ports
877841Sgblack@eecs.umich.edu    #
887841Sgblack@eecs.umich.edu    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
897841Sgblack@eecs.umich.edu    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
907841Sgblack@eecs.umich.edu
917841Sgblack@eecs.umich.edu# Connect the system port for loading of binaries etc
927841Sgblack@eecs.umich.edusystem.system_port = system.ruby._sys_port_proxy.port
937841Sgblack@eecs.umich.edu
94# -----------------------
95# run simulation
96# -----------------------
97
98root = Root( system = system )
99root.system.mem_mode = 'timing'
100
101# Not much point in this being higher than the L1 latency
102m5.ticks.setGlobalFrequency('1ns')
103