simple-timing-mp-ruby.py revision 13618:47a709f53226
12810SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 210771Sstephan.diestelhorst@arm.com# All rights reserved. 310028SGiacomo.Gabrielli@arm.com# 410028SGiacomo.Gabrielli@arm.com# Redistribution and use in source and binary forms, with or without 510028SGiacomo.Gabrielli@arm.com# modification, are permitted provided that the following conditions are 610028SGiacomo.Gabrielli@arm.com# met: redistributions of source code must retain the above copyright 710028SGiacomo.Gabrielli@arm.com# notice, this list of conditions and the following disclaimer; 810028SGiacomo.Gabrielli@arm.com# redistributions in binary form must reproduce the above copyright 910028SGiacomo.Gabrielli@arm.com# notice, this list of conditions and the following disclaimer in the 1010028SGiacomo.Gabrielli@arm.com# documentation and/or other materials provided with the distribution; 1110028SGiacomo.Gabrielli@arm.com# neither the name of the copyright holders nor the names of its 1210028SGiacomo.Gabrielli@arm.com# contributors may be used to endorse or promote products derived from 1310028SGiacomo.Gabrielli@arm.com# this software without specific prior written permission. 142810SN/A# 152810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262810SN/A# 272810SN/A# Authors: Ron Dreslinski 282810SN/A 292810SN/Aimport m5 302810SN/Afrom m5.objects import * 312810SN/Afrom m5.defines import buildEnv 322810SN/Afrom m5.util import addToPath 332810SN/Aimport os, optparse, sys 342810SN/A 352810SN/Am5.util.addToPath('../configs/') 362810SN/A 372810SN/Afrom common import Options 382810SN/Afrom ruby import Ruby 392810SN/A 402810SN/Aparser = optparse.OptionParser() 412810SN/AOptions.addCommonOptions(parser) 422810SN/A 432810SN/A# Add the ruby specific and protocol specific options 442810SN/ARuby.define_options(parser) 453861SN/A 462810SN/A(options, args) = parser.parse_args() 472810SN/A 4810623Smitch.hayenga@arm.com# 4910623Smitch.hayenga@arm.com# Set the default cache size and associativity to be very small to encourage 502810SN/A# races between requests and writebacks. 5112727Snikos.nikoleris@arm.com# 5211168Sandreas.hansson@arm.comoptions.l1d_size="256B" 5311168Sandreas.hansson@arm.comoptions.l1i_size="256B" 5412727Snikos.nikoleris@arm.comoptions.l2_size="512B" 5510623Smitch.hayenga@arm.comoptions.l3_size="1kB" 5612727Snikos.nikoleris@arm.comoptions.l1d_assoc=2 5712727Snikos.nikoleris@arm.comoptions.l1i_assoc=2 5812727Snikos.nikoleris@arm.comoptions.l2_assoc=2 592810SN/Aoptions.l3_assoc=2 6010623Smitch.hayenga@arm.com 612810SN/Anb_cores = 4 622810SN/Acpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 6310623Smitch.hayenga@arm.com 6410623Smitch.hayenga@arm.com# overwrite the num_cpus to equal nb_cores 6510623Smitch.hayenga@arm.comoptions.num_cpus = nb_cores 6610623Smitch.hayenga@arm.com 675875Ssteve.reinhardt@amd.com# system simulated 6810623Smitch.hayenga@arm.comsystem = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz')) 6910623Smitch.hayenga@arm.com 705875Ssteve.reinhardt@amd.com# Create a seperate clock domain for components that should run at 7110623Smitch.hayenga@arm.com# CPUs frequency 7210623Smitch.hayenga@arm.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 7310623Smitch.hayenga@arm.com 7410623Smitch.hayenga@arm.comRuby.create_system(options, False, system) 7510623Smitch.hayenga@arm.com 762810SN/A# Create a separate clock domain for Ruby 7710623Smitch.hayenga@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 7810623Smitch.hayenga@arm.com 7910623Smitch.hayenga@arm.comassert(options.num_cpus == len(system.ruby._cpu_ports)) 8010623Smitch.hayenga@arm.com 815875Ssteve.reinhardt@amd.comfor (i, cpu) in enumerate(system.cpu): 8210623Smitch.hayenga@arm.com # create the interrupt controller 8310028SGiacomo.Gabrielli@arm.com cpu.createInterruptController() 842810SN/A 855875Ssteve.reinhardt@amd.com # 865875Ssteve.reinhardt@amd.com # Tie the cpu ports to the ruby cpu ports 872810SN/A # 8810771Sstephan.diestelhorst@arm.com cpu.connectAllPorts(system.ruby._cpu_ports[i]) 8910771Sstephan.diestelhorst@arm.com 9010771Sstephan.diestelhorst@arm.com# ----------------------- 9110771Sstephan.diestelhorst@arm.com# run simulation 9210771Sstephan.diestelhorst@arm.com# ----------------------- 9310771Sstephan.diestelhorst@arm.com 9410771Sstephan.diestelhorst@arm.comroot = Root( full_system=False, system = system ) 9510771Sstephan.diestelhorst@arm.comroot.system.mem_mode = 'timing' 9610771Sstephan.diestelhorst@arm.com