simple-timing-mp-ruby.py revision 11670
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31from m5.defines import buildEnv 32from m5.util import addToPath 33import os, optparse, sys 34 35m5.util.addToPath('../configs/common') 36m5.util.addToPath('../configs/') 37 38import Options 39from ruby import Ruby 40 41parser = optparse.OptionParser() 42Options.addCommonOptions(parser) 43 44# Add the ruby specific and protocol specific options 45Ruby.define_options(parser) 46 47(options, args) = parser.parse_args() 48 49# 50# Set the default cache size and associativity to be very small to encourage 51# races between requests and writebacks. 52# 53options.l1d_size="256B" 54options.l1i_size="256B" 55options.l2_size="512B" 56options.l3_size="1kB" 57options.l1d_assoc=2 58options.l1i_assoc=2 59options.l2_assoc=2 60options.l3_assoc=2 61 62nb_cores = 4 63cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 64 65# overwrite the num_cpus to equal nb_cores 66options.num_cpus = nb_cores 67 68# system simulated 69system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz')) 70 71# Create a seperate clock domain for components that should run at 72# CPUs frequency 73system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 74 75Ruby.create_system(options, False, system) 76 77# Create a separate clock domain for Ruby 78system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 79 80assert(options.num_cpus == len(system.ruby._cpu_ports)) 81 82for (i, cpu) in enumerate(system.cpu): 83 # create the interrupt controller 84 cpu.createInterruptController() 85 86 # 87 # Tie the cpu ports to the ruby cpu ports 88 # 89 cpu.connectAllPorts(system.ruby._cpu_ports[i]) 90 91# ----------------------- 92# run simulation 93# ----------------------- 94 95root = Root( full_system=False, system = system ) 96root.system.mem_mode = 'timing' 97 98# Not much point in this being higher than the L1 latency 99m5.ticks.setGlobalFrequency('1ns') 100