simple-atomic-mp.py revision 9263:066099902102
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31 32# -------------------- 33# Base L1 Cache 34# ==================== 35 36class L1(BaseCache): 37 hit_latency = '1ns' 38 response_latency = '1ns' 39 block_size = 64 40 mshrs = 4 41 tgts_per_mshr = 8 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 50 hit_latency = '10ns' 51 response_latency = '10ns' 52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56nb_cores = 4 57cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 58 59# system simulated 60system = System(cpu = cpus, 61 physmem = SimpleMemory(range = AddrRange('1024MB')), 62 membus = CoherentBus()) 63 64# l2cache & bus 65system.toL2Bus = CoherentBus() 66system.l2c = L2(size='4MB', assoc=8) 67system.l2c.cpu_side = system.toL2Bus.master 68 69# connect l2c to membus 70system.l2c.mem_side = system.membus.slave 71 72# add L1 caches 73for cpu in cpus: 74 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 75 L1(size = '32kB', assoc = 4)) 76 # create the interrupt controller 77 cpu.createInterruptController() 78 # connect cpu level-1 caches to shared level-2 cache 79 cpu.connectAllPorts(system.toL2Bus, system.membus) 80 cpu.clock = '2GHz' 81 82# connect memory to membus 83system.physmem.port = system.membus.master 84 85# connect system port to membus 86system.system_port = system.membus.slave 87 88# ----------------------- 89# run simulation 90# ----------------------- 91 92root = Root( full_system = False, system = system ) 93root.system.mem_mode = 'atomic' 94