simple-atomic-mp.py revision 7876:189b9b258779 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37    latency = '1ns'
38    block_size = 64
39    mshrs = 4
40    tgts_per_mshr = 8
41
42# ----------------------
43# Base L2 Cache
44# ----------------------
45
46class L2(BaseCache):
47    block_size = 64
48    latency = '10ns'
49    mshrs = 92
50    tgts_per_mshr = 16
51    write_buffers = 8
52
53nb_cores = 4
54cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
55
56# system simulated
57system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
58Bus())
59
60# l2cache & bus
61system.toL2Bus = Bus()
62system.l2c = L2(size='4MB', assoc=8)
63system.l2c.cpu_side = system.toL2Bus.port
64system.l2c.num_cpus = nb_cores
65
66# connect l2c to membus
67system.l2c.mem_side = system.membus.port
68
69# add L1 caches
70for cpu in cpus:
71    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
72                                L1(size = '32kB', assoc = 4))
73    # connect cpu level-1 caches to shared level-2 cache
74    cpu.connectAllPorts(system.toL2Bus, system.membus)
75    cpu.clock = '2GHz'
76
77# connect memory to membus
78system.physmem.port = system.membus.port
79
80
81# -----------------------
82# run simulation
83# -----------------------
84
85root = Root( system = system )
86root.system.mem_mode = 'atomic'
87