simple-atomic-mp.py revision 3134:cf578b0dd70d
16145SN/A# Copyright (c) 2006 The Regents of The University of Michigan 26145SN/A# All rights reserved. 36145SN/A# 46145SN/A# Redistribution and use in source and binary forms, with or without 56145SN/A# modification, are permitted provided that the following conditions are 66145SN/A# met: redistributions of source code must retain the above copyright 76145SN/A# notice, this list of conditions and the following disclaimer; 86145SN/A# redistributions in binary form must reproduce the above copyright 96145SN/A# notice, this list of conditions and the following disclaimer in the 106145SN/A# documentation and/or other materials provided with the distribution; 116145SN/A# neither the name of the copyright holders nor the names of its 126145SN/A# contributors may be used to endorse or promote products derived from 136145SN/A# this software without specific prior written permission. 146145SN/A# 156145SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166145SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176145SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186145SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196145SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206145SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216145SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226145SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236145SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246145SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256145SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266145SN/A# 276145SN/A# Authors: Ron Dreslinski 286145SN/A 296145SN/Aimport m5 307039SN/Afrom m5.objects import * 316145SN/A 326145SN/A# -------------------- 336145SN/A# Base L1 Cache 347039SN/A# ==================== 357039SN/A 366145SN/Aclass L1(BaseCache): 377456SN/A latency = 1 387832SN/A block_size = 64 397456SN/A mshrs = 4 407002SN/A tgts_per_mshr = 8 418229SN/A protocol = CoherenceProtocol(protocol='moesi') 427456SN/A 437002SN/A# ---------------------- 4411021Sjthestness@gmail.com# Base L2 Cache 458229SN/A# ---------------------- 466154SN/A 476154SN/Aclass L2(BaseCache): 4810301Snilay@cs.wisc.edu block_size = 64 4911021Sjthestness@gmail.com latency = 100 5011021Sjthestness@gmail.com mshrs = 92 516145SN/A tgts_per_mshr = 16 5211021Sjthestness@gmail.com write_buffers = 8 537039SN/A 547039SN/Anb_cores = 4 5511021Sjthestness@gmail.comcpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ] 5611021Sjthestness@gmail.com 576145SN/A# system simulated 5811111Snilay@cs.wisc.edusystem = System(cpu = cpus, physmem = PhysicalMemory(), membus = 5911111Snilay@cs.wisc.eduBus()) 6011111Snilay@cs.wisc.edu 617567SN/A# l2cache & bus 627039SN/Asystem.toL2Bus = Bus() 6311111Snilay@cs.wisc.edusystem.l2c = L2(size='4MB', assoc=8) 646145SN/Asystem.l2c.cpu_side = system.toL2Bus.port 657039SN/A 6611111Snilay@cs.wisc.edu# connect l2c to membus 677039SN/Asystem.l2c.mem_side = system.membus.port 6810893Snilay@cs.wisc.edu 697456SN/A# add L1 caches 7010893Snilay@cs.wisc.edufor cpu in cpus: 717456SN/A cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 7211111Snilay@cs.wisc.edu L1(size = '32kB', assoc = 4)) 737039SN/A cpu.mem = cpu.dcache 746145SN/A # connect cpu level-1 caches to shared level-2 cache 7511111Snilay@cs.wisc.edu cpu.connectMemPorts(system.toL2Bus) 767039SN/A 777039SN/A# connect memory to membus 789602SN/Asystem.physmem.port = system.membus.port 797039SN/A 8011021Sjthestness@gmail.com 819629SN/A# ----------------------- 829629SN/A# run simulation 839629SN/A# ----------------------- 849629SN/A 859629SN/Aroot = Root( system = system ) 869602SN/Aroot.system.mem_mode = 'atomic' 877039SN/A