rubytest-ruby.py revision 9827:f47274776aa0
16019SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26019SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 37134Sgblack@eecs.umich.edu# All rights reserved. 47134Sgblack@eecs.umich.edu# 57134Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 67134Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 77134Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 87134Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 97134Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 107134Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 117134Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 127134Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 137134Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 147134Sgblack@eecs.umich.edu# this software without specific prior written permission. 156019SN/A# 166019SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019SN/A# 286019SN/A# Authors: Ron Dreslinski 296019SN/A# Brad Beckmann 306019SN/A 316019SN/Aimport m5 326019SN/Afrom m5.objects import * 336019SN/Afrom m5.defines import buildEnv 346019SN/Afrom m5.util import addToPath 356019SN/Aimport os, optparse, sys 366019SN/A 376019SN/A# Get paths we might need. It's expected this file is in m5/configs/example. 386019SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 396019SN/Aconfig_root = os.path.dirname(config_path) 406019SN/Am5_root = os.path.dirname(config_root) 416019SN/AaddToPath(config_root+'/configs/common') 426308SN/AaddToPath(config_root+'/configs/ruby') 436308SN/AaddToPath(config_root+'/configs/topologies') 446309SN/A 456309SN/Aimport Ruby 466309SN/Aimport Options 476309SN/A 486309SN/Aparser = optparse.OptionParser() 497134Sgblack@eecs.umich.eduOptions.addCommonOptions(parser) 507296Sgblack@eecs.umich.edu 516309SN/A# Add the ruby specific and protocol specific options 526309SN/ARuby.define_options(parser) 537296Sgblack@eecs.umich.edu 548139SMatt.Horsnell@arm.com(options, args) = parser.parse_args() 556309SN/A 566309SN/A# 576309SN/A# Set the default cache size and associativity to be very small to encourage 587342Sgblack@eecs.umich.edu# races between requests and writebacks. 597174Sgblack@eecs.umich.edu# 607639Sgblack@eecs.umich.eduoptions.l1d_size="256B" 617639Sgblack@eecs.umich.eduoptions.l1i_size="256B" 627644Sali.saidi@arm.comoptions.l2_size="512B" 638139SMatt.Horsnell@arm.comoptions.l3_size="1kB" 647639Sgblack@eecs.umich.eduoptions.l1d_assoc=2 657639Sgblack@eecs.umich.eduoptions.l1i_assoc=2 667639Sgblack@eecs.umich.eduoptions.l2_assoc=2 677639Sgblack@eecs.umich.eduoptions.l3_assoc=2 687639Sgblack@eecs.umich.edu 697639Sgblack@eecs.umich.edu# Turn on flush check for the hammer protocol 707639Sgblack@eecs.umich.educheck_flush = False 717644Sali.saidi@arm.comif buildEnv['PROTOCOL'] == 'MOESI_hammer': 728139SMatt.Horsnell@arm.com check_flush = True 737639Sgblack@eecs.umich.edu 747639Sgblack@eecs.umich.edu# 757639Sgblack@eecs.umich.edu# create the tester and system, including ruby 767639Sgblack@eecs.umich.edu# 777639Sgblack@eecs.umich.edutester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 787639Sgblack@eecs.umich.edu wakeup_frequency = 10, num_cpus = options.num_cpus) 797639Sgblack@eecs.umich.edu 807639Sgblack@eecs.umich.edusystem = System(tester = tester, physmem = SimpleMemory(null = True)) 817639Sgblack@eecs.umich.edu# Dummy voltage domain for all our clock domains 827644Sali.saidi@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 838139SMatt.Horsnell@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 847639Sgblack@eecs.umich.edu voltage_domain = system.voltage_domain) 857639Sgblack@eecs.umich.edu 867639Sgblack@eecs.umich.edusystem.mem_ranges = AddrRange('256MB') 877639Sgblack@eecs.umich.edu 887174Sgblack@eecs.umich.eduRuby.create_system(options, system) 898148SAli.Saidi@ARM.com 908303SAli.Saidi@ARM.com# Create a separate clock domain for Ruby 917400SAli.Saidi@ARM.comsystem.ruby.clk_domain = SrcClockDomain(clock = '1GHz', 928303SAli.Saidi@ARM.com voltage_domain = system.voltage_domain) 938303SAli.Saidi@ARM.com 948303SAli.Saidi@ARM.comassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 958303SAli.Saidi@ARM.com 968303SAli.Saidi@ARM.com# 978303SAli.Saidi@ARM.com# The tester is most effective when randomization is turned on and 988303SAli.Saidi@ARM.com# artifical delay is randomly inserted on messages 998303SAli.Saidi@ARM.com# 1008303SAli.Saidi@ARM.comsystem.ruby.randomization = True 1018205SAli.Saidi@ARM.com 1027858SMatt.Horsnell@arm.comfor ruby_port in system.ruby._cpu_ruby_ports: 1038285SPrakash.Ramrakhyani@arm.com # 1046754SN/A # Tie the ruby tester ports to the ruby cpu read and write ports 1058148SAli.Saidi@ARM.com # 1066754SN/A if ruby_port.support_data_reqs: 1076754SN/A tester.cpuDataPort = ruby_port.slave 1088148SAli.Saidi@ARM.com if ruby_port.support_inst_reqs: 1098148SAli.Saidi@ARM.com tester.cpuInstPort = ruby_port.slave 1106754SN/A 1118139SMatt.Horsnell@arm.com # 1127422Sgblack@eecs.umich.edu # Tell the sequencer this is the ruby tester so that it 1138148SAli.Saidi@ARM.com # copies the subblock back to the checker 1148148SAli.Saidi@ARM.com # 1156754SN/A ruby_port.using_ruby_tester = True 1168139SMatt.Horsnell@arm.com 1176309SN/A# ----------------------- 1186309SN/A# run simulation 1197296Sgblack@eecs.umich.edu# ----------------------- 1207303Sgblack@eecs.umich.edu 1218139SMatt.Horsnell@arm.comroot = Root(full_system = False, system = system ) 1226309SN/Aroot.system.mem_mode = 'timing' 1236309SN/A 1246309SN/A# Not much point in this being higher than the L1 latency 1257296Sgblack@eecs.umich.edum5.ticks.setGlobalFrequency('1ns') 1267174Sgblack@eecs.umich.edu