rubytest-ruby.py revision 8931:7a1dfb191e3f
12810SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
212728Snikos.nikoleris@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
39796Sprakash.ramrakhyani@arm.com# All rights reserved.
49796Sprakash.ramrakhyani@arm.com#
59796Sprakash.ramrakhyani@arm.com# Redistribution and use in source and binary forms, with or without
69796Sprakash.ramrakhyani@arm.com# modification, are permitted provided that the following conditions are
79796Sprakash.ramrakhyani@arm.com# met: redistributions of source code must retain the above copyright
89796Sprakash.ramrakhyani@arm.com# notice, this list of conditions and the following disclaimer;
99796Sprakash.ramrakhyani@arm.com# redistributions in binary form must reproduce the above copyright
109796Sprakash.ramrakhyani@arm.com# notice, this list of conditions and the following disclaimer in the
119796Sprakash.ramrakhyani@arm.com# documentation and/or other materials provided with the distribution;
129796Sprakash.ramrakhyani@arm.com# neither the name of the copyright holders nor the names of its
139796Sprakash.ramrakhyani@arm.com# contributors may be used to endorse or promote products derived from
142810SN/A# this software without specific prior written permission.
152810SN/A#
162810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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242810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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262810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810SN/A#
282810SN/A# Authors: Ron Dreslinski
292810SN/A#          Brad Beckmann
302810SN/A
312810SN/Aimport m5
322810SN/Afrom m5.objects import *
332810SN/Afrom m5.defines import buildEnv
342810SN/Afrom m5.util import addToPath
352810SN/Aimport os, optparse, sys
362810SN/A
372810SN/A# Get paths we might need.  It's expected this file is in m5/configs/example.
382810SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__))
392810SN/Aconfig_root = os.path.dirname(config_path)
402810SN/Am5_root = os.path.dirname(config_root)
412810SN/AaddToPath(config_root+'/configs/common')
422810SN/AaddToPath(config_root+'/configs/ruby')
432810SN/A
442810SN/Aimport Ruby
452810SN/Aimport Options
462810SN/A
472810SN/Aparser = optparse.OptionParser()
482810SN/AOptions.addCommonOptions(parser)
4911486Snikos.nikoleris@arm.com
5011486Snikos.nikoleris@arm.com# Add the ruby specific and protocol specific options
5112727Snikos.nikoleris@arm.comRuby.define_options(parser)
5212727Snikos.nikoleris@arm.com
5312727Snikos.nikoleris@arm.com(options, args) = parser.parse_args()
545338Sstever@gmail.com
5513225Sodanrc@yahoo.com.br#
5613219Sodanrc@yahoo.com.br# Set the default cache size and associativity to be very small to encourage
5712727Snikos.nikoleris@arm.com# races between requests and writebacks.
5812727Snikos.nikoleris@arm.com#
592810SN/Aoptions.l1d_size="256B"
6012727Snikos.nikoleris@arm.comoptions.l1i_size="256B"
612810SN/Aoptions.l2_size="512B"
629796Sprakash.ramrakhyani@arm.comoptions.l3_size="1kB"
6311893Snikos.nikoleris@arm.comoptions.l1d_assoc=2
6413418Sodanrc@yahoo.com.broptions.l1i_assoc=2
6513219Sodanrc@yahoo.com.broptions.l2_assoc=2
6612513Sodanrc@yahoo.com.broptions.l3_assoc=2
6712629Sodanrc@yahoo.com.br
6812629Sodanrc@yahoo.com.br#
699796Sprakash.ramrakhyani@arm.com# create the tester and system, including ruby
709796Sprakash.ramrakhyani@arm.com#
719796Sprakash.ramrakhyani@arm.comtester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
722810SN/A
732810SN/Asystem = System(tester = tester, physmem = SimpleMemory())
742810SN/A
7510360Sandreas.hansson@arm.comRuby.create_system(options, system)
762810SN/A
772810SN/Aassert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
782810SN/A
7913219Sodanrc@yahoo.com.br#
8013219Sodanrc@yahoo.com.br# The tester is most effective when randomization is turned on and
8113217Sodanrc@yahoo.com.br# artifical delay is randomly inserted on messages
8213219Sodanrc@yahoo.com.br#
8313217Sodanrc@yahoo.com.brsystem.ruby.randomization = True
8413217Sodanrc@yahoo.com.br
8513217Sodanrc@yahoo.com.brfor ruby_port in system.ruby._cpu_ruby_ports:
8613217Sodanrc@yahoo.com.br    #
8713217Sodanrc@yahoo.com.br    # Tie the ruby tester ports to the ruby cpu ports
8813217Sodanrc@yahoo.com.br    #
8913217Sodanrc@yahoo.com.br    tester.cpuPort = ruby_port.slave
9013217Sodanrc@yahoo.com.br
9113219Sodanrc@yahoo.com.br    #
9213219Sodanrc@yahoo.com.br    # Tell the sequencer this is the ruby tester so that it
9313219Sodanrc@yahoo.com.br    # copies the subblock back to the checker
9413217Sodanrc@yahoo.com.br    #
9513217Sodanrc@yahoo.com.br    ruby_port.using_ruby_tester = True
9613219Sodanrc@yahoo.com.br
9713217Sodanrc@yahoo.com.br    #
9813217Sodanrc@yahoo.com.br    # Ruby doesn't need the backing image of memory when running with
9913217Sodanrc@yahoo.com.br    # the tester.
10013217Sodanrc@yahoo.com.br    #
10113217Sodanrc@yahoo.com.br    ruby_port.access_phys_mem = False
10213217Sodanrc@yahoo.com.br
10313217Sodanrc@yahoo.com.br# -----------------------
10413217Sodanrc@yahoo.com.br# run simulation
10513217Sodanrc@yahoo.com.br# -----------------------
10613217Sodanrc@yahoo.com.br
10713217Sodanrc@yahoo.com.brroot = Root(full_system = False, system = system )
1082810SN/Aroot.system.mem_mode = 'timing'
10913215Sodanrc@yahoo.com.br
11013215Sodanrc@yahoo.com.br# Not much point in this being higher than the L1 latency
11113215Sodanrc@yahoo.com.brm5.ticks.setGlobalFrequency('1ns')
11212636Sodanrc@yahoo.com.br