rubytest-ruby.py revision 8706
17586SAli.Saidi@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27586SAli.Saidi@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 37586SAli.Saidi@arm.com# All rights reserved. 47586SAli.Saidi@arm.com# 57586SAli.Saidi@arm.com# Redistribution and use in source and binary forms, with or without 67586SAli.Saidi@arm.com# modification, are permitted provided that the following conditions are 77586SAli.Saidi@arm.com# met: redistributions of source code must retain the above copyright 87586SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer; 97586SAli.Saidi@arm.com# redistributions in binary form must reproduce the above copyright 107586SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer in the 117586SAli.Saidi@arm.com# documentation and/or other materials provided with the distribution; 127586SAli.Saidi@arm.com# neither the name of the copyright holders nor the names of its 133970Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143005Sstever@eecs.umich.edu# this software without specific prior written permission. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273005Sstever@eecs.umich.edu# 283005Sstever@eecs.umich.edu# Authors: Ron Dreslinski 293005Sstever@eecs.umich.edu# Brad Beckmann 303005Sstever@eecs.umich.edu 313005Sstever@eecs.umich.eduimport m5 323005Sstever@eecs.umich.edufrom m5.objects import * 333005Sstever@eecs.umich.edufrom m5.defines import buildEnv 343005Sstever@eecs.umich.edufrom m5.util import addToPath 353005Sstever@eecs.umich.eduimport os, optparse, sys 363005Sstever@eecs.umich.edu 373005Sstever@eecs.umich.eduif buildEnv['FULL_SYSTEM']: 383005Sstever@eecs.umich.edu panic("This script requires system-emulation mode (*_SE).") 393005Sstever@eecs.umich.edu 403005Sstever@eecs.umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 416654Snate@binkert.orgconfig_path = os.path.dirname(os.path.abspath(__file__)) 426654Snate@binkert.orgconfig_root = os.path.dirname(config_path) 436654Snate@binkert.orgm5_root = os.path.dirname(config_root) 442889SN/AaddToPath(config_root+'/configs/common') 452710SN/AaddToPath(config_root+'/configs/ruby') 466654Snate@binkert.org 476654Snate@binkert.orgimport Ruby 486654Snate@binkert.org 495457Ssaidi@eecs.umich.eduparser = optparse.OptionParser() 506654Snate@binkert.org 516654Snate@binkert.org# 525457Ssaidi@eecs.umich.edu# Add the ruby specific and protocol specific options 536654Snate@binkert.org# 546654Snate@binkert.orgRuby.define_options(parser) 552934SN/A 562549SN/Aexecfile(os.path.join(config_root, "configs/common", "Options.py")) 572995SN/A 583395Shsul@eecs.umich.edu(options, args) = parser.parse_args() 596981SLisa.Hsu@amd.com 603448Shsul@eecs.umich.edu# 612549SN/A# Set the default cache size and associativity to be very small to encourage 623444Sktlim@umich.edu# races between requests and writebacks. 633444Sktlim@umich.edu# 643444Sktlim@umich.eduoptions.l1d_size="256B" 653444Sktlim@umich.eduoptions.l1i_size="256B" 662889SN/Aoptions.l2_size="512B" 672710SN/Aoptions.l3_size="1kB" 687861Sgblack@eecs.umich.eduoptions.l1d_assoc=2 697861Sgblack@eecs.umich.eduoptions.l1i_assoc=2 707861Sgblack@eecs.umich.eduoptions.l2_assoc=2 717861Sgblack@eecs.umich.eduoptions.l3_assoc=2 723873Sbinkertn@umich.edu 733873Sbinkertn@umich.edu# 743873Sbinkertn@umich.edu# create the tester and system, including ruby 757586SAli.Saidi@arm.com# 767586SAli.Saidi@arm.comtester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10) 777586SAli.Saidi@arm.com 787586SAli.Saidi@arm.comsystem = System(tester = tester, physmem = PhysicalMemory()) 797586SAli.Saidi@arm.com 803322Shsul@eecs.umich.eduRuby.create_system(options, system) 812995SN/A 822995SN/Aassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 832995SN/A 842995SN/A# 852995SN/A# The tester is most effective when randomization is turned on and 863143Shsul@eecs.umich.edu# artifical delay is randomly inserted on messages 873322Shsul@eecs.umich.edu# 883322Shsul@eecs.umich.edusystem.ruby.randomization = True 893025Ssaidi@eecs.umich.edu 903143Shsul@eecs.umich.edufor ruby_port in system.ruby._cpu_ruby_ports: 913143Shsul@eecs.umich.edu # 923322Shsul@eecs.umich.edu # Tie the ruby tester ports to the ruby cpu ports 933444Sktlim@umich.edu # 943322Shsul@eecs.umich.edu tester.cpuPort = ruby_port.port 952710SN/A 962710SN/A # 972710SN/A # Tell the sequencer this is the ruby tester so that it 982710SN/A # copies the subblock back to the checker 992710SN/A # 1002710SN/A ruby_port.using_ruby_tester = True 1013322Shsul@eecs.umich.edu 1023304Sstever@eecs.umich.edu # 1033322Shsul@eecs.umich.edu # Ruby doesn't need the backing image of memory when running with 1043322Shsul@eecs.umich.edu # the tester. 1053304Sstever@eecs.umich.edu # 1063481Shsul@eecs.umich.edu ruby_port.access_phys_mem = False 1073481Shsul@eecs.umich.edu 1082566SN/A# Connect the system port for loading of binaries etc 1093322Shsul@eecs.umich.edusystem.system_port = system.ruby._sys_port_proxy.port 1103322Shsul@eecs.umich.edu 1112995SN/A# ----------------------- 1122995SN/A# run simulation 1133304Sstever@eecs.umich.edu# ----------------------- 1143304Sstever@eecs.umich.edu 1153304Sstever@eecs.umich.eduroot = Root( system = system ) 1162995SN/Aroot.system.mem_mode = 'timing' 1172995SN/A 1182995SN/A# Not much point in this being higher than the L1 latency 1192917SN/Am5.ticks.setGlobalFrequency('1ns') 1202995SN/A