rubytest-ruby.py revision 11682
16657Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 26657Snate@binkert.org# Copyright (c) 2009 Advanced Micro Devices, Inc. 310972Sdavid.hashe@amd.com# All rights reserved. 46657Snate@binkert.org# 56657Snate@binkert.org# Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org# modification, are permitted provided that the following conditions are 76657Snate@binkert.org# met: redistributions of source code must retain the above copyright 86657Snate@binkert.org# notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org# redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org# documentation and/or other materials provided with the distribution; 126657Snate@binkert.org# neither the name of the copyright holders nor the names of its 136657Snate@binkert.org# contributors may be used to endorse or promote products derived from 146657Snate@binkert.org# this software without specific prior written permission. 156657Snate@binkert.org# 166657Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org# 286657Snate@binkert.org# Authors: Ron Dreslinski 296999Snate@binkert.org# Brad Beckmann 306657Snate@binkert.org 316657Snate@binkert.orgimport m5 326657Snate@binkert.orgfrom m5.objects import * 336657Snate@binkert.orgfrom m5.defines import buildEnv 348189SLisa.Hsu@amd.comfrom m5.util import addToPath 356657Snate@binkert.orgimport os, optparse, sys 369499Snilay@cs.wisc.edu 379499Snilay@cs.wisc.edum5.util.addToPath('../configs/') 389364Snilay@cs.wisc.edu 397055Snate@binkert.orgfrom ruby import Ruby 406882SBrad.Beckmann@amd.comfrom common import Options 416882SBrad.Beckmann@amd.com 428191SLisa.Hsu@amd.comparser = optparse.OptionParser() 436882SBrad.Beckmann@amd.comOptions.addCommonOptions(parser) 446882SBrad.Beckmann@amd.com 459102SNuwan.Jayasena@amd.com# Add the ruby specific and protocol specific options 4611084Snilay@cs.wisc.eduRuby.define_options(parser) 479366Snilay@cs.wisc.edu 489499Snilay@cs.wisc.edu(options, args) = parser.parse_args() 499499Snilay@cs.wisc.edu 509499Snilay@cs.wisc.edu# 516882SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 526657Snate@binkert.org# races between requests and writebacks. 536657Snate@binkert.org# 546657Snate@binkert.orgoptions.l1d_size="256B" 556657Snate@binkert.orgoptions.l1i_size="256B" 5610311Snilay@cs.wisc.eduoptions.l2_size="512B" 5710311Snilay@cs.wisc.eduoptions.l3_size="1kB" 5810311Snilay@cs.wisc.eduoptions.l1d_assoc=2 5910311Snilay@cs.wisc.eduoptions.l1i_assoc=2 606657Snate@binkert.orgoptions.l2_assoc=2 6110311Snilay@cs.wisc.eduoptions.l3_assoc=2 629366Snilay@cs.wisc.eduoptions.ports=32 637839Snilay@cs.wisc.edu 646657Snate@binkert.org# Turn on flush check for the hammer protocol 656882SBrad.Beckmann@amd.comcheck_flush = False 6610308Snilay@cs.wisc.eduif buildEnv['PROTOCOL'] == 'MOESI_hammer': 6710308Snilay@cs.wisc.edu check_flush = True 686882SBrad.Beckmann@amd.com 6910308Snilay@cs.wisc.edu# 7010308Snilay@cs.wisc.edu# create the tester and system, including ruby 7110308Snilay@cs.wisc.edu# 7210308Snilay@cs.wisc.edutester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 7310308Snilay@cs.wisc.edu wakeup_frequency = 10, num_cpus = options.num_cpus) 749366Snilay@cs.wisc.edu 759366Snilay@cs.wisc.edu# We set the testers as cpu for ruby to find the correct clock domains 766657Snate@binkert.org# for the L1 Objects. 776657Snate@binkert.orgsystem = System(cpu = tester) 786657Snate@binkert.org 796657Snate@binkert.org# Dummy voltage domain for all our clock domains 809104Shestness@cs.utexas.edusystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 816657Snate@binkert.orgsystem.clk_domain = SrcClockDomain(clock = '1GHz', 826657Snate@binkert.org voltage_domain = system.voltage_domain) 836657Snate@binkert.org 8410311Snilay@cs.wisc.edusystem.mem_ranges = AddrRange('256MB') 8510311Snilay@cs.wisc.edu 8610311Snilay@cs.wisc.eduRuby.create_system(options, False, system) 8710311Snilay@cs.wisc.edu 886657Snate@binkert.org# Create a separate clock domain for Ruby 897839Snilay@cs.wisc.edusystem.ruby.clk_domain = SrcClockDomain(clock = '1GHz', 907839Snilay@cs.wisc.edu voltage_domain = system.voltage_domain) 9110972Sdavid.hashe@amd.com 9210972Sdavid.hashe@amd.comassert(options.num_cpus == len(system.ruby._cpu_ports)) 9310972Sdavid.hashe@amd.com 946657Snate@binkert.orgtester.num_cpus = len(system.ruby._cpu_ports) 956657Snate@binkert.org 966657Snate@binkert.org# 976657Snate@binkert.org# The tester is most effective when randomization is turned on and 986657Snate@binkert.org# artifical delay is randomly inserted on messages 996657Snate@binkert.org# 1006657Snate@binkert.orgsystem.ruby.randomization = True 1016657Snate@binkert.org 1026657Snate@binkert.orgfor ruby_port in system.ruby._cpu_ports: 1036657Snate@binkert.org # 1046657Snate@binkert.org # Tie the ruby tester ports to the ruby cpu read and write ports 1056657Snate@binkert.org # 1066657Snate@binkert.org if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: 1076657Snate@binkert.org tester.cpuInstDataPort = ruby_port.slave 1086657Snate@binkert.org elif ruby_port.support_data_reqs: 1096657Snate@binkert.org tester.cpuDataPort = ruby_port.slave 1106657Snate@binkert.org elif ruby_port.support_inst_reqs: 1116657Snate@binkert.org tester.cpuInstPort = ruby_port.slave 1126779SBrad.Beckmann@amd.com 1136657Snate@binkert.org # Do not automatically retry stalled Ruby requests 1146657Snate@binkert.org ruby_port.no_retry_on_stall = True 1156657Snate@binkert.org 1166657Snate@binkert.org # 1176657Snate@binkert.org # Tell the sequencer this is the ruby tester so that it 1186657Snate@binkert.org # copies the subblock back to the checker 1196657Snate@binkert.org # 1206657Snate@binkert.org ruby_port.using_ruby_tester = True 1216657Snate@binkert.org 12210972Sdavid.hashe@amd.com# ----------------------- 12310972Sdavid.hashe@amd.com# run simulation 12410972Sdavid.hashe@amd.com# ----------------------- 1259104Shestness@cs.utexas.edu 1269104Shestness@cs.utexas.eduroot = Root(full_system = False, system = system ) 1279104Shestness@cs.utexas.eduroot.system.mem_mode = 'timing' 1289104Shestness@cs.utexas.edu 1296657Snate@binkert.org# Not much point in this being higher than the L1 latency 1306657Snate@binkert.orgm5.ticks.setGlobalFrequency('1ns') 1316657Snate@binkert.org