realview-simple-atomic.py revision 8876 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39    latency = '1ns'
40    block_size = 64
41    mshrs = 4
42    tgts_per_mshr = 8
43    is_top_level = True
44
45# ----------------------
46# Base L2 Cache
47# ----------------------
48
49class L2(BaseCache):
50    block_size = 64
51    latency = '10ns'
52    mshrs = 92
53    tgts_per_mshr = 16
54    write_buffers = 8
55
56# ---------------------
57# I/O Cache
58# ---------------------
59class IOCache(BaseCache):
60    assoc = 8
61    block_size = 64
62    latency = '50ns'
63    mshrs = 20
64    size = '1kB'
65    tgts_per_mshr = 12
66    addr_range=AddrRange(0, size='256MB')
67    forward_snoops = False
68
69#cpu
70cpu = AtomicSimpleCPU(cpu_id=0)
71#the system
72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
73system.iocache = IOCache()
74system.iocache.cpu_side = system.iobus.master
75system.iocache.mem_side = system.membus.slave
76
77system.cpu = cpu
78#create the l1/l2 bus
79system.toL2Bus = Bus()
80
81#connect up the l2 cache
82system.l2c = L2(size='4MB', assoc=8)
83system.l2c.cpu_side = system.toL2Bus.master
84system.l2c.mem_side = system.membus.slave
85
86#connect up the cpu and l1s
87cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
88                            L1(size = '32kB', assoc = 4))
89# create the interrupt controller
90cpu.createInterruptController()
91# connect cpu level-1 caches to shared level-2 cache
92cpu.connectAllPorts(system.toL2Bus, system.membus)
93cpu.clock = '2GHz'
94
95root = Root(full_system=True, system=system)
96m5.ticks.setGlobalFrequency('1THz')
97
98