realview-simple-atomic.py revision 8061:08e91664adac
12391SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 28931Sandreas.hansson@arm.com# All rights reserved. 37733SN/A# 47733SN/A# Redistribution and use in source and binary forms, with or without 57733SN/A# modification, are permitted provided that the following conditions are 67733SN/A# met: redistributions of source code must retain the above copyright 77733SN/A# notice, this list of conditions and the following disclaimer; 87733SN/A# redistributions in binary form must reproduce the above copyright 97733SN/A# notice, this list of conditions and the following disclaimer in the 107733SN/A# documentation and/or other materials provided with the distribution; 117733SN/A# neither the name of the copyright holders nor the names of its 127733SN/A# contributors may be used to endorse or promote products derived from 137733SN/A# this software without specific prior written permission. 142391SN/A# 152391SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162391SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172391SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182391SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192391SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202391SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212391SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222391SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232391SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242391SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252391SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262391SN/A# 272391SN/A# Authors: Steve Reinhardt 282391SN/A 292391SN/Aimport m5 302391SN/Afrom m5.objects import * 312391SN/Am5.util.addToPath('../configs/common') 322391SN/Aimport FSConfig 332391SN/A 342391SN/A# -------------------- 352391SN/A# Base L1 Cache 362391SN/A# ==================== 372391SN/A 382391SN/Aclass L1(BaseCache): 392665SN/A latency = '1ns' 402665SN/A block_size = 64 412914SN/A mshrs = 4 428931Sandreas.hansson@arm.com tgts_per_mshr = 8 432391SN/A 442391SN/A# ---------------------- 456329SN/A# Base L2 Cache 466658SN/A# ---------------------- 478232SN/A 488232SN/Aclass L2(BaseCache): 498931Sandreas.hansson@arm.com block_size = 64 503879SN/A latency = '10ns' 519053Sdam.sunwoo@arm.com mshrs = 92 522394SN/A tgts_per_mshr = 16 532391SN/A write_buffers = 8 542391SN/A 558931Sandreas.hansson@arm.com# --------------------- 568931Sandreas.hansson@arm.com# I/O Cache 579053Sdam.sunwoo@arm.com# --------------------- 589053Sdam.sunwoo@arm.comclass IOCache(BaseCache): 592391SN/A assoc = 8 607730SN/A block_size = 64 612391SN/A latency = '50ns' 622391SN/A mshrs = 20 632391SN/A size = '1kB' 649293Sandreas.hansson@arm.com tgts_per_mshr = 12 659293Sandreas.hansson@arm.com addr_range=AddrRange(0, size='128MB') 662391SN/A forward_snoops = False 679293Sandreas.hansson@arm.com 682391SN/A#cpu 692391SN/Acpu = AtomicSimpleCPU(cpu_id=0) 708719SN/A#the system 718931Sandreas.hansson@arm.comsystem = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 728719SN/Asystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 738719SN/Asystem.bridge.filter_ranges_b=[AddrRange(0, size='128MB')] 748719SN/Asystem.iocache = IOCache() 759053Sdam.sunwoo@arm.comsystem.iocache.cpu_side = system.iobus.port 769053Sdam.sunwoo@arm.comsystem.iocache.mem_side = system.membus.port 778719SN/A 789053Sdam.sunwoo@arm.comsystem.cpu = cpu 798719SN/A#create the l1/l2 bus 808719SN/Asystem.toL2Bus = Bus() 819053Sdam.sunwoo@arm.com 828719SN/A#connect up the l2 cache 839053Sdam.sunwoo@arm.comsystem.l2c = L2(size='4MB', assoc=8) 849053Sdam.sunwoo@arm.comsystem.l2c.cpu_side = system.toL2Bus.port 859053Sdam.sunwoo@arm.comsystem.l2c.mem_side = system.membus.port 868719SN/A 879053Sdam.sunwoo@arm.com#connect up the cpu and l1s 888719SN/Acpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 898719SN/A L1(size = '32kB', assoc = 4)) 909053Sdam.sunwoo@arm.com# connect cpu level-1 caches to shared level-2 cache 918719SN/Acpu.connectAllPorts(system.toL2Bus, system.membus) 929053Sdam.sunwoo@arm.comcpu.clock = '2GHz' 939053Sdam.sunwoo@arm.com 949053Sdam.sunwoo@arm.comroot = Root(system=system) 958719SN/Am5.ticks.setGlobalFrequency('1THz') 969053Sdam.sunwoo@arm.com 978719SN/A