realview-simple-atomic.py revision 9263
110859Sandreas.sandberg@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 211840SCurtis.Dunham@arm.com# All rights reserved. 310859Sandreas.sandberg@arm.com# 410859Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 510859Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are 610859Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright 710859Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer; 810859Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright 910859Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 1010859Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution; 1110859Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its 1210859Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from 1310859Sandreas.sandberg@arm.com# this software without specific prior written permission. 1410859Sandreas.sandberg@arm.com# 1510859Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1610859Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1710859Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1810859Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1910859Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2010859Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2110859Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2210859Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2310859Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2410859Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2510859Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2610859Sandreas.sandberg@arm.com# 2710859Sandreas.sandberg@arm.com# Authors: Steve Reinhardt 2810859Sandreas.sandberg@arm.com 2910859Sandreas.sandberg@arm.comimport m5 3010859Sandreas.sandberg@arm.comfrom m5.objects import * 3110859Sandreas.sandberg@arm.comm5.util.addToPath('../configs/common') 3210859Sandreas.sandberg@arm.comimport FSConfig 3310859Sandreas.sandberg@arm.com 3410859Sandreas.sandberg@arm.com# -------------------- 3510859Sandreas.sandberg@arm.com# Base L1 Cache 3610859Sandreas.sandberg@arm.com# ==================== 3710859Sandreas.sandberg@arm.com 3811840SCurtis.Dunham@arm.comclass L1(BaseCache): 3910859Sandreas.sandberg@arm.com hit_latency = '1ns' 4010859Sandreas.sandberg@arm.com response_latency = '1ns' 4110859Sandreas.sandberg@arm.com block_size = 64 4210859Sandreas.sandberg@arm.com mshrs = 4 4310859Sandreas.sandberg@arm.com tgts_per_mshr = 8 4410859Sandreas.sandberg@arm.com is_top_level = True 4510859Sandreas.sandberg@arm.com 4610859Sandreas.sandberg@arm.com# ---------------------- 4710859Sandreas.sandberg@arm.com# Base L2 Cache 4811840SCurtis.Dunham@arm.com# ---------------------- 4910859Sandreas.sandberg@arm.com 5010859Sandreas.sandberg@arm.comclass L2(BaseCache): 5111461Sandreas.sandberg@arm.com block_size = 64 5211461Sandreas.sandberg@arm.com hit_latency = '10ns' 5311461Sandreas.sandberg@arm.com response_latency = '10ns' 5411461Sandreas.sandberg@arm.com mshrs = 92 5511461Sandreas.sandberg@arm.com tgts_per_mshr = 16 5611461Sandreas.sandberg@arm.com write_buffers = 8 5711461Sandreas.sandberg@arm.com 5811461Sandreas.sandberg@arm.com# --------------------- 5911461Sandreas.sandberg@arm.com# I/O Cache 6011461Sandreas.sandberg@arm.com# --------------------- 6111461Sandreas.sandberg@arm.comclass IOCache(BaseCache): 6211461Sandreas.sandberg@arm.com assoc = 8 6311461Sandreas.sandberg@arm.com block_size = 64 6411461Sandreas.sandberg@arm.com hit_latency = '50ns' 6511461Sandreas.sandberg@arm.com response_latency = '50ns' 6611461Sandreas.sandberg@arm.com mshrs = 20 6711461Sandreas.sandberg@arm.com size = '1kB' 6811461Sandreas.sandberg@arm.com tgts_per_mshr = 12 6911461Sandreas.sandberg@arm.com addr_ranges = [AddrRange(0, size='256MB')] 7011838SCurtis.Dunham@arm.com forward_snoops = False 7111461Sandreas.sandberg@arm.com 7211462Sandreas.sandberg@arm.com#cpu 7311462Sandreas.sandberg@arm.comcpu = AtomicSimpleCPU(cpu_id=0) 7411461Sandreas.sandberg@arm.com#the system 7511461Sandreas.sandberg@arm.comsystem = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 7611461Sandreas.sandberg@arm.comsystem.iocache = IOCache() 7711461Sandreas.sandberg@arm.comsystem.iocache.cpu_side = system.iobus.master 7811461Sandreas.sandberg@arm.comsystem.iocache.mem_side = system.membus.slave 7911461Sandreas.sandberg@arm.com 8011461Sandreas.sandberg@arm.comsystem.cpu = cpu 8111461Sandreas.sandberg@arm.com#create the l1/l2 bus 8211461Sandreas.sandberg@arm.comsystem.toL2Bus = CoherentBus() 8311461Sandreas.sandberg@arm.com 8411461Sandreas.sandberg@arm.com#connect up the l2 cache 8511461Sandreas.sandberg@arm.comsystem.l2c = L2(size='4MB', assoc=8) 8611461Sandreas.sandberg@arm.comsystem.l2c.cpu_side = system.toL2Bus.master 8711461Sandreas.sandberg@arm.comsystem.l2c.mem_side = system.membus.slave 8811461Sandreas.sandberg@arm.com 8911461Sandreas.sandberg@arm.com#connect up the cpu and l1s 9011461Sandreas.sandberg@arm.comcpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 9111461Sandreas.sandberg@arm.com L1(size = '32kB', assoc = 4)) 9211461Sandreas.sandberg@arm.com# create the interrupt controller 9311461Sandreas.sandberg@arm.comcpu.createInterruptController() 9411461Sandreas.sandberg@arm.com# connect cpu level-1 caches to shared level-2 cache 9511461Sandreas.sandberg@arm.comcpu.connectAllPorts(system.toL2Bus, system.membus) 9611461Sandreas.sandberg@arm.comcpu.clock = '2GHz' 9711461Sandreas.sandberg@arm.com 9811461Sandreas.sandberg@arm.comroot = Root(full_system=True, system=system) 9911461Sandreas.sandberg@arm.comm5.ticks.setGlobalFrequency('1THz') 10011461Sandreas.sandberg@arm.com 10111461Sandreas.sandberg@arm.com