realview-simple-atomic.py revision 8134
17735SAli.Saidi@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
27735SAli.Saidi@ARM.com# All rights reserved.
37735SAli.Saidi@ARM.com#
47735SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without
57735SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are
67735SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright
77735SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer;
87735SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright
97735SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the
107735SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution;
117735SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its
127735SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from
137735SAli.Saidi@ARM.com# this software without specific prior written permission.
147735SAli.Saidi@ARM.com#
157735SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
167735SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
177735SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
187735SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
197735SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
207735SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
217735SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
227735SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
237735SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
247735SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
257735SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
267735SAli.Saidi@ARM.com#
277735SAli.Saidi@ARM.com# Authors: Steve Reinhardt
287735SAli.Saidi@ARM.com
297735SAli.Saidi@ARM.comimport m5
307735SAli.Saidi@ARM.comfrom m5.objects import *
317735SAli.Saidi@ARM.comm5.util.addToPath('../configs/common')
327735SAli.Saidi@ARM.comimport FSConfig
337735SAli.Saidi@ARM.com
347735SAli.Saidi@ARM.com# --------------------
357735SAli.Saidi@ARM.com# Base L1 Cache
367735SAli.Saidi@ARM.com# ====================
377735SAli.Saidi@ARM.com
387735SAli.Saidi@ARM.comclass L1(BaseCache):
397735SAli.Saidi@ARM.com    latency = '1ns'
407735SAli.Saidi@ARM.com    block_size = 64
417735SAli.Saidi@ARM.com    mshrs = 4
427735SAli.Saidi@ARM.com    tgts_per_mshr = 8
438134SAli.Saidi@ARM.com    is_top_level = True
447735SAli.Saidi@ARM.com
457735SAli.Saidi@ARM.com# ----------------------
467735SAli.Saidi@ARM.com# Base L2 Cache
477735SAli.Saidi@ARM.com# ----------------------
487735SAli.Saidi@ARM.com
497735SAli.Saidi@ARM.comclass L2(BaseCache):
507735SAli.Saidi@ARM.com    block_size = 64
517735SAli.Saidi@ARM.com    latency = '10ns'
527735SAli.Saidi@ARM.com    mshrs = 92
537735SAli.Saidi@ARM.com    tgts_per_mshr = 16
547735SAli.Saidi@ARM.com    write_buffers = 8
557735SAli.Saidi@ARM.com
567735SAli.Saidi@ARM.com# ---------------------
577735SAli.Saidi@ARM.com# I/O Cache
587735SAli.Saidi@ARM.com# ---------------------
597735SAli.Saidi@ARM.comclass IOCache(BaseCache):
607735SAli.Saidi@ARM.com    assoc = 8
617735SAli.Saidi@ARM.com    block_size = 64
627735SAli.Saidi@ARM.com    latency = '50ns'
637735SAli.Saidi@ARM.com    mshrs = 20
647735SAli.Saidi@ARM.com    size = '1kB'
657735SAli.Saidi@ARM.com    tgts_per_mshr = 12
667735SAli.Saidi@ARM.com    addr_range=AddrRange(0, size='128MB')
677735SAli.Saidi@ARM.com    forward_snoops = False
687735SAli.Saidi@ARM.com
697735SAli.Saidi@ARM.com#cpu
707735SAli.Saidi@ARM.comcpu = AtomicSimpleCPU(cpu_id=0)
717735SAli.Saidi@ARM.com#the system
728061SAli.Saidi@ARM.comsystem = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
737735SAli.Saidi@ARM.comsystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
747735SAli.Saidi@ARM.comsystem.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
757735SAli.Saidi@ARM.comsystem.iocache = IOCache()
767735SAli.Saidi@ARM.comsystem.iocache.cpu_side = system.iobus.port
777735SAli.Saidi@ARM.comsystem.iocache.mem_side = system.membus.port
787735SAli.Saidi@ARM.com
797735SAli.Saidi@ARM.comsystem.cpu = cpu
807735SAli.Saidi@ARM.com#create the l1/l2 bus
817735SAli.Saidi@ARM.comsystem.toL2Bus = Bus()
827735SAli.Saidi@ARM.com
837735SAli.Saidi@ARM.com#connect up the l2 cache
847735SAli.Saidi@ARM.comsystem.l2c = L2(size='4MB', assoc=8)
857735SAli.Saidi@ARM.comsystem.l2c.cpu_side = system.toL2Bus.port
867735SAli.Saidi@ARM.comsystem.l2c.mem_side = system.membus.port
877735SAli.Saidi@ARM.com
887735SAli.Saidi@ARM.com#connect up the cpu and l1s
897735SAli.Saidi@ARM.comcpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
907735SAli.Saidi@ARM.com                            L1(size = '32kB', assoc = 4))
917735SAli.Saidi@ARM.com# connect cpu level-1 caches to shared level-2 cache
927876Sgblack@eecs.umich.educpu.connectAllPorts(system.toL2Bus, system.membus)
937735SAli.Saidi@ARM.comcpu.clock = '2GHz'
947735SAli.Saidi@ARM.com
957735SAli.Saidi@ARM.comroot = Root(system=system)
967735SAli.Saidi@ARM.comm5.ticks.setGlobalFrequency('1THz')
977735SAli.Saidi@ARM.com
98