realview-o3-checker.py revision 9315:2e00867b5001
1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Geoffrey Blake 37 38import m5 39from m5.objects import * 40m5.util.addToPath('../configs/common') 41import FSConfig 42from Caches import * 43 44#cpu 45cpu = DerivO3CPU(cpu_id=0) 46#the system 47system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 48 49system.cpu = cpu 50#connect up the checker 51cpu.addCheckerCpu() 52 53#create the iocache 54system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')]) 55system.iocache.cpu_side = system.iobus.master 56system.iocache.mem_side = system.membus.slave 57 58#connect up the cpu and caches 59cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), 60 L1Cache(size = '32kB', assoc = 4), 61 L2Cache(size = '4MB', assoc = 8)) 62# create the interrupt controller 63cpu.createInterruptController() 64# connect cpu and caches to the rest of the system 65cpu.connectAllPorts(system.membus) 66# set the cpu clock along with the caches and l1-l2 bus 67cpu.clock = '2GHz' 68 69root = Root(full_system=True, system=system) 70m5.ticks.setGlobalFrequency('1THz') 71 72