realview-o3-checker.py revision 9288:3d6da8559605
1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Geoffrey Blake 37 38import m5 39from m5.objects import * 40m5.util.addToPath('../configs/common') 41import FSConfig 42 43 44# -------------------- 45# Base L1 Cache 46# ==================== 47 48class L1(BaseCache): 49 hit_latency = 2 50 response_latency = 2 51 block_size = 64 52 mshrs = 4 53 tgts_per_mshr = 20 54 is_top_level = True 55 56# ---------------------- 57# Base L2 Cache 58# ---------------------- 59 60class L2(BaseCache): 61 block_size = 64 62 hit_latency = 20 63 response_latency = 20 64 mshrs = 92 65 tgts_per_mshr = 16 66 write_buffers = 8 67 68# --------------------- 69# I/O Cache 70# --------------------- 71class IOCache(BaseCache): 72 assoc = 8 73 block_size = 64 74 hit_latency = 50 75 response_latency = 50 76 mshrs = 20 77 size = '1kB' 78 tgts_per_mshr = 12 79 addr_ranges = [AddrRange(0, size='256MB')] 80 forward_snoops = False 81 82#cpu 83cpu = DerivO3CPU(cpu_id=0) 84#the system 85system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 86 87system.cpu = cpu 88#connect up the checker 89cpu.addCheckerCpu() 90 91#create the iocache 92system.iocache = IOCache(clock = '1GHz') 93system.iocache.cpu_side = system.iobus.master 94system.iocache.mem_side = system.membus.slave 95 96#connect up the cpu and caches 97cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 98 L1(size = '32kB', assoc = 4), 99 L2(size = '4MB', assoc = 8)) 100# create the interrupt controller 101cpu.createInterruptController() 102# connect cpu and caches to the rest of the system 103cpu.connectAllPorts(system.membus) 104# set the cpu clock along with the caches and l1-l2 bus 105cpu.clock = '2GHz' 106 107root = Root(full_system=True, system=system) 108m5.ticks.setGlobalFrequency('1THz') 109 110