realview-o3-checker.py revision 9263:066099902102 
1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
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15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
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20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35#
36# Authors: Geoffrey Blake
37
38import m5
39from m5.objects import *
40m5.util.addToPath('../configs/common')
41import FSConfig
42
43
44# --------------------
45# Base L1 Cache
46# ====================
47
48class L1(BaseCache):
49    hit_latency = '1ns'
50    response_latency = '1ns'
51    block_size = 64
52    mshrs = 4
53    tgts_per_mshr = 20
54    is_top_level = True
55
56# ----------------------
57# Base L2 Cache
58# ----------------------
59
60class L2(BaseCache):
61    block_size = 64
62    hit_latency = '10ns'
63    response_latency = '10ns'
64    mshrs = 92
65    tgts_per_mshr = 16
66    write_buffers = 8
67
68# ---------------------
69# I/O Cache
70# ---------------------
71class IOCache(BaseCache):
72    assoc = 8
73    block_size = 64
74    hit_latency = '50ns'
75    response_latency = '50ns'
76    mshrs = 20
77    size = '1kB'
78    tgts_per_mshr = 12
79    addr_ranges = [AddrRange(0, size='256MB')]
80    forward_snoops = False
81
82#cpu
83cpu = DerivO3CPU(cpu_id=0)
84#the system
85system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
86
87system.cpu = cpu
88#create the l1/l2 bus
89system.toL2Bus = CoherentBus()
90system.iocache = IOCache()
91system.iocache.cpu_side = system.iobus.master
92system.iocache.mem_side = system.membus.slave
93
94
95#connect up the l2 cache
96system.l2c = L2(size='4MB', assoc=8)
97system.l2c.cpu_side = system.toL2Bus.master
98system.l2c.mem_side = system.membus.slave
99
100#connect up the checker
101cpu.addCheckerCpu()
102#connect up the cpu and l1s
103cpu.createInterruptController()
104cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
105                            L1(size = '32kB', assoc = 4))
106# connect cpu level-1 caches to shared level-2 cache
107cpu.connectAllPorts(system.toL2Bus, system.membus)
108cpu.clock = '2GHz'
109
110root = Root(full_system=True, system=system)
111m5.ticks.setGlobalFrequency('1THz')
112
113