pc-simple-timing-ruby.py revision 11682
18968Snilay@cs.wisc.edu# Copyright (c) 2012 Mark D. Hill and David A. Wood 28968Snilay@cs.wisc.edu# All rights reserved. 38968Snilay@cs.wisc.edu# 48968Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 58968Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 68968Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 78968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 88968Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 98968Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 108968Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 118968Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 128968Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 138968Snilay@cs.wisc.edu# this software without specific prior written permission. 148968Snilay@cs.wisc.edu# 158968Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168968Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178968Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188968Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198968Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208968Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218968Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228968Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238968Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248968Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258968Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268968Snilay@cs.wisc.edu# 278968Snilay@cs.wisc.edu# Authors: Nilay Vaish 288968Snilay@cs.wisc.edu 298968Snilay@cs.wisc.eduimport m5, os, optparse, sys 308968Snilay@cs.wisc.edufrom m5.objects import * 3111670Sandreas.hansson@arm.comm5.util.addToPath('../configs/') 3211682Sandreas.hansson@arm.comfrom common.Benchmarks import SysConfig 3311682Sandreas.hansson@arm.comfrom common import FSConfig 3411670Sandreas.hansson@arm.comfrom ruby import Ruby 3511682Sandreas.hansson@arm.comfrom common import Options 368968Snilay@cs.wisc.edu 378968Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 388968Snilay@cs.wisc.eduparser = optparse.OptionParser() 398968Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 408968Snilay@cs.wisc.eduRuby.define_options(parser) 418968Snilay@cs.wisc.edu(options, args) = parser.parse_args() 428968Snilay@cs.wisc.edu 438968Snilay@cs.wisc.edu# Set the default cache size and associativity to be very small to encourage 448968Snilay@cs.wisc.edu# races between requests and writebacks. 458968Snilay@cs.wisc.eduoptions.l1d_size="32kB" 468968Snilay@cs.wisc.eduoptions.l1i_size="32kB" 478968Snilay@cs.wisc.eduoptions.l2_size="4MB" 488968Snilay@cs.wisc.eduoptions.l1d_assoc=2 498968Snilay@cs.wisc.eduoptions.l1i_assoc=2 508968Snilay@cs.wisc.eduoptions.l2_assoc=2 518968Snilay@cs.wisc.eduoptions.num_cpus = 2 528968Snilay@cs.wisc.edu 538968Snilay@cs.wisc.edu#the system 548968Snilay@cs.wisc.edumdesc = SysConfig(disk = 'linux-x86.img') 559826Sandreas.hansson@arm.comsystem = FSConfig.makeLinuxX86System('timing', options.num_cpus, 569802Snilay@cs.wisc.edu mdesc=mdesc, Ruby=True) 579827Sakash.bagdia@arm.com# Dummy voltage domain for all our clock domains 589827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 599793Sakash.bagdia@arm.com 608968Snilay@cs.wisc.edusystem.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 619827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 629827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 639827Sakash.bagdia@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 649827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 659802Snilay@cs.wisc.edusystem.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) 669802Snilay@cs.wisc.edu for i in xrange(options.num_cpus)] 679793Sakash.bagdia@arm.com 6810519Snilay@cs.wisc.eduRuby.create_system(options, True, system, system.iobus, system._dma_ports) 698968Snilay@cs.wisc.edu 709793Sakash.bagdia@arm.com# Create a seperate clock domain for Ruby 719827Sakash.bagdia@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 729827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 739793Sakash.bagdia@arm.com 7410519Snilay@cs.wisc.edu# Connect the ruby io port to the PIO bus, 7510519Snilay@cs.wisc.edu# assuming that there is just one such port. 7610519Snilay@cs.wisc.edusystem.iobus.master = system.ruby._io_port.slave 7710519Snilay@cs.wisc.edu 788968Snilay@cs.wisc.edufor (i, cpu) in enumerate(system.cpu): 798968Snilay@cs.wisc.edu # create the interrupt controller 808968Snilay@cs.wisc.edu cpu.createInterruptController() 818968Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 8210120Snilay@cs.wisc.edu cpu.icache_port = system.ruby._cpu_ports[i].slave 8310120Snilay@cs.wisc.edu cpu.dcache_port = system.ruby._cpu_ports[i].slave 8410120Snilay@cs.wisc.edu cpu.itb.walker.port = system.ruby._cpu_ports[i].slave 8510120Snilay@cs.wisc.edu cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave 8610519Snilay@cs.wisc.edu 8711150Smitch.hayenga@arm.com cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master 8811150Smitch.hayenga@arm.com cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave 8911150Smitch.hayenga@arm.com cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master 908968Snilay@cs.wisc.edu 918968Snilay@cs.wisc.eduroot = Root(full_system = True, system = system) 928968Snilay@cs.wisc.edum5.ticks.setGlobalFrequency('1THz') 93