pc-simple-atomic.py revision 9310:aa7bf10e822a
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26166Ssteve.reinhardt@amd.com# All rights reserved. 36166Ssteve.reinhardt@amd.com# 46166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 56166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 66166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 76166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 86166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 96166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 106166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 116166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 126166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 136166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 146166Ssteve.reinhardt@amd.com# 156166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266166Ssteve.reinhardt@amd.com# 276166Ssteve.reinhardt@amd.com# Authors: Steve Reinhardt 286166Ssteve.reinhardt@amd.com 296166Ssteve.reinhardt@amd.comimport m5 306166Ssteve.reinhardt@amd.comfrom m5.objects import * 316166Ssteve.reinhardt@amd.comm5.util.addToPath('../configs/common') 326166Ssteve.reinhardt@amd.comfrom Benchmarks import SysConfig 336166Ssteve.reinhardt@amd.comimport FSConfig 346166Ssteve.reinhardt@amd.comfrom Caches import * 356166Ssteve.reinhardt@amd.com 366289Snate@binkert.orgmem_size = '128MB' 376870Sdrh5@cs.wisc.edu 386289Snate@binkert.org#cpu 396166Ssteve.reinhardt@amd.comcpu = AtomicSimpleCPU(cpu_id=0) 406289Snate@binkert.org#the system 416166Ssteve.reinhardt@amd.commdesc = SysConfig(disk = 'linux-x86.img') 426166Ssteve.reinhardt@amd.comsystem = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc) 436166Ssteve.reinhardt@amd.comsystem.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 447876Sgblack@eecs.umich.edu 456166Ssteve.reinhardt@amd.comsystem.cpu = cpu 466166Ssteve.reinhardt@amd.com 476166Ssteve.reinhardt@amd.com#create the iocache 486166Ssteve.reinhardt@amd.comsystem.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) 496166Ssteve.reinhardt@amd.comsystem.iocache.cpu_side = system.iobus.master 506166Ssteve.reinhardt@amd.comsystem.iocache.mem_side = system.membus.slave 516166Ssteve.reinhardt@amd.com 526166Ssteve.reinhardt@amd.com#connect up the cpu and caches 536166Ssteve.reinhardt@amd.comcpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 546166Ssteve.reinhardt@amd.com L1(size = '32kB', assoc = 4), 558801Sgblack@eecs.umich.edu L2(size = '4MB', assoc = 8), 566166Ssteve.reinhardt@amd.com PageTableWalkerCache(), 57 PageTableWalkerCache()) 58# create the interrupt controller 59cpu.createInterruptController() 60# connect cpu and caches to the rest of the system 61cpu.connectAllPorts(system.membus) 62# set the cpu clock along with the caches and l1-l2 bus 63cpu.clock = '2GHz' 64 65root = Root(full_system=True, system=system) 66m5.ticks.setGlobalFrequency('1THz') 67 68