pc-simple-atomic.py revision 7926 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34
35mem_size = '128MB'
36
37# --------------------
38# Base L1 Cache
39# ====================
40
41class L1(BaseCache):
42    latency = '1ns'
43    block_size = 64
44    mshrs = 4
45    tgts_per_mshr = 8
46
47# ----------------------
48# Base L2 Cache
49# ----------------------
50
51class L2(BaseCache):
52    block_size = 64
53    latency = '10ns'
54    mshrs = 92
55    tgts_per_mshr = 16
56    write_buffers = 8
57
58# ---------------------
59# Page table walker cache
60# ---------------------
61class PageTableWalkerCache(BaseCache):
62    assoc = 2
63    block_size = 64
64    latency = '1ns'
65    mshrs = 10
66    size = '1kB'
67    tgts_per_mshr = 12
68
69# ---------------------
70# I/O Cache
71# ---------------------
72class IOCache(BaseCache):
73    assoc = 8
74    block_size = 64
75    latency = '50ns'
76    mshrs = 20
77    size = '1kB'
78    tgts_per_mshr = 12
79    addr_range = AddrRange(0, size=mem_size)
80    forward_snoops = False
81
82#cpu
83cpu = AtomicSimpleCPU(cpu_id=0)
84#the system
85mdesc = SysConfig(disk = 'linux-x86.img')
86system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
87system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
88system.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)]
89system.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)]
90system.iocache = IOCache(addr_range=mem_size)
91system.iocache.cpu_side = system.iobus.port
92system.iocache.mem_side = system.membus.port
93
94system.cpu = cpu
95#create the l1/l2 bus
96system.toL2Bus = Bus()
97
98#connect up the l2 cache
99system.l2c = L2(size='4MB', assoc=8)
100system.l2c.cpu_side = system.toL2Bus.port
101system.l2c.mem_side = system.membus.port
102
103#connect up the cpu and l1s
104cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
105                            L1(size = '32kB', assoc = 4),
106                            PageTableWalkerCache(),
107                            PageTableWalkerCache())
108# connect cpu level-1 caches to shared level-2 cache
109cpu.connectAllPorts(system.toL2Bus, system.membus)
110cpu.clock = '2GHz'
111
112root = Root(system=system)
113m5.ticks.setGlobalFrequency('1THz')
114
115